TWI725425B - 封裝件及其形成的方法 - Google Patents

封裝件及其形成的方法 Download PDF

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TWI725425B
TWI725425B TW108116774A TW108116774A TWI725425B TW I725425 B TWI725425 B TW I725425B TW 108116774 A TW108116774 A TW 108116774A TW 108116774 A TW108116774 A TW 108116774A TW I725425 B TWI725425 B TW I725425B
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Taiwan
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metal
layer
conductive features
forming
etching
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TW108116774A
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TW202002064A (zh
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郭宏瑞
余振華
蔡惠榕
謝昀蓁
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台灣積體電路製造股份有限公司
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Abstract

一種形成封裝件方法包含以下步驟。以包封材料包封裝 置晶粒。平坦化裝置晶粒及包封材料。形成電性耦接至裝置晶粒的第一多個導電特徵。形成第一多個導電構件的步驟包含沈積及蝕刻製程，所述製程包含以下步驟。沈積毯覆式含銅層。在毯覆式含銅層上方形成圖案化光阻。蝕刻毯覆式含銅層以將圖案化光阻的圖案轉移至毯覆式含銅層中。

Description

封裝件及其形成的方法
本發明的實施例是有關於一種封裝件及其形成的方法。
隨著半導體技術的發展，半導體晶片/晶粒正變得愈來愈小。同時，更多功能需要整合至半導體晶粒中。因此，半導體晶粒需要具有封裝於較小區域中的數目越來越大的輸入/輸出(I/O)接墊，且輸入/輸出接墊的密度隨時間推移而快速增加。因此，半導體晶粒的封裝變得更困難，此不利地影響封裝的良率。
習知封裝技術可劃分成兩種類別。在第一類別中，封裝晶圓上的晶粒，隨後進行鋸割。此封裝技術具有一些優勢的特徵，諸如較大輸送量(throughput)及較低成本。另外，需要較少底部填充料或模製化合物。然而，此封裝技術亦具有缺點。由於晶粒的大小變得越來越小，且各別封裝僅可能為扇入型封裝，其中每一晶粒的輸入/輸出接墊被限制在各別晶粒的表面正上方的區域。隨著晶粒的區域受限，輸入/輸出接墊的數目由於輸入/輸出接墊的間距的限制而受到限制。若接墊的間距減小，則可能出現焊橋(solder bridge)。另外，在固定球尺寸要求下，焊料球必須具有確定的大 小，此舉又限制可封裝於晶粒的表面上的焊料球的數目。
在封裝的另一類別中，自晶圓鋸割晶粒，隨後進行封裝。此封裝技術的優勢特徵為形成扇出型封裝的可能性，此意謂可將晶粒上的輸入/輸出接墊重新分配至比晶粒更大的區域，且因此可增大封裝於晶粒的表面上的輸入/輸出接墊的數目。此封裝技術的另一優勢特徵為封裝「已知良好晶粒」且捨棄有缺陷的晶粒，且因此不會在有缺陷的晶粒上浪費成本及精力。
在扇出型封裝中，裝置晶粒包封於模製化合物中，所述模製化合物接著被平坦化以暴露裝置晶粒。介電層形成於裝置晶粒上方。重佈線路形成於介電層中以連接至裝置晶粒。扇出型封裝亦可包含穿透模製化合物的穿孔。重佈線路的形成包含形成晶種層、形成經圖案化光阻以及將重佈線路鍍覆至經圖案化光阻中的開口中。
一種形成封裝件的方法包含以下步驟。以包封材料包封裝置晶粒。將裝置晶粒及包封材料平面化。形成電性耦接至裝置晶粒的第一多個導電特徵，其中形成第一多個導電特徵包括沈積及蝕刻製程。所述沈積及蝕刻製程包括以下步驟。沈積毯覆式含銅層。在毯覆式含銅層上方形成圖案化光阻。蝕刻毯覆式含銅層以將圖案化光阻的圖案轉移至毯覆式含銅層中。
一種形成封裝件的方法包含以下步驟。形成多個通孔，所述形成包括沈積第一黏著層，在第一黏著層上方沈積毯覆式含銅層，在毯覆式含銅層上方形成第一圖案化光阻以及蝕刻毯覆式含 銅層及第一黏著層。沈積第一介電層以埋置多個通孔。對第一介電層及多個通孔執行第一平坦化。形成多根金屬線路，所述形成包括在多個通孔上方沈積金屬晶種層且使金屬晶種層接觸多個通孔，在金屬晶種層上方沈積第二圖案化光阻，在第二圖案化光阻中鍍覆金屬區域，移除第二圖案化光阻以及蝕刻金屬晶種層的部分。沈積第二介電層以埋置多根金屬線路。以及對第二介電層及金屬區域執行第二平坦化。
一種封裝件包括裝置晶粒、第一多個導電特徵、第二多個導電特徵。第一多個導電特徵位於裝置晶粒上方且電性耦接至裝置晶粒，其中第一多個導電特徵具有第一傾斜角小於85度的第一側壁。第二多個導電特徵位於第一多個導電特徵上方且電性耦接至第一多個導電特徵，其中第二多個導電特徵具有第二傾斜角大於85度且等於或小於約90度的第二側壁。
20:載體
22:離型膜
24:介電緩衝層
26、64A、221:金屬晶種層
28:光阻
30、68、228、232:開口
32:金屬柱
32-32、34-34:平面交叉線
34:晶粒貼合膜
36:裝置晶粒
40:底層金屬墊
42:金屬柱
43:鈍化層
44:頂部介電層
48A:基礎材料
48B:填充劑顆粒
48、126:包封材料
50A、58A、74A、222、222':黏著層
50B、58B、64B、74B、224':金屬區域
50、64、110、114、120:通孔
52:虛線
56、72、76、108、116、122:介電層
58、106:金屬線路
60:虛線
66、226:圖案化光阻
70:虛線
74、230:導電特徵
78:接合墊
80:電性連接件
82:表面黏著裝置
84'、86、100、102:封裝件
84:封裝件
88:封裝基底
89、94:封裝組件
90:裝置晶粒
92:底部填充料
95:焊料區
104:重佈線路結構
112、118:金屬線路
220:底座結構
223:含銅層
224:毯覆式含銅層
225、225':硬式罩幕
226A:中間部分
300:製程流程
302、304、306、308、310、312、314、316、318、320、322、324、326:製程
H1/W1:縱橫比
H1:高度
P1:間距
R224、R226:蝕刻速率
R224/R226:蝕刻選擇性
S1:間隔
W1、W2、W2'、W3、W3':寬度
α1、α2、α3:傾斜角
根據結合附圖閱讀的以下詳細描述最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種構件未按比例繪製。事實上，可出於論述清楚起見，而任意地增加或縮減各種構件的尺寸。
圖1至圖3示出根據一些實施例的使用光阻(PR)蝕刻製程形成導電構件的中間階段的橫截面視圖。
圖4至圖8示出根據一些實施例的使用硬式罩幕(HM)蝕刻製程形成導電構件的中間階段的橫截面視圖。
圖9至圖12示出根據一些實施例的經由光阻輔助鍍覆製程 形成導電構件的中間階段的橫截面視圖。
圖13及圖14分別示出根據一些實施例的用於使用光阻輔助鍍覆製程形成細長導線的光阻的俯視圖及橫截面視圖。
圖15及圖16分別示出根據一些實施例的用於使用光阻輔助鍍覆製程形成通孔的光阻的俯視圖及橫截面視圖。
圖17至圖32示出根據一些實施例的使用重佈線路(Redistribution-Line；RDL)最後製程(last process)形成封裝的中間階段的橫截面視圖。
圖33及圖34示出根據一些實施例的使用重佈線路第一製程形成封裝的中間階段的橫截面視圖。
圖35示出根據一些實施例的用於形成封裝的製程流程。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及配置的特定實例以簡化本揭露。當然，這些組件及配置僅為實例且不意欲為限制性的。舉例而言，在以下描述中，第一構件於第二構件上方或上的形成可包含第一構件及第二構件直接接觸形成的實施例，且亦可包含其他構件可在第一構件與第二構件之間形成使得第一構件及第二構件可不直接接觸的實施例。另外，本揭露可在各種實例中重複附圖標號及/或字母。此重複是出於簡化及清楚的目的，且本身並不指示所論述的各種實施例及/或組態之間的關係。
另外，在本文中為了易於描述，可使用諸如「下覆(underlying)」、「在...下方(below)」、「下部(lower)」、「上覆 (overlying)」、「上部(upper)」以及類似術語的空間相對術語來描述如在圖式中所示出的一個元件或構件與另一元件或構件的關係。除圖式中所描繪的定向之外，空間相對術語還意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞可同樣相應地進行解釋。
根據各種例示性實施例提供積體扇出型(Integrated Fan-Out；InFO)封裝件及其形成方法。根據一些實施例說明形成積體扇出型封裝件的中間階段。論述一些實施例的一些變型。貫穿各視圖及說明性實施例，相同的附圖標號用以表示相同元件。
圖1至圖12示出可用於在封裝中形成導電特徵(諸如重佈線路(重佈線路包含金屬線路及通孔)及金屬墊)的多個候選製程。圖1至圖3示出第一形成製程(亦稱作PR蝕刻製程，其中術語「PR」表示「光阻」)。圖4至圖8示出第二形成製程(亦稱作HM蝕刻製程，其中術語「HM」表示「硬式罩幕」)。圖9至圖12示出第三形成製程(亦稱作PR輔助鍍覆製程)。另外，光阻蝕刻製程及硬式罩幕蝕刻製程獨立且統稱為沈積及蝕刻製程。應瞭解，在封裝中形成導電特徵時，根據需求、材料以及結構，不同製程可用於形成相同封裝中的導電特徵的不同層，以便達成諸如改善可靠性的最佳化結果而不會不必要地增加製造成本。
圖1至圖3示出根據本揭露的一些實施例的使用光阻蝕刻製程形成導電特徵。此製程可用於形成精細間距的導電特徵。應瞭解，術語「精細間距」是相對於「大間距」的術語，且精細間距的導電特徵與大間距的導電特徵之間的間距差與特定製程、結構 以及所述結構的材料相關。另外，「精細間距」與「大間距」之間的閾值間距(threshold pitch)可受形成製程所使用的光阻影響。根據本揭露的一些實施例，區分精細間距及大間距的閾值間距在約0.1微米與約4微米之間的範圍內。舉例而言，閾值間距可為約4微米。
參考圖1，形成底座結構220。底座結構220表示能於其上方形成導電特徵的任何結構，且不示出底座結構220的細節。底座結構220可包含導電特徵及介電層，其可為重佈線路、裝置晶粒、封裝或類似者的部分。根據本揭露的一些實施例，底座結構220可表示圖21、圖23、圖24以及圖27中所繪示的結構及圖33中的中間結構中的任一者。根據本揭露的一些實施例，底座結構220具有平坦的頂部表面。根據本揭露的替代性實施例，底座結構220具有非平坦頂部表面。
根據本揭露的一些實施例，黏著層222形成於底座結構220上方。根據本揭露的其他實施例，省略黏著層222。因此，層222在圖1中以虛線示出。黏著層222可包含不同於銅的金屬，且可由鈦、鉭、氮化鈦、氮化鉭或類似者形成。黏著層222可形成為毯覆層，且可使用物理氣相沈積(Physical Vapor Deposition；PVD)、化學氣相沈積(Chemical Vapor Deposition；CVD)、電漿增強型化學氣相沈積(Plasma-Enhanced Chemical Vapor Deposition；PECVD)或類似者來沈積。毯覆式含銅層224形成於底座結構220上方及黏著層222上方(若形成的話)。毯覆式含銅層224可由實質上純銅或銅合金形成，及因此替代性地被稱作含銅層，然而此金屬層(毯覆式含銅層224)可由其他材料形成，諸如鋁、鎳或類似者。 圖案化光阻226形成於黏著層222上方，且開口228例如經由曝光及顯影形成於圖案化光阻226中。
根據一些實施例，圖案化光阻226包含在俯視圖中具有長條形狀的一些部分。圖案化光阻226可具有小於約1.5的縱橫比H1/W1，且根據一些例示性實施例，縱橫比可在約1.0與約1.5之間的範圍內。根據一些實施例，圖案化光阻226的部分的寬度W1可在約0.3微米與約2微米之間的範圍內。圖案化光阻226的相鄰部分之間的間隔S1可在約0.3微米與約2微米之間的範圍內。高度H1可在約0.45微米與約3微米之間的範圍內。在低縱橫比(aspect ratio)的情況下，圖案化光阻226(尤其是窄的那些部分)將不會不利地塌陷。
參考圖2，執行乾式蝕刻(由箭頭表示)製程以蝕刻毯覆式含銅層224，且毯覆式含銅層224的剩餘部分被稱作金屬區域224'。蝕刻可使用製程氣體執行，所述製程氣體包含(但不限於)氬氣、氮氣、氟基氣體或其組合。在蝕刻中，圖案化光阻226亦被蝕刻/消耗。假定圖案化光阻226的蝕刻速率為R226，且毯覆式含銅層224的蝕刻速率為R224，則蝕刻選擇性R224/R226可被調節。蝕刻選擇性的調節可經由調節製程氣體的組合、圖案化光阻226的組成及/或蝕刻製程條件來進行。蝕刻選擇性的調節導致金屬區域224'的側壁傾斜，且金屬區域224'具有梯形形狀的橫截面視圖，其中底側比對應的頂側更長。舉例而言，傾斜角α1可調節至期望的值，其可小於約85度或小於約80度。傾斜角α1可在約60度與約85度之間的範圍內，且可在約65度與80度之間的範圍內。具有底側比頂側更長的導電特徵有利於導電特徵與周圍介 電層的黏合。舉例而言，在底側比頂側更長的情況下，黏著層的剩餘部分(圖3)相較底側等於或小於對應的頂側的情況具有更大的面積，且因此提高金屬區域224'與底座結構220的黏著力。另外，使底側比對應的頂側更長亦可提高金屬區域224'與介電層的黏著力，所述介電層將設置於與金屬區域224'相同的水平處。
在蝕刻毯覆式含銅層224之後，暴露黏著層222，且接著蝕刻。圖案化光阻226亦在蝕刻黏著層222之前或之後被移除。黏著層222可經由濕式蝕刻或乾式蝕刻進行蝕刻。選擇蝕刻化學製品/溶液以侵蝕黏著層222，且不侵蝕金屬區域224'。蝕刻化學製品/溶液可包含氫氟酸(HF)溶液，氫氟酸/雙氧水(HF/H2O2)、雙氧水(具有一些其他添加劑)、碳酸氫鈉(NaHCO3)、氫氧化鈉(NaOH)的混合物，碳酸氫鈉/氫氧化鈉的混合物，碳酸氫鈉/氫氧化鈉/雙氧水的混合物或鹼金屬氫氧化物水溶液。鹼金屬氫氧化物水溶液可為氫氧化鈉溶液、氫氧化鉀(KOH)溶液或類似者。黏著層222的剩餘部分表示為黏著層222'，如圖3中所繪示。黏著層222'及金屬區域224'組合稱作導電特徵230。
圖4至圖6示出用於形成具有豎直或實質上豎直側壁的導電特徵230的方法，例如，其中傾斜角α2(圖7)大於約80度且等於或小於90度。參考圖4，形成底座結構220，隨後沈積黏著層222、毯覆式含銅層(亦稱作含銅層)224以及圖案化光阻226。另外，硬式罩幕225形成於毯覆式含銅層224上方。根據本揭露的一些實施例，硬式罩幕225由與黏著層222的材料相同的材料形成，以使得用於形成硬式罩幕225的製程可在與黏著層222相同的生產器具中執行，其間無真空破壞(vacuum break)。因此可 減少生產成本。圖案化光阻226的例示性尺寸及間隔可類似於參考圖1所論述的尺寸及間隔，且不在本文中重複。圖案化光阻226的縱橫比低，例如在約1.0與約1.5之間的範圍內，以使得圖案化光阻226不會遭受(suffer from)塌陷。
接著蝕刻硬式罩幕225，其中剩餘部分表示為225'，如圖5中所繪示。蝕刻可經由乾式蝕刻或濕式蝕刻來執行。在蝕刻硬式罩幕225之後，移除圖案化光阻226，且所得結構繪示於圖6中。接著，硬式罩幕225'用作蝕刻罩幕以蝕刻下覆的毯覆式含銅層224，且毯覆式含銅層224的剩餘部分示出為金屬區域224'，如圖7中所繪示。蝕刻是非等向性的，且可經由乾式蝕刻來執行。蝕刻氣體可包含(但不限於)氧氣、氟化物(諸如氫氟酸)、氯化物(諸如氯化鐵)或其組合。亦可添加氬氣及氮氣。不同於在蝕刻中被消耗的光阻，硬式罩幕225'蝕刻/消耗不明顯。因此，所得金屬區域224'的剩餘部分的側壁是豎直或實質上豎直的，例如，其中傾斜角α2大於85度或約88度且低於或等於90度。傾斜角α2亦可大於圖2中的傾斜角α1，例如，差值(α2-α1)大於約2度或3度。接著使用硬式罩幕225'及金屬區域224'作為蝕刻罩幕來蝕刻黏著層222。硬式罩幕225'是在移除黏著層222之後移除。所得結構繪示於圖8中。剩餘的黏著層222'及金屬區域224'組合稱作導電特徵230。
圖9至圖12示出光阻輔助鍍覆製程。參考圖9，金屬晶種層221形成於底座結構220上。金屬晶種層221形成為毯覆層，其可包含黏著層222及含銅層223。含銅層223可由實質上純銅或銅合金形成。圖案化光阻226形成於金屬晶種層221上方，且開 口232藉由例如使用微影罩幕曝光圖案化光阻226且接著使圖案化光阻226顯影形成。
接著，參考圖10，金屬區域224'例如藉由將金屬材料鍍覆至開口232中形成。被鍍覆金屬材料可為銅或銅合金。金屬區域224'的頂部表面低於圖案化光阻226的頂部表面，使得金屬區域224'受開口232限制。金屬區域224'可具有實質上豎直的側壁。舉例而言，傾斜角α3可略微小於、等於或略微大於90度(例如，在85度與約90度之間或在約90度與約100度之間)。
在後續步驟中，移除圖案化光阻226，且因此暴露金屬晶種層221的下覆部分。接著在多個蝕刻步驟中移除金屬晶種層221的暴露部分，多個蝕刻步驟例如非等向性蝕刻步驟、等向性蝕刻步驟或其組合，如圖11及圖12中所繪示。遍及本說明書，金屬晶種層221'及金屬區域224'的剩餘部分組合稱作導電特徵230。
如圖1至圖12中所示出的三種製程中的每一者具有其有利的及不利的特徵。舉例而言，光阻蝕刻製程(圖1至圖3)及硬式罩幕蝕刻製程(圖4至圖6)適合於形成精細間距的導電特徵，此是因為光阻的縱橫比(圖1及圖3)可調節為充分低以避免光阻塌陷問題。然而，圖1至圖3及圖4至圖8中所繪示的製程的製程難度高，且製造成本相對較高。舉例而言，銅難以被蝕刻。
在另一方面，光阻輔助蝕刻製程由於可靠性問題不適合用於形成精細間距的導電特徵。舉例而言，圖13及圖14示出為分別繪示圖案化光阻226及開口232中的被鍍覆的金屬區域224'的俯視圖及橫截面視圖。如圖13中所繪示，開口232形成於圖案化光阻226中。開口232具有細長形狀，其中間距P1較小。兩個 相鄰開口232之間的圖案化光阻226的中間部分226A較窄，所述中間部分226A具有期望的寬度W3。開口232具有期望的寬度W2。
圖14示出圖13中所繪示的結構的橫截面視圖，其中所述橫截面視圖自圖13中的平面交叉線32-32獲得。金屬區域224'形成於開口232中，其中金屬區域224'具有期望的寬度W2。在鍍覆金屬區域224'之後，移除圖案化光阻226，且蝕刻下覆的金屬晶種層221。在蝕刻金屬晶種層221時，由於金屬晶種層221包含由與金屬區域224'相同或相似的材料(銅)形成的部分，因此金屬區域224'將亦會被蝕刻，且所得金屬區域224'的寬度將減少差值△W。為補償金屬區域224'的寬度的此種不期望的減少，如圖14中所繪示的開口232需要具有寬度W2'，其等於(W2+△W)。由於金屬區域224'的間距P1不會減少，因此中間部分226A的寬度將自W3減少至W3'，其減少的寬度等於(W3-W3')。在另一方面，圖案化光阻226的厚度不能相應地減少，此是因為圖案化光阻226的厚度需要大於金屬區域224'的設計厚度。因此圖案化光阻226的中間部分226A的縱橫比進一步增加。舉例而言，增加至大於約4或5的值。亦如圖13中所繪示，中間部分226A為遭受塌陷的長條(long strip)。
圖15及圖16示出用於形成金屬區域224'的通孔的圖案的俯視圖及橫截面視圖，所述金屬區域224'將鍍覆在開口232中。圖16中所繪示的橫截面視圖自圖15中的平面交叉線34-34獲得。自圖15及圖16，觀測到通孔的形成可能遭受如圖13及圖14中所繪示的類似問題。自圖33亦觀測到，由於兩個相鄰開口232之 間的中間部分226A不如圖13中所繪示的那樣細長，因此當形成精細間距的通孔時，光阻塌陷問題不如圖13及圖14中那麼嚴重。
針對圖1至圖12中所繪示的製程的有利特徵及不利特徵，在形成諸如重佈線路(金屬線及通孔)及金屬墊的導電特徵中，不同製程可用於形成不同的層以利用有利特徵同時避免不利特徵。舉例而言，當形成精細間距的導電特徵時，光阻蝕刻製程或硬式罩幕蝕刻製程可用於避免可靠性問題。當形成大間距的導電特徵(其可與精細間距的導電特徵處於同一封裝中)時，其中不存在與光阻的塌陷相關聯的可靠性問題，光阻輔助鍍覆製程可被採用以提供較低製程難度及較低製造成本的有利特徵。
區分精細間距的導電特徵與大間距的導電特徵的閾值間距與用於形成導電特徵的材料、結構以及製程相關，且可透過在樣本晶圓上的實驗來決定。舉例而言，可形成具有不同類型的導電特徵(重佈線路、金屬線、通孔、金屬墊等)且使用不同形成製程的多個樣本晶圓。閾值間距可判定為可使用光阻輔助鍍覆製程而不會造成可靠性問題(諸如光阻塌陷)的最小間距。因此，精細間距小於閾值間距，且大間距等於或大於閾值間距。同時，由於導電特徵層中的每一層可具有多個不同的間距，因此當決定一層導電特徵的間距是否大於、等於或小於閾值間距時，導電特徵的對應層的最小間距(minimum pitch/smallest pitch)用於與閾值間距進行比較。
圖17至圖32示出根據一些實施例的封裝的形成的中間階段的橫截面視圖。亦在圖35中所繪示的製程流程300中示意性地示出圖17至圖32中所繪示的步驟。
參考圖17，提供載體20，且離型膜22塗佈於載體20上。各別製程在圖35中所繪示的製程流程中示出為製程302。載體20由透明材料形成，且可為玻璃載體、陶瓷載體、有機載體或類似者。載體20可具有圓形俯視圖形狀。離型膜22與載體20的頂部表面實體接觸。離型膜22可由光熱轉換(Light-To-Heat-Conversion；LTHC)塗佈材料形成，且可藉由塗佈塗覆至載體20上。根據本揭露的一些實施例，光熱轉換塗佈材料在光/輻射(諸如雷射)的熱量下能夠分解，且因此可自其上形成的結構釋放載體20。離型膜22被替代地稱作光熱轉換塗佈材料。
根據本揭露的一些實施例，如圖17中所繪示，介電緩衝層24形成於離型膜22上。各別製程在圖35中所繪示的製程流程中亦示出為製程302。根據一些實施例，介電緩衝層24由諸如聚苯并噁唑(polybenzoxazole；PBO)、聚醯亞胺、苯并環丁烯(benzocyclobutene；BCB)或其類似者的聚合物形成。
圖18及圖19示出金屬柱32的形成。參考圖18，金屬晶種層26例如經由物理氣相沈積形成。各別製程在圖35中所繪示的製程流程中示出為製程304。根據本揭露的一些實施例，金屬晶種層26包含鈦層及鈦層上方的銅層。光阻28形成於金屬晶種層26上方。接著使用微影罩幕(未示出)對光阻28執行曝光。在後續顯影之後，開口30形成於光阻28中。金屬晶種層26的一些部分經由開口30暴露。
接著，金屬柱32藉由例如將金屬材料鍍覆於開口30中形成。各別製程在圖35中所繪示的製程流程中亦示出為製程304。金屬柱32替代地稱作穿孔或模製穿孔(through-molding via)，此 是因為在最終封裝中金屬柱32將穿過後續形成的包封材料(其可為模製化合物)。被鍍覆的金屬材料可為銅或銅合金。金屬柱32的頂部表面低於光阻28的頂部表面，以使得金屬柱32的形狀受開口30限制。金屬柱32可具有實質上豎直且筆直的邊緣。或者，金屬柱32在橫截面視圖中可具有砂時計(sand timer)形狀，其中金屬柱32的中間部分比對應頂部部分及底部部分窄。
在後續步驟中，移除圖案化的光阻28，且因此暴露金屬晶種層26的下覆部分。接著在蝕刻步驟中，例如在非等向性蝕刻步驟或等向性蝕刻步驟中移除金屬晶種層26的暴露部分。因此，剩餘金屬晶種層26的邊緣可與金屬柱32的各別上覆部分共邊界或實質上共邊界，或可自各別上覆鍍覆材料的各別邊緣側向地凹進，因而具有底切部(undercut)。所得金屬柱32示出於圖19中，其中底切部未示出。遍及本說明書，金屬晶種層26的剩餘部分(圖19)被視為金屬柱32的部分。金屬柱32的俯視圖形狀包含但不限於圓形形狀、矩形、六邊形、八邊形以及類似者。形成金屬柱32之後，暴露介電緩衝層24。
圖20示出裝置(或者被稱作封裝組件)的置放/附接。各別製程在圖35中所繪示的製程流程中示出為製程306。裝置可為裝置晶粒，且因此在下文中被稱作裝置晶粒36，同時裝置晶粒36亦可為封裝、晶粒堆疊或類似者。裝置晶粒36經由晶粒貼合膜(Die-Attach Film；DAF)34附接至介電緩衝層24，所述晶粒貼合膜34是在將裝置晶粒36置放於介電緩衝層24上之前預先附接於裝置晶粒36上的黏著膜。裝置晶粒36可包含具有與各別下覆的晶粒貼合膜34接觸的背表面(表面朝下)的半導體基底。裝置晶 粒36可包含半導體基底的前表面(表面朝上)處的積體電路裝置，諸如主動裝置，其包含電晶體(未示出)。根據本揭露的一些實施例，裝置晶粒36包含一或多個邏輯晶粒，其可為中央處理單元(Central Processing Unit；CPU)晶粒、圖形處理單元(Graphic Processing Unit；GPU)晶粒、行動應用程式晶粒、微型控制單元(Micro Control Unit；MCU)晶粒、輸入輸出(input-output；IO)晶粒、基頻(BaseBand；BB)晶粒或應用程式處理器(Application processor；AP)晶粒。由於載體20為晶圓級載體，因此儘管示出一個裝置晶粒36，但裝置晶粒36的多個相同群組可在晶粒置放步驟中置放於介電緩衝層24上方，且裝置晶粒群組可作為包含多個列及多個行的陣列來分佈。
根據一些例示性實施例，金屬柱42(諸如銅柱)預定成型(pre-formed)為裝置晶粒36的部分，且金屬柱42經由下覆的金屬墊40(其可為例如鋁接墊)電性耦接至裝置晶粒36中的積體電路裝置，諸如電晶體(未示出)。儘管一個金屬墊40及一個金屬柱42示出為裝置晶粒36中的每一者，但裝置晶粒36中的每一者可包含多個金屬墊40及多個上覆金屬柱42。根據本揭露的一些實施例，頂部介電層(諸如聚合物層)44填充同一裝置晶粒中相鄰金屬柱42之間的間隙以形成頂部介電層。頂部介電層44亦稱作聚合物層。鈍化層43亦可位於聚合物層44下方。頂部介電層44亦可包含覆蓋及保護金屬柱42的部分。根據本揭露的一些實施例，當由聚合物形成時，頂部介電層44可由聚苯并噁唑或聚醯亞胺形成。應瞭解，裝置晶粒36可具有包含不同頂部介電層的不同設計，所述頂部介電層由本發明的實施例涵蓋。
接著，參考圖21，裝置晶粒36及金屬柱32以包封材料48包封。各別製程在圖35中所繪示的製程流程中示出為製程308。因此，金屬柱32在下文中被稱作穿孔。包封材料48填充金屬柱32與裝置晶粒36之間的間隙。包封材料48可為模製化合物、模製底部填充料、環氧樹脂及/或樹脂。包封材料48的頂部表面高於金屬柱42及金屬柱32的頂端。包封材料48可包含基礎材料48A以及基礎材料48A中的填充劑顆粒48B，基礎材料48A可為聚合物、樹脂、環氧樹脂或類似者。填充劑顆粒可為諸如SiO2、Al2O3、矽石或類似者的介電材料的粒子，且可具有球面形狀。此外，球面填充劑顆粒48B可具有相同直徑或不同直徑，如根據一些實例所繪示。
在後續步驟中，亦如圖21中所繪示，執行諸如化學機械拋光(Chemical Mechanical Polish；CMP)製程或機械研磨製程的平坦化製程以使包封材料48及頂部介電層44變薄，直至暴露金屬柱32及金屬柱42。金屬柱32及金屬柱42亦可稍微研磨以確保暴露金屬柱32及金屬柱42兩者。由於平坦化製程，金屬柱32的頂端實質上與金屬柱42的頂部表面齊平(共平面)，且實質上與包封材料48的頂部表面共平面。由於平坦化製程，模製的包封材料48的頂部處的一些填充劑顆粒48B部分被研磨，使得填充劑顆粒中的一些的頂部部分移除，且底部部分保留，如圖21中所繪示。所得部分填充劑顆粒由此將具有平坦的頂部表面，此平坦的頂部表面與基礎材料48A、金屬柱32以及金屬柱42的頂部表面共平面。
圖22至圖30示出前側重佈線路結構的形成。在圖22至 圖30中所繪示的製程中，黏著層50A對應於圖1至圖12中的黏著層222'，且對應黏著層(諸如黏著層50A、黏著層58A)上方的金屬區域(諸如金屬區域50B、金屬區域58B)對應於圖1至圖12中的金屬區域224'。參考圖22，通孔50形成於金屬柱32及金屬柱42上方且與其電性連接。各別製程在圖35中所繪示的製程流程中示出為製程310。通孔50可包含黏著層50A及金屬區域50B。視通孔50的間距是精細間距抑或大間距而定，形成製程可採用由以下製程中選出的適合的製程：光阻蝕刻製程(圖1至圖3)、硬式罩幕蝕刻製程(圖4至圖8)以及光阻輔助鍍覆製程(圖9至圖12)。圖22示出虛線52，其表示當光阻蝕刻製程用以形成通孔50時，通孔50的側壁。或者，通孔50的側壁可為豎直或實質上豎直的，其可在採用硬式罩幕蝕刻製程或光阻輔助鍍覆製程時實現。
參考圖23，形成介電層56。各別製程在圖35中所繪示的製程流程中示出為製程312。根據本揭露的一些實施例，介電層56由諸如聚苯并噁唑、聚醯亞胺或類似者的聚合物形成。形成方法包含以可流動形式塗佈介電層56，且接著使用熱固化或紫外線(Ultra-Violet；UV)固化來固化介電層56。根據本揭露的替代性實施例，介電層56由諸如氮化矽、氧化矽或類似者的無機介電材料形成。形成方法可包含化學氣相沈積、原子層沈積(Atomic Layer Deposition；ALD)、電漿增強型化學氣相沈積或其他可應用的沈積法。接著應用諸如化學機械拋光製程或機械研磨製程的平坦化製程以平坦化通孔50及介電層56的頂部表面。
圖24示出通孔50上方且電連接至通孔50的金屬線路58的形成。金屬線路58可包含黏著層58A及金屬區域58B。各別製 程在圖35中所繪示的製程流程中示出為製程314。視金屬線路58的間距為精細間距抑或大間距而定，根據各種實施例，形成製程可採用由以下製程中選出的適合的製程中的任一者：光阻蝕刻製程、硬式罩幕蝕刻製程以及光阻輔助鍍覆製程。圖24示出虛線60，其表示當採用光阻蝕刻製程時金屬線路58的側壁。或者，金屬線路58的側壁可為豎直或實質上豎直的情況可在使用硬式罩幕蝕刻製程或光阻輔助鍍覆製程時實現。
應瞭解，金屬線路58可包含彼此平行的細長金屬線路，類似於圖13中所繪示的金屬線路。通孔50可能具有較大間隔及間距。因此，金屬線路58比通孔50更可能遭受光阻塌陷問題。根據本揭露的一些實施例，金屬線路58使用光阻蝕刻製程或硬式罩幕蝕刻製程形成，而通孔50使用光阻輔助鍍覆製程形成。根據本揭露的替代性實施例，金屬線路58及通孔50中的每一者使用光阻蝕刻製程及硬式罩幕蝕刻製程形成。
圖25及圖26示出根據本揭露的一些實施例的使用光阻輔助鍍覆製程形成通孔64(圖26)的中間階段的橫截面視圖。參考圖25，形成金屬晶種層64A。各別製程在圖35中所繪示的製程流程中示出為製程316。金屬晶種層64A的形成方法及材料可類似於圖9中所繪示的金屬晶種層221，且因此不本文中重複。接著形成圖案化光阻66，其中開口68與金屬線路58的部分交疊。各別製程在圖35中所繪示的製程流程中亦示出為製程316。接著，金屬區域64B(其為通孔)經由鍍覆形成於開口68中。各別製程在圖35中所繪示的製程流程中示出為製程318。在形成金屬區域64B之後，移除圖案化光阻66。接著，蝕刻金屬晶種層64A的被 暴露部分，且剩餘部分亦表示為64A，如圖26中所繪示。各別製程在圖35中所繪示的製程流程中示出為製程320。金屬區域64B及金屬晶種層64A的剩餘部分組合稱作通孔64，如圖10中所繪示。
根據替代性實施例，通孔64使用光阻蝕刻製程或硬式罩幕蝕刻製程形成。虛線70表示當使用光阻蝕刻製程形成時的通孔64的傾斜側壁。類似地，通孔64是使用光阻蝕刻製程抑或硬式罩幕蝕刻製程形成是基於光阻的可靠性及側壁是否傾斜的偏好來決定。
參考圖27，形成介電層72。各別製程在圖35中所繪示的製程流程中示出為步驟322。介電層72的材料及形成方法可由形成介電層56的候選材料及候選方法中選出。接著應用諸如化學機械拋光製程或機械研磨製程的平坦化製程以平面化通孔64及介電層72的頂部表面。根據替代性實施例，並非在形成金屬線路58及通孔64兩者之後形成介電層72，第一介電層可在形成金屬線路58之後且形成通孔64之前形成，隨後進行第一平坦化製程，且第二介電層可在形成通孔64之後形成，隨後進行第二平坦化製程。
圖28至圖30示出例示性大間距導電特徵74的形成，所述導電特徵74可包含金屬線路及金屬墊。各別步驟在圖35中所繪示的製程流程中示出為步驟324。應瞭解，其他金屬線路及通孔(未示出)可在通孔64與導電特徵74的金屬線路之間形成，且其他金屬線路及通孔可使用光阻蝕刻製程、硬式罩幕蝕刻製程或光阻輔助鍍覆製程形成，此可基於對應間距為大間距抑或精細間距來決定。金屬線路(其可包含導電特徵74的金屬墊)可包含黏著 層74A及金屬區域74B。導電特徵74的金屬線路及金屬墊可具有大於閾值間距的間距，且因此使用光阻輔助鍍覆製程形成。
參考圖29，形成介電層76，隨後形成接合墊(或被稱作凸塊下金屬)78，如圖30中所繪示。各別製程在圖35中所繪示的製程流程中示出為製程326。介電層76可使用由形成介電層56的候選材料及候選方法中選出的材料及方法形成。接合墊78可由鎳、銅、鈦或其多層形成。根據一些例示性實施例，接合墊78包含鈦層及鈦層上方的銅層。
參考圖31，亦形成電性連接件80，其可包含焊料區。電性連接件80亦稱作焊料區。遍及本說明書，離型膜22上方的結構的部分稱作封裝件84，其亦可為包含如所說明的多個相同封裝的複合晶圓(或重建晶圓(reconstructed wafer))。表面黏著裝置(SMD)82可黏接至封裝件84的頂部表面。
接著，封裝件84置放於膠帶(未示出)上，使得封裝件84可例如藉由光(此類雷射光束)投射於離型膜22上而自載體20卸下，且光穿過透明的載體20。由此分解離型膜22，且封裝件84自載體20釋放。
參考圖32，開口(由焊料區95佔據)形成於介電緩衝層24中，且因此暴露金屬柱32。根據本揭露的一些實施例，開口經由雷射鑽孔形成。根據本揭露的替代性實施例，開口經由微影製程中的蝕刻形成。
封裝件84包含彼此相同的多個封裝件84'(參考圖32)，其中封裝件84'中的每一者包含多個金屬柱32及一或多個裝置晶粒36。圖32示出將封裝件86黏合於封裝件84'上，由此形成疊層 封裝(Package-on-Package；PoP)結構/封裝件100。黏接經由電性連接件80來執行。根據本揭露的一些實施例，封裝件86包含封裝基底88及裝置晶粒90，所述裝置晶粒可為諸如靜態隨機存取記憶體(Static Random Access Memory；SRAM)晶粒、動態隨機存取記憶體(Dynamic Random Access Memory；DRAM)晶粒或類似者的記憶體晶粒。底部填充料92亦設置於封裝件86與下覆的封裝件84'之間的間隙中，且被固化。
執行單體化(晶粒據割)製程以將封裝件84分離為彼此相同的獨立封裝件。圖32亦示出經單體化封裝經由焊料區95黏接至封裝組件94。根據本揭露的一些實施例，封裝組件94為封裝基底，其可為無核心基底或有核心(諸如玻璃纖維強制型核心)的基底。根據本揭露的其他實施例，封裝組件94是印刷電路板或封裝件。圖32中的封裝件在下文中被稱作封裝件102。
在圖32中，重佈線路包含通孔50、通孔64、金屬線路58、導電特徵74以及對應的介電層合稱作重佈線路結構104。封裝件84'被稱作使用重佈線路最後製程形成，此是因為重佈線路結構104在包封裝置晶粒36之後形成。圖33及圖34示出使用重佈線路第一製程形成封裝件102，其中重佈線路結構104是在黏接及包封裝置晶粒36之前形成。
參考圖33，提供載體20。離型膜22及介電緩衝層24形成於載體20上方。接著，重佈線路結構104形成於介電緩衝層24上方。根據一些例示性實施例，重佈線路結構104包含導電特徵，所述導電特徵包含金屬線路106、金屬線路112及金屬線路118以及通孔110、通孔114及通孔120，所述導電特徵位於介電層108、 介電層116以及介電層122中。金屬線路106、金屬線路112及金屬線路118以及通孔110、通孔114及通孔120中的每一層可使用由光阻蝕刻製程、硬式罩幕蝕刻製程以及光阻輔助鍍覆製程中選出的方法形成，且涵蓋所有組合。此外，是否使用光阻蝕刻製程、硬式罩幕蝕刻製程或光阻輔助鍍覆製程形成導電特徵可基於光阻的可靠性(諸如對應的最小間距是否小於閾值間距)、製程難度、製造成本以及側壁是否傾斜的偏好來決定。重佈線路結構104的形成製程因此可參考圖22至圖30中的重佈線路結構104的形成及圖1至圖12中所繪示的製程而得出，且因此不重複。
圖33亦示出接合墊(或凸塊下金屬(UBM)或金屬柱)78、電性連接件80的形成以及將裝置晶粒36黏接至接合墊78。施加包封材料126，其可為模製化合物或模製的底部填充料。在圖34中示出載體20(圖33)的拆卸、單體化以及將封裝組件89黏接至封裝件84'。封裝組件可為封裝基底、印刷電路板或類似者。
根據本揭露的一些實施例，在如圖32及圖34中所繪示的封裝件84'的形成中，決定金屬線路層的第一閾值間距。金屬線層路中具有等於或大於第一閾值間距的間距的所有導電特徵(金屬線路及接墊)使用光阻輔助鍍覆製程形成，且金屬線路層中具有小於第一閾值間距的間距的所有導電特徵使用光阻蝕刻製程或硬式罩幕蝕刻製程形成。通孔層的第二閾值間距也被決定。通孔層中具有等於或大於第二閾值間距的間距的所有通孔使用光阻輔助鍍覆製程形成，且通孔層中具有小於第二閾值間距的間距的所有通孔使用光阻蝕刻製程或硬式罩幕蝕刻製程形成。第一閾值間距可等於或小於第二閾值間距。
在上文所示出的例示性實施例中，根據本揭露的一些實施例論述一些例示性製程及特徵。亦可包含其他特徵及製程。舉例而言，可包含測試結構以輔助三維(3D)封裝或三維積體電路(3DIC)裝置的校驗(verification)測試。測試結構可包含例如形成於重佈層中或基板上的測試接墊，從而允許測試三維封裝或三維積體電路、使用探測器及/或探測卡以及類似者。可對中間結構以及最終結構執行校驗測試。另外，本文中所揭露的結構及方法可與對已知良好晶粒(known good die)的中間校驗的測試方法結合使用，以增加良率及降低成本。
本揭露的實施例具有一些有利特徵。藉由在封裝的重佈線路結構中使用光阻蝕刻製程或硬式罩幕蝕刻製程(兩個製程被替代地稱作沈積及蝕刻製程)形成導電特徵，可減小封裝中的導電特徵的最小間距(在無可靠性問題的情況下)。光阻蝕刻製程及硬式罩幕蝕刻製程可與光阻輔助鍍覆製程組合以達成減小間距而不造成製造成本不必要的增加。
根據本揭露的一些實施例，一種形成封裝件的方法包含以下步驟。以包封材料包封裝置晶粒。將裝置晶粒及包封材料平面化。形成電性耦接至裝置晶粒的第一多個導電特徵，其中形成第一多個導電特徵包括沈積及蝕刻製程。所述沈積及蝕刻製程包括以下步驟。沈積毯覆式含銅層。在毯覆式含銅層上方形成圖案化光阻。蝕刻毯覆式含銅層以將圖案化光阻的圖案轉移至毯覆式含銅層中。在實施例中，第一多個導電特徵具有傾斜側壁，所述傾斜側壁具有小於約85度的傾斜角。在實施例中，形成第一多個導電特徵更包括以下步驟。在毯覆式含銅層上方沈積硬式罩幕。使用圖案 化光阻作為蝕刻罩幕蝕刻硬式罩幕，其中毯覆式含銅層使用硬式罩幕作為蝕刻罩幕來蝕刻。在實施例中，所述方法更包含沈積黏著層，其中黏著層及硬式罩幕由相同材料形成，其中毯覆式含銅層在黏著層上方且接觸所述黏著層。在實施例中，所述方法更包含使用光阻輔助鍍覆製程形成電性耦接至第一多個導電特徵的第二多個導電特徵，且所述光阻輔助鍍覆製程包括以下步驟。沈積金屬晶種層。在金屬晶種層上方形成另外的圖案化光阻。將金屬區域鍍覆至另外的圖案化光阻內的開口中及金屬晶種層上方。移除另外的圖案化光阻以暴露金屬晶種層的部分。蝕刻金屬晶種層的部分。在實施例中，第一多個導電特徵具有第一最小間距，所述第一多個小於第二多個導電特徵的第二最小間距。在實施例中，所述方法更包含形成多個樣本導電特徵以判定閾值間距，其中多個樣本導電特徵中具有小於閾值間距的間距的金屬特徵遭受光阻塌陷問題，且多個樣本導電特徵中具有等於或大於閾值間距的間距的所有金屬特徵免於受到(frse from)光阻塌陷問題，其中第一最小間距小於閾值間距，且第二最小間距等於或大於閾值間距。在實施例中，第一多個導電特徵包括通孔，且第二多個導電特徵包括金屬線路，其中通孔的頂部表面與金屬線路的底部表面實體接觸。在實施例中，所述方法更包含形成耦接至裝置晶粒的多個導電層，其中多個導電層包括：第一多個導電層，具有小於閾值間距的最小間距；及第二多個導電層，具有等於或大於閾值間距的最小間距，其中所有的第一多個導電層使用其他沈積及蝕刻製程形成，且所有的第二多個導電層使用光阻輔助鍍覆製程形成。
根據本揭露的一些實施例，一種形成封裝件的方法包含 以下步驟。以包封材料包封裝置晶粒。形成電性耦接至裝置晶粒的多個導電特徵。所述形成包括以下步驟：使用光阻輔助鍍覆製程形成第一多個導電特徵，及使用沈積及蝕刻製程形成第二多個導電特徵，其中第一多個導電特徵及第二多個導電特徵包括銅，且第一多個導電特徵的第一最小間距大於第一多個導電特徵的第二最小間距。在實施例中，多個導電特徵是在包封裝置晶粒之前形成。在實施例中，多個導電特徵是在包封裝置晶粒之後形成。
根據本揭露的一些實施例，一種形成封裝件的方法包含以下步驟。形成多個通孔，所述形成包括沈積第一黏著層，在第一黏著層上方沈積毯覆式含銅層，在毯覆式含銅層上方形成第一圖案化光阻以及蝕刻毯覆式含銅層及第一黏著層。沈積第一介電層以埋置多個通孔。對第一介電層及多個通孔執行第一平坦化。形成多根金屬線路，所述形成包括在多個通孔上方沈積金屬晶種層且使金屬晶種層接觸多個通孔，在金屬晶種層上方沈積第二圖案化光阻，在第二圖案化光阻中鍍覆金屬區域，移除第二圖案化光阻以及蝕刻金屬晶種層的部分。沈積第二介電層以埋置多根金屬線路。以及對第二介電層及金屬區域執行第二平坦化。在實施例中，形成多個通孔是藉由使用第一圖案化光阻作為蝕刻罩幕蝕刻毯覆式含銅層來執行。在實施例中，蝕刻毯覆式含銅層採用形成多個通孔的傾斜側壁的製程條件。在實施例中，傾斜側壁具有在約65度與約80度之間的傾斜角。在實施例中，形成通孔更包括：在毯覆式含銅層上方形成硬式罩幕，其中硬式罩幕由與第一黏著層相同的材料形成，且第一圖案化光阻在硬式罩幕上方，使用第一圖案化光阻作為蝕刻罩幕蝕刻硬式罩幕，其中蝕刻毯覆式含銅層使用經蝕刻 硬式罩幕作為蝕刻罩幕來執行。在實施例中，形成金屬晶種層包括以下步驟。沈積第二黏著層。在第二黏著層上方沈積含銅的晶種層。
一種封裝件包括裝置晶粒、第一多個導電特徵、第二多個導電特徵。第一多個導電特徵位於裝置晶粒上方且電性耦接至裝置晶粒，其中第一多個導電特徵具有第一傾斜角小於85度的第一側壁。第二多個導電特徵位於第一多個導電特徵上方且電性耦接至第一多個導電特徵，其中第二多個導電特徵具有第二傾斜角大於85度且等於或小於約90度的第二側壁。在實施例中，第二多個導電特徵具有與第一多個導電特徵的頂部表面接觸的底部表面。在實施例中，裝置晶粒包括電性連接件，且其中第一多個導電特徵是與裝置晶粒的電性連接件接觸的通孔。
前文概述若干實施例的特徵，以使得所屬領域中具通常知識者可較佳地理解本揭露的態樣。所屬領域中具通常知識者應理解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他方法及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域中具通常知識者可在而不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
24:介電緩衝層
32:金屬柱
34:晶粒貼合膜
36:裝置晶粒
40:底層金屬墊
42:金屬柱
48:包封材料
48A:基礎材料
48B:填充劑顆粒
50、64:通孔
50A、74A:黏著層
50B、64B、74B:金屬區域
56、72、76:介電層
58:金屬線路
64A:金屬晶種層
74:導電構件
78:接合墊
80:電性連接件
84'、86、100、102:封裝件
88:封裝基底
94:封裝組件
90:裝置晶粒
92:底部填充料
95:焊料區
104:重佈線結構

Claims (14)

  1. 一種形成封裝件的方法，包括：以包封材料包封裝置晶粒；以及形成電性耦接至所述裝置晶粒的第一多個導電特徵，其中所述形成所述第一多個導電特徵包括沈積及蝕刻製程，所述沈積及蝕刻製程包括：沈積黏著層；沈積毯覆式含銅層，其中所述毯覆式含銅層位於所述黏著層上方且接觸所述黏著層；在所述毯覆式含銅層上方沈積硬式罩幕，其中所述黏著層及所述硬式罩幕由相同材料形成；在所述硬式罩幕上方形成圖案化光阻；使用所述圖案化光阻作為蝕刻罩幕來蝕刻所述硬式罩幕；以及使用被蝕刻的所述硬式罩幕作為另一蝕刻罩幕來蝕刻所述毯覆式含銅層以將所述圖案化光阻的圖案轉移至所述毯覆式含銅層。
  2. 如申請專利範圍第1項所述的方法，其中所述第一多個導電特徵具有傾斜側壁，所述傾斜側壁具有小於約85度的傾斜角。
  3. 如申請專利範圍第1項所述的方法，其中所述硬式罩幕以濕式蝕刻製程蝕刻。
  4. 如申請專利範圍第1項所述的方法，其中所述硬式罩幕以乾式蝕刻製程蝕刻。
  5. 如申請專利範圍第1項所述的方法，更包括使用光阻 (PR)輔助鍍覆製程形成電性耦接至所述第一多個導電特徵的第二多個導電特徵，且所述光阻輔助鍍覆製程包括：沈積金屬晶種層；在所述金屬晶種層上方形成另一圖案化光阻；將金屬區域鍍覆至所述另一圖案化光阻內的開口中及所述金屬晶種層上方；移除所述另一圖案化光阻以暴露所述金屬晶種層的部分；以及蝕刻所述金屬晶種層的所述部分。
  6. 如申請專利範圍第5項所述的方法，其中所述第一多個導電特徵具有第一最小間距，所述第一最小間距小於所述第二多個導電特徵的第二最小間距。
  7. 如申請專利範圍第6項所述的方法，更包括：形成多個樣本導電特徵以判定閾值間距，其中在所述多個樣本導電特徵中，具有小於所述閾值間距的間距的金屬特徵遭受(suffer from)光阻塌陷問題(photo-resist-collapsing problem)，且在所述多個樣本導電特徵中，具有等於或大於所述閾值間距的間距的所有金屬特徵免於受到(free from)所述光阻塌陷問題，其中所述第一最小間距小於所述閾值間距，且所述第二最小間距等於或大於所述閾值間距。
  8. 如申請專利範圍第1項所述的方法，包括形成耦接至所述裝置晶粒的多個導電層，其中所述多個導電層包括：第一多個導電層，具有小於閾值間距的最小間距；及第二多個導電層，具有等於或大於所述閾值間距的最小間距， 其中所有的所述第一多個導電層使用另一沈積及蝕刻製程形成，且所有的所述第二多個導電層使用光阻輔助鍍覆製程形成。
  9. 一種形成封裝件的方法，包括：形成多個通孔，包括：沈積第一黏著層；在所述第一黏著層上方沈積毯覆式含銅層；在所述毯覆式含銅層上方形成第一圖案化光阻；以及蝕刻所述毯覆式含銅層及所述第一黏著層；沈積第一介電層以埋置所述多個通孔；對所述第一介電層及所述多個通孔執行第一平坦化；形成多根金屬線路，包括：在所述多個通孔上方沈積金屬晶種層且使所述金屬晶種層接觸所述多個通孔；在所述金屬晶種層上方沈積第二圖案化光阻；將金屬區域鍍覆於所述第二圖案化光阻中；移除所述第二圖案化光阻；以及蝕刻所述金屬晶種層的部分；沈積第二介電層以埋置所述多根金屬線路；以及對所述第二介電層及所述金屬區域執行第二平坦化。
  10. 如申請專利範圍第9項所述的方法，其中所述形成所述多個通孔是藉由使用所述第一圖案化光阻作為蝕刻罩幕蝕刻所述毯覆式含銅層來執行。
  11. 如申請專利範圍第10項所述的方法，其中所述蝕刻所述毯覆式含銅層採用形成所述多個通孔的傾斜側壁的製程條件。
  12. 如申請專利範圍第11項所述的方法，其中所述傾斜側壁具有在約65度與約80度之間的傾斜角。
  13. 如申請專利範圍第9項所述的方法，其中所述形成所述通孔更包括：在所述毯覆式含銅層上方形成硬式罩幕，所述硬式罩幕由與所述第一黏著層相同的材料形成，且所述第一圖案化光阻位於所述硬式罩幕上方；以及使用所述第一圖案化光阻作為蝕刻罩幕來蝕刻所述硬式罩幕，其中使用被蝕刻的所述硬式罩幕作為蝕刻罩幕來執行所述蝕刻所述毯覆式含銅層。
  14. 一種封裝件，包括：裝置晶粒，包括電性連接件；第一多個導電特徵，位於所述裝置晶粒上方且電性耦接至所述裝置晶粒，其中所述第一多個導電特徵具有第一傾斜角小於85度的第一側壁；以及第二多個導電特徵，位於所述第一多個導電特徵上方且電性耦接至所述第一多個導電特徵，其中所述第二多個導電特徵具有第二傾斜角大於85度且等於或小於約90度的第二側壁，且所述第一多個導電特徵與所述裝置晶粒的電性連接件接觸。
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