CN110660686B - 形成rdl的方法和由其形成的结构 - Google Patents

形成rdl的方法和由其形成的结构 Download PDF

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CN110660686B
CN110660686B CN201910456698.0A CN201910456698A CN110660686B CN 110660686 B CN110660686 B CN 110660686B CN 201910456698 A CN201910456698 A CN 201910456698A CN 110660686 B CN110660686 B CN 110660686B
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layer
photoresist
conductive
forming
metal
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CN110660686A (zh
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郭宏瑞
谢昀蓁
蔡惠榕
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括将器件管芯封装在封装材料中，平坦化器件管芯和封装材料，并形成电耦合至器件管芯的多个第一导电部件。形成多个第一导电部件的步骤包括沉积和蚀刻工艺，其包括沉积毯式含铜层，在毯式含铜层上方形成图案化的光刻胶，以及蚀刻毯式含铜层以将图案化的光刻胶的图案转印到毯式含铜层中。本发明实施例涉及形成RDL的方法和由其形成的结构。

Description

形成RDL的方法和由其形成的结构
技术领域
本发明实施例涉及形成RDL的方法和由其形成的结构。
背景技术
随着半导体技术的发展，半导体芯片/管芯变得越来越小。同时，需要将更多功能集成到半导体管芯中。因此，半导体管芯需要具有越来越多的封装到更小区域中的I/O焊盘，并且I/O焊盘的密度随时间快速增大。结果，半导体管芯的封装变得更加困难，这不利地影响了封装的产量。
传统的封装技术可以分为两类。在第一类中，晶圆上的管芯在锯切之前被封装。这种封装技术具有一些有利的特征，诸如更高的产量和更低的成本。此外，需要较少的底部填充物或模塑料。然而，这种封装技术也存在缺点。由于管芯的尺寸变得越来越小，并且相应的封装只能是扇入型封装，其中每个管芯的I/O焊盘限制于直接在相应管芯的表面上方的区域。在管芯的区域有限的情况下，由于I/O焊盘的间距的限制，I/O焊盘的数量受到限制。如果要减小焊盘的间距，则可能发生焊料桥接。另外，在固定的球尺寸的要求下，焊球必须具有一定的尺寸，这又限制了可以封装在管芯表面上的焊球的数量。
在另一类封装中，在封装管芯之前从晶圆锯切管芯。这种封装技术的一个有利特点是可以形成扇出封装，这意味着芯片上的I/O焊盘可以重新分配到比管芯更大的面积，因此封装在管芯的表面上的I/O焊盘的数量更可以增加。该封装技术的另一个有利特征是封装了“已知良好管芯”，并且丢弃了有缺陷的管芯，因此不会在有缺陷的管芯上浪费成本和精力。
在扇出封装中，器件管芯被封装在模塑料中，然后将其平坦化以暴露器件管芯。在器件管芯上方形成介电层。重分布线形成在介电层中以连接到器件管芯。扇出封装还可以包括穿透模塑料的通孔。重分布线的形成包括形成晶种层，形成图案化的光刻胶，以及将重分布线镀到图案化的光刻胶的开口中。
发明内容
根据本发明的一些实施例，提供了一种形成半导体结构的方法，包括：将器件管芯封装在封装材料中；以及形成电耦合至所述器件管芯的多个第一导电部件，其中，形成所述多个第一导电部件包括沉积和蚀刻工艺，包括：沉积毯式含铜层；在所述毯式含铜层上方形成图案化的光刻胶；和蚀刻所述毯式含铜层以将所述图案化的光刻胶的图案转印到所述毯式含铜层中。
根据本发明的另一些实施例，还提供了一种形成半导体结构的方法，包括：形成多个通孔，包括：沉积第一粘合层；在所述第一粘合层上方沉积毯式含铜层；在所述毯式含铜层上方形成第一图案化的光刻胶；和蚀刻所述毯式含铜层和所述第一粘合层；沉积第一介电层以嵌入所述多个通孔；对所述第一介电层和所述多个通孔实施第一平坦化；形成多条金属线，包括：在所述多个通孔上方与沉积所述多个通孔接触的金属晶种层；在所述金属晶种层上方沉积第二图案化的光刻胶；在所述第二图案化的光刻胶中镀金属区域；去除所述第二图案化的光刻胶；和蚀刻所述金属晶种层的部分；沉积第二介电层以嵌入所述多条金属线；和对所述第二介电层和所述金属区域实施第二平坦化。
根据本发明的又一些实施例，还提供了一种半导体结构，包括：器件管芯；多个第一导电部件，位于所述器件管芯上方并且电耦合至所述器件管芯，其中，所述多个第一导电部件具有第一侧壁，所述第一侧壁具有小于85度的第一倾斜角；和多个第二导电部件，位于所述多个第一导电部件上方并且电耦合至所述多个第一导电部件，其中，所述多个第二导电部件具有第二侧壁，所述第二侧壁具有大于85度且等于或小于90度的第二倾斜角。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图3示出了根据一些实施例的使用PR蚀刻工艺形成导电部件的中间阶段的截面图。
图4至图8示出了根据一些实施例的使用HM蚀刻工艺形成导电部件的中间阶段的截面图。
图9至图12示出了根据一些实施例的通过PR辅助镀工艺形成导电部件的中间阶段的截面图。
图13和14分别示出了根据一些实施例的使用PR辅助镀工艺用于形成细长导线的光刻胶的俯视图和截面图。
图15和16分别示出了根据一些实施例的使用PR辅助镀工艺用于形成通孔的光刻胶的俯视图和截面图。
图17至图32示出了根据一些实施例的使用后重分布线(RDL)工艺形成封装件的中间阶段的截面图。
图33和34示出了根据一些实施例的使用先RDL工艺形成封装件的中间阶段的截面图。
图35示出了根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同部件的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，使用空间相对术语，例如，“下面”，下方”，“下部”，“之上”,“上部”等以便于描述本公开的一个部件与另一个部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
根据各种示例性实施例提供了集成扇出(InFO)封装件及其形成方法。根据一些实施例示出了形成InFO封装件的中间阶段。讨论了一些实施例的一些变型。在各种视图和说明性实施例中，相同的附图标记用于表示相同的元件。
图1至图12示出了可用于在封装件中形成导电部件(诸如重分布线(RDL，其包括金属线和通孔)和金属焊盘)的多个候选工艺。图1至图3示出了第一形成工艺(也称为PR蚀刻工艺，术语“PR”表示“光刻胶”)。图4至图8示出了第二形成工艺(也称为HM蚀刻工艺，术语“HM”表示“硬掩模”)。图9至12示出了第三形成工艺(也称为PR辅助镀工艺)。此外，PR蚀刻工艺和HM蚀刻工艺被单独地和统称为沉积和蚀刻工艺。应当理解，在封装件中形成导电部件时，根据要求、材料和结构，可以使用不同的工艺在同一封装件中形成不同的导电部件层，以实现优化的结果，诸如提高可靠性而不会不必要地增加制造成本。
图1至图3示出了根据本公开的一些实施例的使用PR蚀刻工艺形成导电部件。该工艺可用于形成细间距导电部件。应当理解，术语“细间距”是相对于“大间距”的术语，并且细间距导电部件和大间距导电部件之间的间距差异与具体工艺、结构和结构的材料相关。此外，“细间距”和“大间距”之间的阈值间距可能受到在形成工艺中使用的光刻胶的影响。根据本公开的一些实施例，划分细间距和大间距的阈值间距在约0.1μm和约4μm之间的范围内。例如，阈值间距可以是约4μm。
参考图1，形成基底结构220。基底结构220表示将在其上形成导电部件的任何结构，并且未示出基底结构220的细节。基底结构220可以包括导电部件和介电层，其可以是RDL、器件管芯、封装等的一部分。根据本公开的一些实施例，基底结构220可以表示图21、23、24和27中所示的任何结构以及图33中的中间结构。根据本公开的一些实施例，基底结构220具有平坦的顶面。根据本公开的替代实施例，基底结构220具有非平坦顶面。
根据本公开的一些实施例，粘合层222形成在基底结构220上方。根据本公开的其他实施例，省略粘合层222。因此，层222在图1中以虚线示出。粘合层222可以包括与铜不同的金属，并且可以由钛，钽，氮化钛，氮化钽等形成。粘合层222可以形成为毯式层，并且可以使用物理气相沉积(PVD)，化学气相沉积(CVD)，等离子体增强化学气相沉积(PECVD)等来沉积。毯式金属层224形成在基底结构220上方和粘合层222上方(如果形成的话)。金属层224可以由基本上纯铜或铜合金形成，因此可以替代地称为含铜层224，但是金属层224可以由诸如铝，镍等的其他材料形成。在粘合层222上方形成图案化的光刻胶226，并且在图案化的光刻胶226中例如通过曝光和显影形成开口228。
根据一些实施例，图案化的光刻胶226包括在俯视图中具有长条形状的一些部分。根据一些示例性实施例，图案化的光刻胶226可以具有小于约1.5的纵横比H1/W1，并且纵横比可以在约1.0和约1.5之间的范围内。根据一些实施例，光刻胶226的部分的宽度W1可以在约0.3μm和约2μm之间的范围内。光刻胶226的相邻部分之间的间隔S1可以在约0.3μm和约2μm之间的范围内。高度H1可以在约0.45μm和约3μm之间的范围内。在具有低纵横比的情况下，光刻胶226，尤其是较窄的那些部分，将不会不利地坍塌。
参考图2，执行干蚀刻(由箭头表示)工艺以蚀刻含铜层224，并且将含铜层224的剩余部分称为金属区域224'。可以使用包括但不限于氩气，氮气，氟基气体或其组合的工艺气体来执行蚀刻。在蚀刻中，还蚀刻/消耗光刻胶226。假设光刻胶226的蚀刻速率为R226，并且含铜层224的蚀刻速率为R224，则可以调节蚀刻选择性，即R224/R226。蚀刻选择性的调节可以通过调节工艺气体的组成、光刻胶226的组成和/或蚀刻工艺条件来实现。蚀刻选择性的调节导致金属区域224'的侧壁倾斜，并且金属区域224'具有梯形截面视图，底侧比相应的顶侧长。例如，可以将倾斜角α1调节到期望值，该期望值可以小于约85度或小于约80度。倾斜角α1可以在约60度和约85度之间的范围内，并且可以在约65度和80度之间的范围内。具有底侧比顶侧长的导电部件有利于导电部件与周围介电层的粘合。例如，在底侧比顶侧长的情况下，与如果底侧等于或小于相应顶侧的情况相比，粘合层的剩余部分(图3)具有更大的面积，因此金属区域224'到基底结构220的粘附性得到改进。此外，使底侧比相应顶侧长，也可以改善金属区域224'至介电层的粘附性，该介电层将设置在与金属区域224'相同的层级上。
在蚀刻含铜层224之后，暴露粘合层222，然后蚀刻粘合层222。在蚀刻粘合层222之前或之后，也去除光刻胶226。可以通过湿蚀刻或干蚀刻来蚀刻粘合层222。选择蚀刻化学品/溶液以侵蚀粘合层222，并且不侵蚀金属区域224'。蚀刻化学品/溶液可包括HF溶液，HF/H2O2的混合物，H2O2(具有一些其他添加剂)，NaHCO3，NaOH，NaHCO3/H2O2的混合物，NaHCO3/NaOH/H2O2的混合物，或碱金属氢氧化物水溶液。碱金属氢氧化物水溶液可以是NaOH，KOH等的溶液。粘合层222的剩余部分表示为粘合层222'，如图3所示。粘合层222'和金属区域224'组合称为导电部件230。
图4至图6示出了用于形成具有垂直或基本垂直侧壁的导电部件230的工艺，例如，具有大于约80度且等于或小于90度的倾斜角α(图7)。参照图4，形成基底结构220，接着沉积粘合层222，毯式金属层(也称为含铜层)224和图案化的光刻胶226。此外，硬掩模225形成在含铜层224上方。根据本公开的一些实施例，硬掩模225由与粘合层222的材料相同的材料形成，使得用于形成硬掩模225的工艺可以在与粘合层222相同的生产工具中实施，其间没有真空破坏。因此可以降低生产成本。光刻胶226的示例性尺寸和间隔可以类似于参考图1所讨论的，并且在此不再重复。光刻胶226的纵横比低，例如，在约1.0和约1.5之间的范围内，因此它不会发生坍塌。
然后蚀刻硬掩模225，剩余部分表示为225'，如图5所示。可以通过干蚀刻或湿蚀刻来执行蚀刻。在蚀刻硬掩模225之后，去除光刻胶226，并且所得到的结构如图6所示。接下来，使用硬掩模225'作为蚀刻掩模来蚀刻下面的含铜层224，并且含铜层224的剩余部分被示出为金属区域224'，如图7所示。蚀刻是各向异性的，并且可以通过干蚀刻进行。蚀刻气体可包括但不限于氧气，诸如氢氟酸的氟化物，诸如氯化铁的氯化物，或其组合。也可以添加氩气和氮气。与在蚀刻中消耗的光刻胶不同，硬掩模225'未被显著蚀刻/消耗。结果，所得金属区域224'的剩余部分的侧壁是垂直的或基本垂直的，例如，倾斜角α2大于85度，或大约88度并且小于或等于90度。倾斜角α2也可以大于图2中的倾斜角α1，例如，差(α2-α1)大于约2或3度。然后使用硬掩模225'和金属区域224'作为蚀刻掩模来蚀刻粘合层222。在去除粘合层222之后去除硬掩模225'。所得到的结构如图8所示。剩余的粘合层222'和金属区域224'组合称为导电部件230。
图9至12示出了PR辅助镀工艺。参照图9，金属晶种层221形成在基底结构220上。金属晶种层221形成为毯式层，其可包括粘合层222和含铜层223。含铜层223可由基本上纯铜或铜合金形成。在金属晶种层221上方形成图案化的光刻胶226，并且例如通过使用光刻掩模对光刻胶226进行曝光，然后显影光刻胶226来形成开口232。
接下来，参考图10，例如，通过将金属材料镀到开口232中来形成金属区域224'。镀的金属材料可以是铜或铜合金。金属区域224'的顶面低于光刻胶226的顶面，使得金属区域224'被开口228限制。金属区域224'可以具有基本垂直的侧壁。例如，倾斜角α3可以略微小于，等于或略大于90度(例如，在85度和约90度之间或者在约90度和约100度之间)。
在随后的步骤中，去除图案化的光刻胶226，因此暴露下面的金属晶种层221的部分。然后在多个蚀刻步骤(例如，各向异性蚀刻步骤，各向同性蚀刻步骤或其组合)中去除金属晶种层221的暴露部分，如图11和12所示。在整个说明书中，金属晶种层221'和金属区域224'的剩余部分组合称为导电部件230。
如图1至图12中所示的三个工艺中的每一个都具有其有利和不利的特征。例如，PR蚀刻工艺(图1至图3)和HM蚀刻工艺(图4至图6)适合于形成细间距导电部件，因为光刻胶的纵横比(图1和图3)可以调整到足够低，以避免光刻胶坍塌问题。然而，图1至3和图4至8中所示的工艺的工艺难度很高，并且制造成本相对较高。例如，铜难以蚀刻。
另一方面，由于可靠性问题，PR辅助蚀刻工艺不适合于形成细间距导电部件。例如，图13和14分别示出了光刻胶226和开口232中的镀的金属区域224'的顶视图和截面图。如图13所示，将开口232形成在光刻胶226中，开口232具有细长的形状，间距P1很小。两个相邻开口232之间的光刻胶226的中间部分226A是窄的，具有期望的宽度W3。开口232具有期望的宽度W2。
图14示出了图13中所示结构的截面图，其中截面图是从图13中的平面交叉线32-32获得的。金属区域224'将形成在开口232中，金属区域224'具有期望的宽度W2。在镀金属区域224'之后，去除光刻胶226，并蚀刻下面的金属晶种层221。在金属晶种层221的蚀刻中，由于金属晶种层221包括由与金属区域224'(铜)相同或相似的材料形成的部分，所以还将蚀刻金属区域224'，并且所得到的金属区域224'的宽度将减小差值ΔW。为了补偿金属区域224'的宽度的这种不希望的减小，如图14所示的开口232需要具有宽度W2'，其等于(W2+ΔW)。由于金属区域224'的间距P1不能减小，所以光刻胶部分226A的宽度W3将从W3减小到W3'，其等于(W3-W3')。另一方面，光刻胶226的厚度不能相应地减小，因为光刻胶226的厚度需要大于金属区域224'的设计厚度。因此，光刻胶226的中间部分226A的纵横比进一步增加。例如，增加至大于约4或5的值。如图13所示，光刻胶部分226A是长条带，其遭受坍塌。
图15和16示出了用于形成金属区域224'的通孔的图案的顶视图和截面图，其将被镀在开口232中。图16中所示的截面图是从图15中的平面交叉线34-34获得的。从图15和16中可以看出，通孔的形成可能遇到如图13和14所示的类似的问题。从图33中也可以看出，由于两个相邻开口232之间的中间光刻胶部分226A不像图13所示那样是细长的，当形成细间距通孔时，光刻胶坍塌问题不像图13和14那样严重。
对于图1至图12中所示的工艺的有利特征和不利特征，在形成诸如RDL(金属线和通孔)和金属焊盘的导电部件时，可以使用不同的工艺来形成不同的层以利用有利特征，同时避免不利特征。例如，当形成细间距导电部件时，可以使用PR蚀刻工艺或HM蚀刻工艺来避免可靠性问题。当形成大间距导电部件(其可以与细间距导电部件位于同一封装件中)时，其中不存在与光刻胶坍塌相关的可靠性问题，可以采用PR辅助镀工艺来利用降低工艺难度和降低制造成本的特征。
划分细间距和大间距导电部件的阈值间距与材料、结构和形成导电部件的工艺有关，并且可以通过对样品晶圆的实验来确定。例如，可以形成具有不同类型的导电部件(RDL，金属线，通孔，金属焊盘等)并使用不同的形成工艺来形成的多个样品晶圆。阈值间距可以被确定为可以使用PR辅助镀工艺实现的最小间距，而不会引起可靠性问题(例如PR坍塌)。因此，细间距小于阈值间距，并且大间距等于或大于阈值间距。而且，由于导电部件的每个层可以具有多个不同的间距，所以当确定导电部件层的间距是否大于，等于或小于阈值间距时，导电部件的相应层的最小间距(最小的间距)用于与阈值间距进行比较。
图17至32示出了根据一些实施例的封装件形成中的中间阶段的截面图。图17至32中所示的步骤也在图35中所示的工艺流程300中示意性地示出。
参照图17，提供载体20，并且将离型膜22涂覆在载体20上。相应的工艺在图35所示的工艺流程中示为工艺302。载体20由透明材料形成，并且可以是玻璃载体，陶瓷载体，有机载体等。载体20可具有圆形顶视图形状。离型膜22与载体20的顶面物理接触。离型膜22可以由光-热转换(LTHC)涂层材料形成，并且可以通过涂布施加到载体20上。根据本公开的一些实施例，LTHC涂层材料能够在光/辐射(例如激光)的热量下分解，因此可以从形成在其上的结构释放载体20。可选地，离型膜22被称为LTHC涂层材料22。
根据本公开的一些实施例，如图17所示，介电缓冲层24形成在LTHC涂层材料22上。相应的工艺也被示为图35中所示的工艺流程中的工艺302。根据一些实施例，介电缓冲层24由聚合物形成，诸如聚苯并恶唑(PBO)，聚酰亚胺，苯并环丁烯(BCB)等。
图18和19示出了金属柱32的形成。参考图18，例如通过物理气相沉积(PVD)形成金属晶种层26。相应的工艺被示为图35中所示的工艺流程中的工艺304。根据本公开的一些实施例，金属晶种层26包括钛层和钛层上方的铜层。在金属晶种层26上形成光刻胶28。然后使用光刻掩模(未示出)对光刻胶28进行曝光。在随后的显影之后，在光刻胶28中形成开口30。金属晶种层26的一些部分通过开口30暴露。
接下来，例如通过在开口30中镀金属材料来形成金属柱32。相应的工艺也被示为图35中所示的工艺流程中的工艺304。金属柱32可替代地称为通孔或模制通孔，因为它们将穿透位于最终封装件中的随后形成的封装材料(可以是模塑料)。镀的金属材料可以是铜或铜合金。金属柱32的顶面低于光刻胶28的顶面，使得金属柱32的形状由开口30限制。金属柱32可具有基本垂直和直的边缘。或者，金属柱32在截面图中可具有沙漏形状，金属柱32的中间部分比相应的顶部和底部窄。
在随后的步骤中，去除图案化的光刻胶28，因此暴露下面的金属晶种层26的部分。然后在蚀刻步骤中去除金属晶种层26的暴露部分，例如，在各向异性蚀刻步骤或各向同性蚀刻步骤中。因此，剩余的金属晶种层26的边缘可以与上面的相应金属柱32的部分共同终止或基本上共同终止，或者可以从相应上面的镀材料的相应边缘横向凹进，因此具有底切。所得到的金属柱32在图19中示出，其中未示出底切。在整个说明书中，金属晶种层26(图19)的剩余部分被认为是金属柱32的一部分。金属柱32的顶视图形状包括但不限于圆形，矩形，六边形，八边形。等等。在形成金属柱32之后，暴露介电缓冲层24。
图20示出了器件36(或者称为封装组件)的放置/附接。相应的工艺被示为图35中所示的工艺流程中的工艺306。器件36可以是器件管芯，因此在下文中被称为器件管芯36，但是器件36也可以是封装件，管芯堆叠件等。器件管芯36通过管芯附接膜(DAF)34附接到介电缓冲层24，所述管芯附接膜34是在器件管芯36放置在介电缓冲层24上之前预先附接在器件管芯36上的粘合膜。器件管芯36可以包括具有与相应的下面的DAF34接触的背面(朝下的表面)的半导体衬底。器件管芯36可以包括集成电路器件，诸如有源器件，其包括在半导体衬底的正面(朝上的表面)处的晶体管(未示出)。根据本公开的一些实施例，器件管芯36包括一个或多个逻辑管芯，其可以是中央处理单元(CPU)管芯，图形处理单元(GPU)管芯，移动应用管芯，微控制单元(MCU)管芯，输入输出(IO)管芯，基带(BB)管芯或应用处理器(AP)管芯。由于载体20是晶圆级载体，尽管示出了一个器件管芯36，但是在管芯放置步骤中可以在介电缓冲层24上方放置多个相同组的器件管芯36，并且器件管芯组可以分配为包括多个行和多个列的阵列。
根据一些示例性实施例，金属柱42(诸如铜柱)被预先形成为器件管芯36的一部分，并且金属柱42通过下面的金属焊盘40电耦合至集成电路器件，诸如器件管芯36中的晶体管(未示出)，例如，金属焊盘40可以是铝焊盘。尽管在每个器件36中示出了一个金属焊盘40和一个金属柱42，但是每个器件36可以包括多个金属焊盘40和多个上面的金属柱42。根据本公开的一些实施例，顶部介电层(诸如聚合物层)44填充相同器件管芯中的相邻金属柱42之间的间隙，以形成顶部介电层。顶部介电层44也称为聚合物层。钝化层43也可以位于聚合物层44下面。顶部介电层44还可以包括覆盖和保护金属柱42的部分。根据本公开的一些实施例，顶部介电层44，当由聚合物形成时，可以由PBO或聚酰亚胺形成。应了解，器件管芯36可具有不同的设计，包括不同的顶部介电层，其可由本公开的实施例预期。
接下来，参考图21，器件管芯36和金属柱32封装在封装材料48中。相应的工艺在图35所示的工艺流程中被示为工艺308。因此，金属柱32在下文中被称为通孔。封装材料48填充通孔32和器件管芯36之间的间隙。封装材料48可以是模塑料，模制底部填充物，环氧树脂和/或树脂。封装材料48的顶面高于金属柱42和通孔32的顶端。封装材料48可包括基底材料48A，其可以是聚合物，树脂，环氧树脂等，填料颗粒48B位于基底材料48A中。填料颗粒可以是介电材料的颗粒，诸如SiO2、Al2O3、二氧化硅等，并且可以具有球形形状。而且，球形填料颗粒48B可以具有相同或不同的直径，如根据一些实例所示。
在随后的步骤中，也如图21所示，执行诸如化学机械抛光(CMP)工艺或机械研磨工艺的平坦化工艺以薄化封装材料48和介电层44，直到暴露通孔32和金属柱42。通孔32和金属柱42也可以稍微抛光以确保通孔32和金属柱42的暴露。由于平坦化工艺，通孔32的顶端与金属柱42的顶面基本齐平(共面)并且与封装材料48的顶面基本上共面。由于平坦化工艺，模制的封装材料48顶部的一些填料颗粒48B被部分抛光，导致一些填料颗粒的顶部被去除，并留下底部，如图21所示。所得的部分填料颗粒因此具有平坦的顶面，该平坦顶面与基底材料48A、通孔32和金属柱42的顶面共面。
图22至30示出了正侧重分布结构的形成。在图22至30所示的工艺中，粘合层50A对应于图1至12中的粘合层222'，并且覆盖相应的粘合层(诸如50A，58A)的金属区域(诸如50B，58B)对应于图1至图12中的金属区域224'。参见图22，通孔50形成在通孔32和金属柱42上方并且电连接到通孔32和金属柱42。相应的工艺在图35的工艺流程中示出为工艺310。通孔50可包括粘合层50A和金属区域50B。形成工艺可采用选自PR蚀刻工艺(图1至3)，HM蚀刻工艺(图4至8)和PR辅助镀工艺(图9至12)的合适工艺，取决于通孔50的间距是细间距还是大间距。图22示出了虚线52，其表示当采用PR蚀刻工艺来形成通孔50时的通孔50的侧壁。或者，通孔50的侧壁可以是垂直的或基本垂直的，这可以当采用HM蚀刻工艺或PR辅助镀工艺时实现。
参考图23，形成介电层56。相应的工艺被示为图35中所示的工艺流程中的工艺312。根据本公开的一些实施例，介电层56由诸如聚苯并恶唑(PBO)，聚酰亚胺等的聚合物形成。形成方法包括以可流动的形式涂覆介电层56，然后使用热固化或紫外(UV)固化来固化介电层56。根据本公开的替代实施例，介电层56由诸如氮化硅，氧化硅等的无机介电材料形成。形成方法可以包括化学气相沉积(CVD)，原子层沉积(ALD)，PECVD或其他适用的沉积方法。然后应用诸如CMP工艺或机械研磨工艺的平坦化工艺以平坦化通孔50和介电层56的顶面。
图24示出了在通孔50上方形成电连接到通孔50的金属线58。金属线58可以包括粘合层58A和金属区域58B。相应的工艺在图35所示的工艺流程中被示为工艺314。根据各种实施例，形成工艺可以采用选自PR蚀刻工艺，HM蚀刻工艺和PR辅助镀工艺中的任何合适的工艺，取决于金属线58的间距是细间距还是大间距。图24示出了虚线60，其表示采用PR蚀刻工艺时金属线58的侧壁。或者，金属线58的侧壁可以是垂直的或基本垂直的，这可以在使用HM蚀刻工艺或PR辅助镀工艺时实现。
应当理解，金属线58可以包括彼此平行的细长金属线，类似于图13中所示。通孔50可能具有更大的间隔和间距。因此，金属线58比通孔50更可能遭受光刻胶坍塌问题。根据本公开的一些实施例，使用PR蚀刻工艺或HM蚀刻工艺形成金属线58，同时通孔50使用PR辅助镀工艺形成。根据本公开的替代实施例，使用PR蚀刻工艺和HM蚀刻工艺形成金属线58和通孔50中的每一个。
图25和26示出了根据本公开的一些实施例的使用PR辅助镀工艺形成通孔64(图26)的中间阶段的截面图。参考图25，形成金属晶种层64A。相应的工艺在图35所示的工艺流程中示为工艺316。金属晶种层64A的形成方法和材料可以类似于图9中所示的金属晶种层221，因此这里不再重复。然后形成图案化的光刻胶66，其中开口68与金属线58的部分重叠。相应的工艺也在图35所示的工艺流程中示为工艺316。接下来，在开口68中通过镀形成金属区域64B(其为通孔)。相应的工艺在图35所示的工艺流程中示出为工艺318。在形成金属区域64B之后，去除光刻胶66。接下来，蚀刻金属晶种层64A的暴露部分，并且剩余部分也表示为64A，如图26所示。相应的工艺在图35所示的工艺流程中示为工艺320。金属区域64B和金属晶种层64A的剩余部分组合称为通孔64，如图26所示。
根据替代实施例，使用PR蚀刻工艺或HM蚀刻工艺形成通孔64。虚线70表示当使用PR蚀刻工艺形成通孔64时的通孔64的倾斜侧壁。类似地，是否使用PR蚀刻工艺或HM蚀刻工艺形成通孔64是基于PR的可靠性以及侧壁是否倾斜的偏好来确定的。
参考图27，形成介电层72。各个工艺被示为图35中所示的工艺流程中的工艺322。介电层72的材料和形成方法可以选自用于形成介电层56的候选材料和候选方法。然后应用诸如CMP工艺或机械研磨工艺的平坦化工艺，以平坦化通孔64和介电层72的顶面。根据替代实施例，代替在形成金属线58和通孔64之后形成介电层72，可以在形成金属线58之后并且在形成通孔64之前形成第一介电层，然后进行第一平坦化工艺，并且可以在形成通孔64之后形成第二介电层，然后进行第二平坦化工艺。
图28至图30示出了示例性大间距导电部件74的形成，其可包括金属线和金属焊盘。相应的工艺在图35所示的工艺流程中被示为工艺324。应当理解，可以在通孔64和导电部件74的金属线之间形成额外的金属线和通孔(未示出)，以及额外的金属线和通孔可以使用PR蚀刻工艺，HM蚀刻工艺或PR辅助镀工艺来，其可以基于相应的间距是大间距还是细间距来确定。金属线(可包括导电部件74的金属焊盘)可包括粘合层74A和金属区域74B。导电部件74的金属线和焊盘可以具有大于阈值间距的间距，因此使用PR辅助镀工艺形成。
参考图29，形成介电层76，接着形成接合焊盘(或称为凸块下金属)78，如图30所示。相应的工艺在图35中示出的工艺流程中被示为工艺326。可以使用选自用于形成介电层56的候选材料和候选方法的材料和方法来形成介电层76。接合焊盘78可以由镍，铜，钛或它们的多层形成。根据一些示例性实施例，接合焊盘78包括钛层和位于钛层上方的铜层。
参考图31，还形成可包括焊料区域的电连接器80。电连接器80也称为焊料区域80。在整个说明书中，位于离型膜22上面的结构的部分被称为封装件84，其也可以是包括多个相同的如图所示的封装件的复合晶圆(或重建晶圆)。表面安装器件(SMD)82可以结合到复合晶圆84的顶面。
接下来，将复合晶圆84放置在带(未示出)上，使得复合晶圆84可以从载体20上卸下，例如，通过在离型膜22上投射光，并且光(例如激光束)穿透透明载体20。因此，离型膜22被分解，并且复合晶圆84从载体20释放。
参考图32，在介电缓冲层24中形成开口(由焊料区域95占据)，因此暴露出通孔32。根据本公开的一些实施例，开口通过激光钻孔形成。根据本公开的替代实施例，通过光刻工艺中的蚀刻形成开口。
复合晶圆84包括多个封装件84'(参见图32)，它们彼此相同，每个封装件84'包括多个通孔32和一个或多个器件管芯36。图32示出了封装件86接合在封装件84'上，从而形成叠层封装(PoP)结构/封装件100。通过焊料区域80执行接合。根据本公开的一些实施例，封装件86包括封装衬底88和器件管芯90，器件管芯90可以是存储器管芯，诸如静态随机存取存储器(SRAM)管芯，动态随机存取存储器(DRAM)管芯等。底部填充物92也设置在封装件86和下面的封装件84'之间的间隙中，并固化。
执行分割(管芯锯切)工艺以将复合晶圆84分离成彼此相同的单个封装件。图32还示出了分割的封装件通过焊料区域95接合至封装组件94。根据本发明的一些实施例，封装组件94是封装衬底，其可以是无芯衬底或具有芯的衬底(诸如玻璃纤维增强的芯)。根据本公开的其他实施例，封装组件94是印刷电路板或封装件。图32中的封装件在下文中称为封装件102。
在图32中，包括通孔50和64，金属线58，导电部件74和相应的介电层的RDL组合称为重分布结构104。由于在封装器件管芯36之后形成重分布结构104，封装件84'被称为使用后RDL工艺形成。图33和34示出了使用先RDL工艺形成封装件102，其中在接合和封装器件管芯36之前形成重分布结构104。
参考图33，提供了载体20。在载体20上方形成离型膜22和介电缓冲层24。接下来，在缓冲层24上方形成重分布结构104。根据一些示例性实施例，重分布结构104包括具有金属线106,112和118的导电部件，以及通孔110,114和120位于介电层108,116和122中。每层金属线106,112和118以及通孔110,114和120可以使用选自PR蚀刻工艺，HM蚀刻工艺和PR辅助镀工艺的方法形成，以及所有组合都是预期的。此外，可以基于PR的可靠性(诸如相应的最小间距是否小于阈值间距)、工艺难度、制造成本以及侧壁是否倾斜的偏好来确定是否使用PR蚀刻工艺，HM蚀刻工艺或PR辅助镀工艺来形成导电部件层。因此，可以参考图22至图30中的重分布结构104的形成和图1至图12中所示的工艺来找到重分布结构104的形成工艺，因此不再重复。
图33还示出了形成接合焊盘(或UBM或金属柱)78，焊料区域80以及器件管芯36至接合焊盘78的接合。分配封装材料126，其可以是模塑料或模制底部填充物。在图34中示出了载体20(图33)的分离，分割以及将封装组件89与封装件84'的接合。封装组件可以是封装衬底，印刷电路板等。
根据本公开的一些实施例，如图32和34所示，在形成封装件84'中，确定金属线层的第一阈值间距。使用PR辅助镀工艺形成具有等于或大于第一阈值间距的间距的金属线层中的所有导电部件(金属线和焊盘)，并且使用PR蚀刻工艺或HM蚀刻工艺在金属线层中形成具有小于第一阈值间距的间距的所有导电部件。还确定通孔层的第二阈值间距。使用PR辅助镀工艺形成具有等于或大于第二阈值间距的间距的通孔层中的所有通孔，并且使用PR蚀刻工艺或HM蚀刻工艺形成具有小于第二阈值间距的间距的通孔层中的所有通孔。第一阈值间距可以等于或小于第二阈值间距。
在上面示出的示例性实施例中，根据本公开的一些实施例讨论了一些示例性工艺和部件。还可以包括其他部件和工艺。例如，可以包括测试结构以帮助3D封装件或3DIC器件的验证测试。测试结构可以包括，例如，在重分布层中或在衬底上形成的测试焊盘以允许测试3D封装件或3DIC的测试，探针和/或探针卡的使用等。可以对中间结构以及最终结构执行验证测试。另外，本文所公开的结构和方法可以与测试方法结合使用，所述测试方法结合已知良好管芯的中间验证以增加产量并降低成本。
本公开的实施例具有一些有利特征。通过使用PR蚀刻或HM蚀刻工艺(可替代地称为沉积和蚀刻工艺)在封装件的重分布结构中形成导电部件，封装件中的导电部件的最小间距(没有可靠性问题)可以减少。PR蚀刻工艺和HM蚀刻工艺可以与PR辅助镀工艺组合以实现减小的间距，而不会导致制造成本的不必要的增加。
根据本公开的一些实施例，一种方法包括将器件管芯封装在封装材料中；平坦化器件管芯和封装材料；形成与器件管芯电耦合的多个第一导电部件，其中形成多个第一导电部件包括沉积和蚀刻工艺，包括：沉积毯式含铜层；在毯式含铜层上方形成图案化的光刻胶；并且蚀刻毯式含铜层以将图案化的光刻胶的图案转移到毯式含铜层中。在一个实施例中，多个第一导电部件具有倾斜侧壁，该倾斜侧壁具有小于约85度的倾斜角。在一个实施例中，形成多个第一导电部件还包括在毯式含铜层上方沉积硬掩模；使用图案化的光刻胶作为蚀刻掩模蚀刻硬掩模，其中使用硬掩模作为蚀刻掩模蚀刻毯式含铜层。在一个实施例中，该方法还包括沉积粘合层，其中粘合层和硬掩模由相同的材料形成，其中毯式含铜层在粘合层上方并与粘合层接触。在一个实施例中，该方法还包括使用PR辅助镀工艺形成电耦合至多个第一导电部件的多个第二导电部件，并且PR辅助镀工艺包括沉积金属晶种层；在金属晶种层上方形成额外的图案化的光刻胶；将金属区域镀到额外的图案化的光刻胶中的开口中和金属晶种层上方；去除额外的图案化的光刻胶以暴露部分金属晶种层；并蚀刻金属晶种层的部分。在一个实施例中，多个第一导电部件具有小于多个第二导电部件的第二最小间距的第一最小间距。在一个实施例中，该方法还包括形成多个样品导电部件以确定阈值间距，其中具有小于阈值间距的间距的多个样品导电部件中的金属部件遭受光刻胶坍塌问题，并且具有等于或大于阈值间距的间距的多个样品导电部件中的所有金属部件没有光刻胶坍塌问题，其中第一最小间距小于阈值间距，并且第二最小间距等于或者大于阈值间距。在一个实施例中，多个第一导电部件包括通孔，多个第二导电部件包括金属线，通孔的顶面与金属线的底面物理接触。在一个实施例中，该方法还包括形成耦合到器件管芯的多个导电层，其中多个导电层包括：具有小于阈值间距的最小间距的多个第一导电层；以及具有等于或大于阈值间距的最小间距的多个第二导电层，其中所有多个第一导电层使用额外的沉积和蚀刻工艺形成，并且所有多个第二导电层是使用PR辅助镀工艺形成。
根据本公开的一些实施例，一种方法包括将器件管芯封装在封装材料中；形成与器件管芯电耦合的多个导电部件，包括：使用PR辅助镀工艺形成多个第一导电部件；使用沉积和蚀刻工艺形成多个第二导电部件，其中所述多个第一导电部件和所述多个第二导电部件均包括铜，并且所述多个第一导电部件的第一最小间距大于多个第一导电部件的第二小间距。在一个实施例中，在封装器件管芯之前形成多个导电部件。在一个实施例中，在封装器件管芯之后形成多个导电部件。
根据本公开的一些实施例，一种方法包括形成多个通孔，包括：沉积第一粘合层；在第一粘合层上方沉积毯式含铜层；在毯式含铜层上方形成第一图案化的光刻胶；并且蚀刻毯式含铜层和第一粘合层；沉积第一介电层以嵌入多个通孔；在第一介电层和多个通孔上进行第一平坦化；形成多条金属线，包括：在多个通孔上方沉积与通孔接触的金属晶种层；在金属晶种层上方沉积第二图案化的光刻胶；在第二图案化的光刻胶中镀金属区域；去除第二图案化的光刻胶；蚀刻金属晶种层的部分；沉积第二介电层以嵌入多条金属线；在第二介电层和金属区域上进行第二平坦化。在一个实施例中，通过使用第一图案化的光刻胶作为蚀刻掩模蚀刻毯式含铜层来执行形成多个通孔。在一个实施例中，对毯式含铜层的蚀刻采用形成多个通孔的倾斜侧壁的工艺条件。在一个实施例中，倾斜侧壁具有在约65度和约80度之间的倾斜角。在一个实施例中，形成通孔还包括：在毯式含铜层上方形成硬掩模，其中硬掩模由与第一粘合层相同的材料形成，并且第一图案化的光刻胶位于硬掩模上；使用第一图案化的光刻胶作为蚀刻掩模蚀刻硬掩模，其中使用蚀刻硬掩模作为蚀刻掩模来执行蚀刻毯式含铜层。在一个实施例中，形成金属晶种层包括：沉积第二粘合层；在第二粘合层上方沉积含铜晶种层。
一种结构包括和位于器件管芯上方并且电耦合至器件管芯的多个第一导电部件，其中多个第一导电部件具有第一侧壁，第一侧壁具有小于85度的第一倾斜角；多个第二导电部件在多个第一导电部件上方并且电耦合至多个第一导电部件，其中多个第二导电部件具有第二侧壁，第二侧壁具有大于85度且等于或小于约90度的第二倾斜角。在一个实施例中，多个第二导电部件具有与多个第一导电部件的顶面接触的底面。在一个实施例中，器件管芯包括电连接器，并且其中多个第一导电部件是与器件管芯的电连接器接触的通孔。
根据本发明的一些实施例，提供了一种形成半导体结构的方法，包括：将器件管芯封装在封装材料中；以及形成电耦合至所述器件管芯的多个第一导电部件，其中，形成所述多个第一导电部件包括沉积和蚀刻工艺，包括：沉积毯式含铜层；在所述毯式含铜层上方形成图案化的光刻胶；和蚀刻所述毯式含铜层以将所述图案化的光刻胶的图案转印到所述毯式含铜层中。
在上述方法中，所述多个第一导电部件具有倾斜侧壁，所述倾斜侧壁具有小于85度的倾斜角。
在上述方法中，形成所述多个第一导电部件还包括：在所述毯式含铜层上方沉积硬掩模；和使用所述图案化的光刻胶作为蚀刻掩模蚀刻所述硬掩模，其中，使用蚀刻的所述硬掩模作为蚀刻掩模蚀刻所述毯式含铜层。
在上述方法中，还包括沉积粘合层，其中，所述粘合层和所述硬掩模由相同的材料形成，其中，所述毯式含铜层在所述粘合层上方并与所述粘合层接触。
在上述方法中，在湿蚀刻工艺中蚀刻所述硬掩模。
在上述方法中，在干蚀刻工艺中蚀刻所述硬掩模。
在上述方法中，还包括使用PR辅助镀工艺形成电耦合至所述多个第一导电部件的多个第二导电部件，并且所述PR辅助镀工艺包括：沉积金属晶种层；在所述金属晶种层上方形成额外的图案化的光刻胶；将金属区域镀到额外的图案化的光刻胶中的开口内和金属晶种层上方；去除额外的图案化的光刻胶以暴露所述金属晶种层的部分；和蚀刻所述金属晶种层的部分。
在上述方法中，所述多个第一导电部件具有小于所述多个第二导电部件的第二最小间距的第一最小间距。
在上述方法中，还包括：形成多个样品导电部件以确定阈值间距，其中，具有小于所述阈值间距的间距的多个样品导电部件中的金属部件遭受光刻胶坍塌问题，并且具有等于或大于所述阈值间距的间距的多个样品导电部件中的所有金属部件没有光刻胶坍塌问题，其中，所述第一最小间距小于所述阈值间距，所述第二最小间距等于或大于所述阈值间距。
在上述方法中，所述多个第一导电部件包括通孔，并且所述多个第二导电部件包括金属线，所述通孔的顶面与所述金属线的底面物理接触。
在上述方法中，包括形成耦合到所述器件管芯的多个导电层，其中，所述多个导电层包括：多个第一导电层，具有小于阈值间距的最小间距；和多个第二导电层，具有等于或大于所述阈值间距的最小间距，其中，使用额外的沉积和蚀刻工艺形成所有的多个第一导电层，并且使用PR辅助镀工艺形成所有的多个第二导电层。
根据本发明的另一些实施例，还提供了一种形成半导体结构的方法，包括：形成多个通孔，包括：沉积第一粘合层；在所述第一粘合层上方沉积毯式含铜层；在所述毯式含铜层上方形成第一图案化的光刻胶；和蚀刻所述毯式含铜层和所述第一粘合层；沉积第一介电层以嵌入所述多个通孔；对所述第一介电层和所述多个通孔实施第一平坦化；形成多条金属线，包括：在所述多个通孔上方与沉积所述多个通孔接触的金属晶种层；在所述金属晶种层上方沉积第二图案化的光刻胶；在所述第二图案化的光刻胶中镀金属区域；去除所述第二图案化的光刻胶；和蚀刻所述金属晶种层的部分；沉积第二介电层以嵌入所述多条金属线；和对所述第二介电层和所述金属区域实施第二平坦化。
在上述方法中，通过使用所述第一图案化的光刻胶作为蚀刻掩模蚀刻所述毯式含铜层来执行形成所述多个通孔。
在上述方法中，蚀刻所述毯式含铜层采用形成所述多个通孔的倾斜侧壁的工艺条件。
在上述方法中，所述倾斜侧壁具有介于65度与80度之间的倾斜角。
在上述方法中，形成所述通孔还包括：在毯式含铜层上方形成硬掩模，其中，所述硬掩模由与所述第一粘合层由相同的材料形成，并且所述第一图案化的光刻胶位于所述硬掩模上方；和使用第一图案化的光刻胶作为蚀刻掩模蚀刻所述硬掩模，其中，使用蚀刻的所述硬掩模作为蚀刻掩模来执行蚀刻所述毯式含铜层。
在上述方法中，形成所述金属晶种层包括：沉积第二粘合层；和在所述第二粘合层上方沉积含铜晶种层。
根据本发明的又一些实施例，还提供了一种半导体结构，包括：器件管芯；多个第一导电部件，位于所述器件管芯上方并且电耦合至所述器件管芯，其中，所述多个第一导电部件具有第一侧壁，所述第一侧壁具有小于85度的第一倾斜角；和多个第二导电部件，位于所述多个第一导电部件上方并且电耦合至所述多个第一导电部件，其中，所述多个第二导电部件具有第二侧壁，所述第二侧壁具有大于85度且等于或小于90度的第二倾斜角。
在上述半导体结构中，所述多个第二导电部件具有与所述多个第一导电部件的顶面接触的底面。
在上述半导体结构中，所述器件管芯包括电连接器，并且其中，所述多个第一导电部件是与所述器件管芯的电连接器接触的通孔。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基底来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成半导体结构的方法，包括：
将器件管芯封装在封装材料中；形成电耦合至所述器件管芯的多个第一导电部件，其中，形成所述多个第一导电部件包括沉积和蚀刻工艺，包括：
沉积毯式含铜层；
在所述毯式含铜层上方形成图案化的光刻胶；和
蚀刻所述毯式含铜层以将所述图案化的光刻胶的图案转印到所述毯式含铜层中；以及
形成耦合到所述器件管芯的多个导电层，其中，所述多个导电层包括：
第一导电层，包括多个第二导电部件，其中，当所述多个第二导电部件具有小于阈值间距的第二最小间距时，使用沉积和光刻胶蚀刻工艺或者沉积和硬掩模蚀刻工艺形成所有的所述多个第二导电部件，当所述多个第二导电部件具有等于或大于所述阈值间距的所述第二最小间距时，使用光刻胶辅助镀工艺形成所有的所述多个第二导电部件，所述阈值间距是使用所述光刻胶辅助镀工艺实现的最小间距；和
第二导电层，包括多个第三导电部件，其中，当所述多个第三导电部件具有小于所述阈值间距的第三最小间距时，使用沉积和光刻胶蚀刻工艺或者沉积和硬掩模蚀刻工艺形成所有的所述多个第三导电部件，当所述多个第三导电部件具有等于或大于所述阈值间距的所述第三最小间距时，使用光刻胶辅助镀工艺形成所有的所述多个第三导电部件。
2.根据权利要求1所述的方法，其中，所述多个第一导电部件具有倾斜侧壁，所述倾斜侧壁具有小于85度的倾斜角。
3.根据权利要求1所述的方法，其中，形成所述多个第一导电部件还包括：
在所述毯式含铜层上方沉积硬掩模；以及
使用所述图案化的光刻胶作为蚀刻掩模蚀刻所述硬掩模，其中，使用蚀刻的所述硬掩模作为蚀刻掩模蚀刻所述毯式含铜层。
4.根据权利要求3所述的方法，还包括沉积粘合层，其中，所述粘合层和所述硬掩模由相同的材料形成，其中，所述毯式含铜层在所述粘合层上方并与所述粘合层接触。
5.根据权利要求3所述的方法，其中，在湿蚀刻工艺中蚀刻所述硬掩模。
6.根据权利要求3所述的方法，其中，在干蚀刻工艺中蚀刻所述硬掩模。
7.根据权利要求1所述的方法，其中，所述光刻胶辅助镀工艺包括：
沉积金属晶种层；
在所述金属晶种层上方形成额外的图案化的光刻胶；
将金属区域镀到额外的图案化的光刻胶中的开口内和金属晶种层上方；
去除额外的图案化的光刻胶以暴露所述金属晶种层的部分；以及
蚀刻所述金属晶种层的部分。
8.根据权利要求7所述的方法，其中，利用所述光刻胶辅助镀工艺形成所述多个第二导电部件，所述多个第一导电部件具有小于所述多个第二导电部件的所述第二最小间距的第一最小间距。
9.根据权利要求8所述的方法，还包括：
通过形成多个样品导电部件以确定所述阈值间距，其中，具有小于所述阈值间距的间距的所述多个样品导电部件中的金属部件在通过所述光刻胶辅助镀工艺形成时，遭受光刻胶坍塌问题，而具有等于或大于所述阈值间距的间距的所述多个样品导电部件中的所有金属部件在通过所述光刻胶辅助镀工艺形成时，没有所述光刻胶坍塌问题。
10.根据权利要求7所述的方法，其中，所述多个第一导电部件包括通孔，并且所述多个第二导电部件包括金属线，所述通孔的顶面与所述金属线的底面物理接触。
11.根据权利要求4所述的方法，其中，所述粘合层和所述硬掩模由氮化钛形成。
12.一种形成半导体结构的方法，包括：
利用光刻胶蚀刻工艺形成多个通孔，包括：
沉积第一粘合层；
在所述第一粘合层上方沉积毯式含铜层；
在所述毯式含铜层上方形成第一图案化的光刻胶；和
蚀刻所述毯式含铜层和所述第一粘合层；
沉积第一介电层以嵌入所述多个通孔；
对所述第一介电层和所述多个通孔实施第一平坦化；
利用光刻胶辅助镀工艺形成多条金属线，包括：
在所述多个通孔上方与沉积所述多个通孔接触的金属晶种层；
在所述金属晶种层上方沉积第二图案化的光刻胶；
在所述第二图案化的光刻胶中镀金属区域；
去除所述第二图案化的光刻胶；和
蚀刻所述金属晶种层的部分；
沉积第二介电层以嵌入所述多条金属线；以及
对所述第二介电层和所述金属区域实施第二平坦化，
其中，所述多个通孔具有小于阈值间距的第一最小间距，所述多条金属线具有等于或大于所述阈值间距的第二最小间距，其中，所述阈值间距是使用所述光刻胶辅助镀工艺实现的最小间距。
13.根据权利要求12所述的方法，其中，通过使用所述第一图案化的光刻胶作为蚀刻掩模蚀刻所述毯式含铜层来执行形成所述多个通孔。
14.根据权利要求13所述的方法，其中，蚀刻所述毯式含铜层采用形成所述多个通孔的倾斜侧壁的工艺条件。
15.根据权利要求14所述的方法，其中，所述倾斜侧壁具有介于65度与80度之间的倾斜角。
16.根据权利要求12所述的方法，其中，形成所述通孔还包括：
在毯式含铜层上方形成硬掩模，其中，所述硬掩模由与所述第一粘合层由相同的材料形成，并且所述第一图案化的光刻胶位于所述硬掩模上方；和
使用第一图案化的光刻胶作为蚀刻掩模蚀刻所述硬掩模，其中，使用蚀刻的所述硬掩模作为蚀刻掩模来执行蚀刻所述毯式含铜层。
17.根据权利要求12所述的方法，其中，形成所述金属晶种层包括：
沉积第二粘合层；和
在所述第二粘合层上方沉积含铜晶种层。
18.一种半导体结构，包括：
器件管芯；
多个第一导电部件，位于所述器件管芯上方并且电耦合至所述器件管芯，其中，所述多个第一导电部件具有第一侧壁，所述第一侧壁具有小于85度的第一倾斜角；以及
多个第二导电部件，位于所述多个第一导电部件上方并且电耦合至所述多个第一导电部件，其中，所述多个第二导电部件具有第二侧壁，所述第二侧壁具有大于85度且等于或小于90度的第二倾斜角，
其中，所述多个第一导电部件通过光刻胶蚀刻工艺形成且具有小于阈值间距的第一最小间距，所述多个第二导电部件通过光刻胶辅助镀工艺形成具有等于或大于所述阈值间距的第二最小间距，其中，所述阈值间距是使用所述光刻胶辅助镀工艺实现的最小间距。
19.根据权利要求18所述的半导体结构，其中，所述多个第二导电部件具有与所述多个第一导电部件的顶面接触的底面。
20.根据权利要求18所述的半导体结构，其中，所述器件管芯包括电连接器，并且其中，所述多个第一导电部件是与所述器件管芯的电连接器接触的通孔。
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