CN109801849B - 封装件及其形成方法 - Google Patents

封装件及其形成方法 Download PDF

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Publication number
CN109801849B
CN109801849B CN201811131295.0A CN201811131295A CN109801849B CN 109801849 B CN109801849 B CN 109801849B CN 201811131295 A CN201811131295 A CN 201811131295A CN 109801849 B CN109801849 B CN 109801849B
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copper
etch
seed layer
etching
redistribution lines
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CN109801849A (zh
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蔡惠榕
谢昀蓁
彭竣翔
张岱民
雷弋昜
郭宏瑞
余振华
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种方法包括将器件密封在密封材料中，平坦化密封材料和器件，以及在密封材料和器件上方形成导电部件。导电部件的形成包括沉积第一导电材料以形成第一晶种层，在第一晶种层上方沉积与第一导电材料不同的第二导电材料以形成第二晶种层，在第二晶种层上方镀金属区，对第二晶种层实施第一蚀刻，并且对第一晶种层实施第二蚀刻，并且在蚀刻第一晶种层之后，对第二晶种层和金属区实施第三蚀刻。本发明的实施例还涉及封装件及其形成方法。

Description

封装件及其形成方法
技术领域
本发明的实施例涉及封装件及其形成方法。
背景技术
随着半导体技术的发展，半导体芯片/管芯变得越来越小。同时，需要将更多功能集成在半导体管芯中。因此，半导体管芯需要将越来越多的I/O焊盘封装到较小的区域内，并且因此I/O焊盘的密度随着时间迅速提升。结果，半导体管芯的封装变得更加困难，这会对封装产量产生不利影响。
传统的封装技术可以划分为两类。在第一类中，晶圆上的管芯在它们被分割之前进行封装。这种封装技术具有诸如较大的生产量和较低的成本的一些有利特征。此外，需要较少的底部填充物或模塑料。然而，这种封装技术还具有缺陷。由于管芯的尺寸正变得越来越小，并且相应的封装件仅可以是扇入型封装件，其中，每个管芯的I/O焊盘限制于位于相应管芯的表面正上方的区域。由于管芯的面积有限，由于I/O焊盘的间距的限制，I/O焊盘的数量受到限制。如果焊盘的间距减小，则可能发生焊料桥接。此外，在固定的焊球尺寸的需求下，焊球必须具有特定的尺寸，这进而限制了可以封装在管芯表面上的焊球的数量。
在另一类封装中，管芯在被封装之前从晶圆上分割下来。该封装技术的有利特征是形成扇出型封装件的可能性，这意味着管芯上的I/O焊盘可以分布至比管芯更大的区域，并且因此可以增大封装在管芯的表面上的I/O焊盘的数量。该封装技术的另一有利特征是封装“已知良好管芯”，以及丢弃缺陷管芯，并且因此不会在缺陷管芯上浪费成本和精力。
在扇出封装件中，将器件管芯密封在模塑料中，然后平坦化模塑料以暴露器件管芯。在器件管芯上方形成介电层。在介电层中形成再分布线以连接至器件管芯。扇出封装件还可以包括穿过模塑料的贯通孔。
发明内容
本发明的实施例提供了一种形成封装件的方法，包括：将器件密封在密封材料中；平坦化所述密封材料和所述器件；以及在所述密封材料和所述器件上方形成导电部件，其中，形成所述导电部件包括：沉积第一导电材料以形成第一晶种层；在所述第一晶种层上方沉积与所述第一导电材料不同的第二导电材料以形成第二晶种层；在所述第二晶种层上方镀金属区；对所述第二晶种层实施第一蚀刻；对所述第一晶种层实施第二蚀刻；以及在蚀刻所述第一晶种层之后，对所述第二晶种层和所述金属区实施第三蚀刻。
本发明的另一实施例提供了一种形成封装件的方法，包括：形成粘合层；在所述粘合层上方形成多个含铜部件；选择性地蚀刻所述粘合层，从而去除所述粘合层的不位于所述多个含铜部件下方的部分和所述粘合层的位于所述多个含铜部件下方的横向底切部分，以形成底切；以及选择性地蚀刻所述多个含铜部件以减少所述底切。
本发明的又一实施例提供了一种封装件，包括：器件管芯；密封剂，将所述器件管芯密封在所述密封剂中；第一多个再分布线(RDL)，位于所述器件管芯上方并且电连接至所述器件管芯，其中，所述第一多个再分布线具有第一间距，并且所述第一多个再分布线没有底切；以及第二多个再分布线，位于所述器件管芯上方并且电连接至所述器件管芯，其中，所述第二多个再分布线具有大于所述第一间距的第二间距，并且所述第二多个再分布线具有底切。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1至图26示出根据一些实施例的形成封装件的中间阶段的截面图。
图27示出根据一些实施例的不具有贯通孔的封装件的截面图。
图28至图35示出根据一些实施例的形成封装件的中间阶段的截面图。
图36A、图36B和图37示出根据一些实施例的一些RDL的轮廓。
图38示出根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
根据各个示例性实施例，提供了集成扇出(InFO)封装件及其形成方法。根据一些实施例示出形成InFO封装件的中间阶段。讨论了一些实施例的一些变化。贯穿各个图和示例性实施例，相同的参考标号用于指定相同的元件。
图1至图26示出根据一些实施例的形成封装件的中间阶段的截面图。图1至图26所示的步骤还在图38所示的工艺流程200中示意性地示出。
参考图1，提供了载体20，并且在载体20上涂覆释放膜22。相应工艺在图38所示的工艺流程中示出为步骤202。载体20由透明材料形成，并且可以是玻璃载体、陶瓷载体、有机载体等。载体20可具有圆形顶视图形状。释放膜22与载体20的顶面物理接触。释放膜22可以由光-热转换(LTHC)涂覆材料形成，并且可以通过涂覆施加到载体20上。根据本发明的一些实施例，LTHC涂覆材料能够在光/辐射(诸如激光)的热量下分解，并且因此可以从形成在其上的结构释放载体20。
根据本发明的一些实施例，如图1所示，在LTHC涂覆材料22上形成介电缓冲层24。相应工艺还在图38所示的工艺流程中示出为步骤202。根据一些实施例，介电缓冲层24由诸如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等的聚合物形成。
图2和图3示出形成金属杆32。参考图2，例如，通过物理汽相沉积(PVD)来形成金属晶种层26。相应工艺在图38所示的工艺流程中示出为步骤204。根据本发明的一些实施例，金属晶种层26包括钛层和位于钛层上方的铜层。在金属晶种层26上方形成光刻胶28。然后使用光刻掩模(未示出)对光刻胶28实施曝光。在后续的显影之后，在光刻胶28中形成开口30。通过开口30暴露金属晶种层26的一些部分。
接下来，例如通过在开口30中镀金属材料来形成金属杆32。相应工艺还在图38所示的工艺流程中示出为步骤204。金属杆32可选地称为贯通孔或贯模制通孔，因为它们将穿过后续在最终封装件中形成的密封材料(可以是模塑料)。镀的金属材料可以是铜或铜合金。金属杆32的顶面低于光刻胶28的顶面，从而使得通过开口30限定金属杆32的形状。金属杆32可以具有大致垂直和笔直的边缘。可选地，在截面图中，金属杆32可以具有沙时计形状，其中，金属杆32的中间部分比相应的顶部部分和底部部分更窄。
在后续步骤中，去除图案化的光刻胶28，并且因此暴露下面的金属晶种层26的部分。然后在例如各向异性蚀刻步骤或各向同性蚀刻步骤中的蚀刻步骤中去除金属晶种层26的暴露部分。因此，剩余的晶种层26的边缘可以与金属杆32的相应的上面部分共末端或大致共末端，或可以从相应的上面的镀材料的相应边缘横向凹进，因此具有底切。在图3中示出所得到的金属杆32，其中，未示出底切。在整个描述中，金属晶种层26的剩余部分(图3)认为是金属杆32的部分。金属杆32的顶视图形状包括但不限于圆形、矩形、六边形、八边形等。在形成金属杆32之后，暴露介电缓冲层24。
图4示出放置/附接器件36(可选地称为封装组件)。相应工艺在图38所示的工艺流程中示出为步骤206。器件36可以是器件管芯，并且因此在下文中称为器件管芯36，同时器件36也可以是封装件、管芯堆叠件等。器件管芯36通过管芯附接膜(DAF)34附接至介电缓冲层24，其中，该管芯附接膜是在将器件管芯36放置在介电缓冲层24上之前在器件管芯36上预先附接的粘合膜。器件管芯36可以包括具有与相应的下面的DAF 34物理接触的背面(朝下的表面)的半导体衬底。器件管芯36可以包括位于半导体衬底的正面(朝上的表面)处的诸如有源器件的集成电路器件(包括晶体管，未示出)。根据本发明的一些实施例，器件管芯36包括一个或多个逻辑管芯，其中，该逻辑管芯可以是中央处理单元(CPU)管芯、图形处理单元(GPU)管芯、移动应用管芯、微控制单元(MCU)管芯、输入-输出(IO)管芯、基带(BB)管芯或应用处理器(AP)管芯。由于载体20是晶圆级载体，尽管示出一个器件管芯36，但是在管芯放置步骤中可以在介电缓冲层24上方放置多个相同组的器件管芯36，并且可以将器件管芯组分配为包括多行和多列的阵列。
根据一些示例性实施例，金属柱42(诸如铜柱)预先形成为器件管芯36的部分，并且金属柱42通过下面的金属焊盘40(可以是，例如，铝焊盘)电连接至器件管芯36中的诸如晶体管(未示出)的集成电路器件。尽管在每个器件36中示出一个金属焊盘40和一个金属柱42，但是每个器件36可以包括多个金属焊盘和多个上面的金属柱42。根据本发明的一些实施例，诸如聚合物层44的介电层填充位于同一器件管芯中的相邻金属柱42之间的间隙以作为顶部介电层。钝化层43也可以位于聚合物层44下面。顶部介电层44还可以包括覆盖和保护金属柱42的部分。根据本发明的一些实施例，聚合物层44可以由PBO或聚酰亚胺形成。应当理解，通过本发明的实施例可以预期，器件管芯36可具有包括不同的顶部介电层的不同设计。
接下来，参考图5，将器件管芯36和金属杆32密封在密封材料48中。相应工艺在图38所示的工艺流程中示出为步骤208。因此，金属杆32在下文中称为贯通孔。密封材料48填充位于相邻的贯通孔32之间的间隙以及位于贯通孔32和器件管芯36之间的间隙。密封材料48可以是模塑料、模制底部填充物、环氧树脂和/或树脂。密封材料48的顶面高于金属柱42和贯通孔32的顶端。密封材料48可包括基底材料48A和位于基底材料48A中的填料颗粒48B，其中，基底材料可以是聚合物、树脂、环氧树脂等。填料颗粒可以是诸如SiO2、Al2O3、硅石等的介电材料的颗粒，并且可以具有球形形状。而且，如根据一些实例所示出的，球形填料颗粒48B可以具有相同或不同的直径。
在后续步骤中，如图5所示，实施诸如化学机械抛光(CMP)步骤或机械研磨步骤的平坦化步骤以削薄密封材料48和介电层44，直到暴露贯通孔32和金属柱42。也可以轻微抛光贯通孔32和金属柱42以确保暴露贯通孔32和金属柱42。由于平坦化工艺，贯通孔32的顶端与金属柱42的顶面大致齐平(共面)，并且与密封材料48的顶面大致共面。如图5所示，由于平坦化工艺，部分地抛光位于模制的密封材料48的顶部处的一些填料颗粒48B，导致一些填料颗粒的顶部被去除，并且留下底部。因此，所得到的部分填料颗粒将具有平坦的顶面，其中，该平坦的顶面与基底材料48A、贯通孔32和金属柱42的顶面共面。
图6至图22示出形成前侧再分布结构。图6至图10示出形成通孔和相应的介电层。参考图6，金属晶种层50形成为毯式层，其中，该金属晶种层50可以包括粘合层50A和含铜层50B。相应工艺在图38所示的工艺流程中示出为步骤210。粘合层50A包括与铜不同的金属，并且可以包括钛、钽、氮化钛、氮化钽等。含铜层50B可以由纯的或大致纯的(例如，具有大于约95％的百分比)铜或铜合金形成。在金属晶种层50上方形成图案化的光刻胶52，并且例如通过光刻工艺形成开口54。相应工艺还在图38所示的工艺流程中示出为步骤210。
接下来，如图7所示，例如，通过镀(可以是电化学镀)在开口54中形成通孔56。相应工艺在图38所示的工艺流程中示出为步骤212。通孔56可以由铜或铜合金形成。在用于形成通孔56的镀之后，去除光刻胶52。相应工艺在图38所示的工艺流程中示出为步骤214。
接下来，实施三步蚀刻工艺。在三步蚀刻工艺的第一步中，去除含铜层50B的位于去除的光刻胶52正下方的部分。相应工艺在图38所示的工艺流程中示出为步骤216。蚀刻可以是湿蚀刻或干蚀刻，并且可以是各向同性蚀刻工艺。蚀刻化学品可以包括H3PO4、H2O2和H2O的混合物，H2SO4、H2O2和H2O的混合物，(NH4)2S2O8和H2O的混合物，HCl溶液，HCl和CuCl2的混合物，FeCl3溶液以及它们的组合。
在蚀刻含铜层50B之后，暴露粘合层50A。然后实施第二蚀刻工艺。相应工艺在图38所示的工艺流程中示出为步骤218。可以使用湿蚀刻来蚀刻粘合层50A。选择蚀刻化学品/溶液以侵蚀粘合层50A，并且不侵蚀含铜层50B和通孔56。蚀刻化学品/溶液可包括酸性或碱性化学品/溶液，诸如HF溶液、HF/H2O2的混合物、H2O2(具有一些其他添加剂)、NaHCO3、NaOH、NaHCO3/H2O2的混合物、NaHCO3/NaOH/H2O2的混合物或碱金属氢氧化物水溶液。碱金属氢氧化物水溶液可以是NaOH、KOH等的溶液。在整个描述中，含铜层50B的剩余部分和上面的通孔56组合称为通孔60。
如图8所示，在通孔60的边缘部分正下方形成底切58，其中，该底切58是由粘合层50A的横向过蚀刻导致的。根据本发明的一些实施例，底切58的宽度W1大于约0.1μm，并且可以在约0.1μm和约0.5μm之间，这取决于相应蚀刻剂的蚀刻选择性和蚀刻能力。底切导致通孔60的可靠性降低，特别是当通孔60具有在约1μm和约6μm之间(诸如约4μm)的范围内的小间距(例如，小于阈值间距)和/或通孔60的宽度W2小于约2μm时。间距可以是相邻部件的中间线之间的距离、相邻部件的左边缘之间的距离或相邻部件的右边缘之间的距离。当底切58的宽度W1大于通孔60的W2的10％时，底切可能导致通孔60的变形和/或分层。
根据本发明的一些实施例，实施再蚀刻工艺(三步蚀刻中的第三蚀刻步骤)以减小通孔60的横向尺寸，从而使得在减小的通孔60下方没有底切。相应工艺在图38所示的工艺流程中示出为步骤220。这样命名再蚀刻是由于已经在第一蚀刻步骤中蚀刻了通孔56和含铜层50B。选择蚀刻化学品/溶液以侵蚀通孔60，并且不侵蚀粘合层50A。蚀刻化学品可包括H3PO4、H2O2和H2O的混合物，H2SO4、H2O2和H2O的混合物，(NH4)2S2O8和H2O的混合物，HCl溶液、HCl和CuCl2的混合物，FeCl3溶液以及它们的组合。蚀刻化学品可以是酸性的，包括一些上述酸性化学品。蚀刻可以是湿蚀刻，并且可以是各向同性蚀刻工艺。在再蚀刻中，通孔60比粘合层50A横向收缩得更多，并且因此至少减少或消除了底切。在再蚀刻工艺之后，可以存在零底切(例如，底切的宽度为零，或小于约0.1μm)。在零底切的情况下，通孔60的边缘可以与下面的粘合层50A的边缘齐平或大致齐平。由于工艺变化，一些粘合层50A可以具有与相应的上面的通孔60的边缘齐平的边缘，而位于同一封装件中的一些其他粘合层50A可以横向延伸超过相应的上面的通孔60的边缘(该效应称为基脚)。去除底切导致通孔60的可靠性得到改善。
根据本发明的一些实施例，为了确定用于产生零底切的期望的工艺条件，可以通过实验确定用于蚀刻通孔60的工艺条件。例如，可以制造多个样品晶圆，并且在样品晶圆中形成包括具有底切的通孔60的结构。应当意识到，底切的量与通孔60和粘合层50A的材料有关，并且与用于蚀刻粘合层50A和通孔60的工艺条件有关。因此，使用不同的工艺条件蚀刻多个样品晶圆，其中，该工艺条件包括例如不同的蚀刻持续时间、不同浓度的蚀刻化学品、不同的温度、不同的蚀刻化学品等，从而使得可以确定产生零底切的工艺条件。然后使用用于形成通孔60和蚀刻通孔60的工艺条件在产品晶圆上形成通孔60以进行批量生产。在图9中示出所得到的具有零底切的通孔60。
参考图10，形成介电层62。根据本发明的一些实施例，介电层62由诸如PBO、聚酰亚胺等的聚合物形成。该形成包括以可流动的形式涂覆介电层62，并且然后固化介电层62。根据本发明的可选实施例，介电层62由诸如氮化硅、氧化硅等的无机介电材料形成。形成方法可以包括化学汽相沉积(CVD)、原子层沉积(ALD)、等离子体增强化学汽相沉积(PECVD)或其他可应用的沉积方法。然后应用诸如CMP工艺或机械研磨工艺的平坦化工艺以平坦化通孔60和介电层62的顶面。相应工艺在图38所示的工艺流程中示出为步骤222。
接下来，图11至图18示出形成金属线和上面的通孔。参考图11，形成金属晶种层64。相应工艺在图38所示的工艺流程中示出为步骤224。金属晶种层64形成为毯式层，其中，金属晶种层64可包括粘合层64A和含铜层64B。粘合层64包括与铜不同的金属，并且可以包括钛、钽、氮化钛、氮化钽等。在金属晶种层64上方形成图案化的光刻胶66，并且例如通过曝光和显影形成开口68。相应工艺还在图38所示的工艺流程中示出为步骤224。
接下来，如图12所示，例如，通过镀(可以是电化学镀)在开口68中形成金属线70。相应工艺在图38所示的工艺流程中示出为步骤226。金属线70可以由铜或铜合金形成。在用于形成金属线70的镀之后，去除光刻胶66，并且在图13中示出所得到的结构。相应工艺在图38所示的工艺流程中示出为步骤228。
接下来，参考图14，在不蚀刻金属晶种层64的情况下，形成并图案化光刻胶72以形成开口74，其中，通过开口74暴露金属线70。相应工艺在图38所示的工艺流程中示出为步骤230。在后续步骤中，如图15所示，例如，通过镀在开口74中形成通孔76。相应工艺在图38所示的工艺流程中示出为步骤232。可以形成通孔76而不形成另一毯式晶种层，因为此时仍然存在毯式晶种层64以用作毯式导电层。通孔76可以由铜或铜合金的均质材料形成。虚线示出为标记金属线70连接上面的通孔76的位置。
然后去除光刻胶72，暴露下面的金属晶种层64的部分。在图16中示出所得到的结构。相应工艺在图38所示的工艺流程中示出为步骤234。接下来，实施另一个三步蚀刻工艺的第一蚀刻步骤和第二蚀刻步骤，形成图17所示的结构。在第一蚀刻工艺中蚀刻含铜层64B。相应工艺在图38所示的工艺流程中示出为步骤236。蚀刻可以是使用侵蚀含铜层64B(以及金属线70和通孔76)并且不侵蚀粘合层64A的化学品的各向同性蚀刻，然后实施第二蚀刻工艺，其中，蚀刻粘合层64A。相应工艺在图38所示的工艺流程中示出为步骤238。蚀刻可以是使用侵蚀粘合层64A并且不侵蚀金属线70和通孔76的化学品的各向同性蚀刻。可以分别在层50A和50B的蚀刻的讨论(图8)中找到蚀刻层64A和64B的细节，并且在此不再重复。在所得到的结构中，含铜层64B的部分和上面的金属线70的组合称为金属线71。可以在金属线71下方形成底切77。
接下来，在第三蚀刻步骤中，再蚀刻金属线71和通孔76以消除或至少减少底切77。相应工艺在图38所示的工艺流程中示出为步骤240。在图18中示出所得到的结构。蚀刻可以是使用同时侵蚀金属线71和通孔76并且不侵蚀粘合层64A的化学品的各向同性蚀刻。蚀刻化学品和工艺条件以及用于确定最佳蚀刻工艺条件的工艺类似于用于形成通孔60的工艺，并且可以在形成通孔60的讨论中找到。在蚀刻工艺中，金属线71和通孔76的横向尺寸减小，导致消除或至少减少底切。此外，也减小金属线71和通孔76的高度，并且金属线71和通孔76的角部可以被圆化。
参考图18，形成介电层78。根据本发明的一些实施例，介电层78由材料形成，并且使用选自相同组的候选材料和用于形成介电层62的候选方法的方法。因此这里不再重复细节。然后实施诸如CMP工艺或机械研磨工艺的平坦化工艺以平坦化通孔76和介电层78的顶面。在图19中示出所得到的结构。
图20和图21示出形成粘合层80A、金属线82、通孔84和介电层86。粘合层80A、金属线82、通孔84和介电层86的形成的细节可以与粘合层64A、金属线71、通孔76和介电层78的形成大致相同，并且因此这里不再重复。
图22和图23示出形成粘合层88A、金属线和金属焊盘(下文中称为金属线/焊盘)90和介电层92。细节也可以与粘合层64A、金属线71、通孔76和介电层78的形成大致相同，并且因此这里不再重复。根据可选实施例，选择性地跳过粘合层88A的再蚀刻步骤，并且在金属线/焊盘90下方存在底切。还如图23所示，在介电层92中形成开口94以暴露金属线/焊盘90中的金属焊盘。
图24示出根据一些示例性实施例形成凸块下金属(UBM)96和电连接件98。根据本发明的一些实施例，UBM 96形成为延伸至位于介电层92中的开口中以接触金属线/焊盘90中的金属焊盘。UBM 96可以由镍、铜、钛或它们的多层形成。根据一些示例性实施例，UBM 96包括钛层和位于钛层上方的铜层。
然后形成电连接件98。形成电连接件98可以包括镀非焊料金属柱，其可以是铜柱。还可以通过镀并且然后进行回流来形成焊帽100。在整个描述中，包括位于释放膜22上方的所有组件的组合的结构称为封装件102，其中，该封装件可以是包括多个器件管芯36的复合晶圆(并且下文中也称为复合晶圆102)。
接下来，在例如通过将光投射到释放膜22上，并且光(这种激光束)穿过透明载体20来将复合晶圆102从载体20上卸下之后，可以将复合晶圆102放置在带(未示出)上。因此，分解释放膜22，并且从载体20释放复合晶圆102。在图25中示出所得到的复合晶圆102。
参考图26，在介电缓冲层24中形成开口(由焊料区122占据)，并且因此暴露贯通孔32。根据本发明的一些实施例，通过激光钻孔形成开口。根据本发明的可选实施例，通过光刻工艺中的蚀刻形成开口。
复合晶圆102包括彼此相同的多个封装件102’(参见图26)，其中，每个封装件102’包括多个贯通孔32和一个或多个器件管芯36。图26示出封装件104与封装件102’的接合，从而形成叠层封装(PoP)结构/封装件300。通过焊料区100实施该接合。根据本发明的一些实施例，封装件104包括封装衬底106和器件管芯108，其中，该器件管芯108可以是诸如静态随机存取存储器(SRAM)管芯、动态随机存取存储器(DRAM)管芯等的存储器管芯。还在位于封装件104和下面的封装件102’之间的间隙中设置底部填充物128，并且进行固化。
实施分割(管芯锯切)工艺以将复合晶圆102分离成彼此相同的单独的封装件。图26示出通过焊料区122将分割的封装件接合至封装组件120。根据本发明的一些实施例，封装组件120是封装衬底，其中，该封装衬底可以是无核心衬底或具有核心的衬底。根据本发明的其他实施例，封装组件120是印刷电路板或封装件。在下文中图26中的封装件称为封装件126。
图27示出根据可选实施例形成封装件126。图27中所示的封装件类似于图26中所示的封装件，除了未形成图26中的贯通孔32之外。因此，封装组件120接合至封装件102’。
图28至图35示出根据本发明的一些实施例的在形成封装件的中间阶段的截面图。除非另有声明，这些实施例中的组件的材料和形成方法与相同的组件大致相同，其中，相同的组件由图1至图26所示实施例中的相同的参考标号表示。因此，可以在图1至图26所示实施例的讨论中找到关于图28至图35所示组件的形成工艺和材料的细节。
这些实施例的初始步骤与图1至图5中所示的步骤大致相同。接下来，形成介电层130，并且在介电层130中形成通孔开口132以暴露贯通孔32和金属柱42。介电层130可以由选自用于形成介电层62(图10)的相同组候选材料的材料形成。
参考图29，形成金属晶种层134，并且金属晶种层134可以包括粘合层134A和含铜层134B。粘合层134A和含铜层134B的组成和形成方法可以分别类似于粘合层50A和含铜层50B(图6)的组成和形成方法，并且因此这里不再重复。然后形成图案化的光刻胶136，其中，形成开口138以暴露下面的晶种层134。接下来，如图30所示，实施镀工艺，从而在金属晶种层134上形成通孔140和金属线142。在下文中，通孔140和金属线142组合称为再分布线144。根据本发明的一些实施例，通孔140和金属线142可以由铜或铜合金形成。
在后续步骤中，去除光刻胶136，并且因此暴露下面的金属晶种层134的部分。然后实施三步骤蚀刻工艺。首先，在第一蚀刻步骤和第二蚀刻步骤中蚀刻金属晶种层134的暴露部分。蚀刻工艺条件和相应的化学品类似于参考图7和图8讨论的用于蚀刻金属晶种层50的蚀刻工艺条件和化学品。结果，如图31所示，形成底切146。在整个描述中，金属线142和通孔140认为包括下面的含铜层134B的剩余部分(图29)作为它们的底部。
接下来，在各向同性蚀刻工艺中实施再蚀刻，并且在图32中示出所得到的结构。如参考图8中所示的工艺所讨论的，可以使用从用于蚀刻金属晶种层50的相同组的化学品选择的化学品来实施再蚀刻。因此这里不再重复工艺细节。在再蚀刻之后，金属线142的横向尺寸减小，从而使得金属线142的边缘可以与粘合层134A的相应边缘齐平。如果没有大致消除，至少减少如图31所示的底切146。
图33示出形成介电层148、含金属晶种层150A、通孔156和金属线158。在下文中，通孔156和金属线158组合称为RDL 160。形成工艺可以与用于形成介电层130、粘合层134A、通孔140和金属线142的工艺大致相同，并且因此这里不讨论细节。而且，通孔156和金属线158包括下面的含铜晶种层的剩余部分。
图34示出形成介电层92、UBM 96、金属柱98和焊料区100，从而形成复合晶圆102。在后续步骤中，从载体20上拆卸下复合晶圆102。后续步骤类似于参考图25和图26所示和讨论的步骤，并且因此这里不讨论细节。在图35中示出所得到的封装件126。
通过再蚀刻诸如含铜金属线的含铜区和通孔，可以消除或减少底切，并且所得到的封装件的可靠性得到改善。实验结果表明，当形成用于细间距金属线和通孔(例如，间距小于阈值间距，可以在约1μm和约6μm之间)的底切时，所得结构的可靠性受到不利影响。另一方面，当形成用于大间距金属线和通孔(例如，间距大于阈值间距)的底切时，所得结构的可靠性不会受到不利影响。根据本发明的一些实施例，可以对样品晶圆实施实验以形成诸如RDL(包括金属线和通孔)和具有不同间距和宽度的金属焊盘的样品导电部件，并且测试样品导电部件的可靠性。因此，可以确定阈值间距，其中，具有等于或大于阈值间距的间距的样品导电部件是可靠的并且不会遭受变形和分层问题，并且可以认为这些样品导电部件具有大间距。具有小于阈值间距的间距的样品导电部件可能遭受变形和分层问题，并且可以认为这些样品导电部件具有细间距。
根据本发明的一些实施例，可以对小间距RDL(导电部件)实施再蚀刻以消除/减少底切，并且不对大间距RDL实施再蚀刻以消除/减少底切。通过区分细间距和大间距RDL的形成并选择性地对细间距RDL进行再蚀刻，可靠性得到改善，并且由于节约了对大间距RDL的再蚀刻的额外成本，而不会不必要地增加制造成本。例如，参考图26所示的结构，下部RDL层(诸如60、71、86和84的金属线和通孔以及下面的粘合层)可以具有小间距，并且因此可以采用再蚀刻工艺来形成，同时可以跳过再蚀刻工艺来形成上部层(诸如金属线/焊盘90和金属柱98)。结果，一些RDL(诸如下部RDL层)和部件可能没有底切，而一些其他RDL(诸如上部RDL层和金属柱98)可能具有底切。在一些其他示例性实施例中，例如，参考图35所示的结构，下部RDL层(金属线和通孔)(诸如RDL 144)可具有小间距，并且因此可采用再蚀刻工艺形成，同时可以跳过再刻蚀工艺来形成上部层(诸如RDL 160)。结果，一些RDL(诸如RDL 144)和部件可能没有底切，而同一封装件中的一些其他RDL(诸如RDL 160和金属柱98)可以具有底切。
此外，在封装件的形成中，在没有再蚀刻的情况下，所有RDL和金属焊盘可以形成为具有等于或大于阈值间距的间距，并且因此具有底切。另一方面，可以使用三步蚀刻来使所有RDL和金属焊盘形成为具有小于阈值间距的间距。
图36A和图36B和图37示出根据本发明的一些实施例的RDL中的通孔和金属线的可能轮廓。在图36A和图36B和图37中，粘合层172A表示图26和图35所示实施例中的位于金属晶种层中的粘合层，并且部件174表示图26和图35所示实施例中的位于RDL中的金属线和通孔。在用于减少底切的再蚀刻中，由于部件134的角部区比平坦表面蚀刻得更多，因此部件174的角部是圆形的。根据本发明的一些实施例，圆角的半径R1可以大于约0.05μm，并且可以在约0.05μm和约1μm之间的范围内，这取决于消除底切的需求，和部件174的尺寸。另一方面，即使在与部件174相同的封装件中，不实施再蚀刻的RDL也具有更尖锐的角部。
而且，在图36A和图36B和图37中，虚线用于表示粘合层172A可以横向延伸超过上面的部件174的相应边缘，这称为基脚轮廓。这可能是由工艺变化导致的，从而使得一些部件174比同一封装件中的其他部件174蚀刻得更多。例如，在同一芯片中，一些RDL可以具有零底切，而一些其他RDL可以具有基脚轮廓。
在上述示例性实施例中，根据本发明的一些实施例讨论了一些示例性工艺和部件。也可以包括其他部件和工艺。例如，可以包括测试结构以辅助三维(3D)封装或3DIC器件的验证测试。测试结构可以包括例如形成在再分布层中或衬底上的测试焊盘，以允许使用探针和/或探针卡等测试3D封装或3DIC。可以对中间结构以及最终结构实施验证测试。额外地，本文公开的结构和方法可以与测试方法结合使用，该测试方法结合了已知良好管芯的中间验证以增加产量并降低成本。
本发明的实施例具有一些有利特征。通过实施三步蚀刻工艺以形成RDL，消除或减少了RDL中的底切，并且RDL的可靠性得到改善。
根据本发明的一些实施例，一种方法包括将器件密封在密封材料中，平坦化密封材料和器件，以及在密封材料和器件上方形成导电部件。形成导电部件包括沉积第一导电材料以形成第一晶种层，在第一晶种层上方沉积与第一导电材料不同的第二导电材料以形成第二晶种层，在第二晶种层上方镀金属区，对第二晶种层实施第一蚀刻，并且对第一晶种层实施第二蚀刻，并且在蚀刻第一晶种层之后，对第二晶种层和金属区实施第三蚀刻。在实施例中，使用大致不侵蚀第一晶种层的化学品来实施第三蚀刻。在实施例中，第一晶种层包括钛，并且第二晶种层包括铜。在实施例中，第三蚀刻包括湿蚀刻。在实施例中，通过第二蚀刻产生底切，并且第三蚀刻消除底切。在实施例中，该方法包括形成多个样品，其中，每个样品包括与导电部件的结构类似的结构，其中，形成多个样品包括使用不同的蚀刻工艺条件蚀刻多个样品；并且从不同的蚀刻工艺条件中选择导致样品具有最小底切的工艺条件，其中，使用该工艺条件实施形成导电部件。在实施例中，镀金属区包括第一镀工艺以形成金属线；以及第二镀工艺以在金属线上方形成通孔并且通孔连接至金属线，其中，通孔比金属线更窄，并且在第三蚀刻期间，蚀刻金属线和通孔两者。
根据本发明的一些实施例，一种方法包括形成包括粘合层的金属晶种层；在金属晶种层上方形成多个含铜部件；蚀刻金属晶种层，其中，金属晶种层的剩余部分与含铜部件重叠，并且彼此物理分离；以及对多个含铜部件实施蚀刻，其中在蚀刻中，多个含铜部件的横向尺寸比金属晶种层的其余部分中的粘合层的相应的下面部分减小得更多。在实施例中，蚀刻金属晶种层包括使用第一化学溶液实施的蚀刻步骤，并且使用与第一化学溶液不同的第二化学溶液对多个含铜部件实施蚀刻。在实施例中，在蚀刻金属晶种层之后对多个含铜部件实施蚀刻。在实施例中，在蚀刻金属晶种层之后，在含铜部件的边缘部分下方产生底切，并且其中，在对多个含铜部件进行蚀刻之后，减少了底切。在实施例中，通过对多个含铜部件进行的蚀刻来消除底切。在实施例中，粘合层由与含铜部件的材料不同的材料形成。在实施例中，在对多个含铜部件进行的蚀刻期间，大致不蚀刻粘合层。
根据本发明的一些实施例，一种方法包括沉积钛晶种层；在钛晶种层上方沉积铜晶种层；在铜晶种层上方形成第一图案化的掩模，其中，在第一图案化的掩模中形成第一开口；在第一开口镀金属线；去除第一图案化的掩模；在金属线和铜晶种层上方形成第二图案化的掩模以暴露金属线的部分，其中，在第二图案化的掩模中形成第二开口；在金属线和第二开口上方镀通孔；去除第二图案化的掩模；对铜晶种层实施第一蚀刻，直到去除铜晶种层的未被金属线覆盖的暴露部分，并且暴露钛晶种层的部分；对钛晶种层实施第二蚀刻以去除钛晶种层的部分，其中，钛晶种层相对于金属线横向凹进以形成底切；以及对金属线和铜晶种层实施第三蚀刻，以至少减少底切。在实施例中，通过第三蚀刻消除底切。在实施例中，在第三蚀刻中，蚀刻金属线和通孔两者。在实施例中，第三蚀刻是各向同性蚀刻。在实施例中，第三蚀刻包括湿蚀刻。在实施例中，在第三蚀刻中，大致不蚀刻钛晶种层。
本发明的实施例提供了一种形成封装件的方法，包括：将器件密封在密封材料中；平坦化所述密封材料和所述器件；以及在所述密封材料和所述器件上方形成导电部件，其中，形成所述导电部件包括：沉积第一导电材料以形成第一晶种层；在所述第一晶种层上方沉积与所述第一导电材料不同的第二导电材料以形成第二晶种层；在所述第二晶种层上方镀金属区；对所述第二晶种层实施第一蚀刻；对所述第一晶种层实施第二蚀刻；以及在蚀刻所述第一晶种层之后，对所述第二晶种层和所述金属区实施第三蚀刻。
在上述方法中，其中，所述第一晶种层包括钛、钽、氮化钛或氮化钽，并且所述第二晶种层和所述金属区均包括铜。
在上述方法中，其中，所述第三蚀刻包括湿蚀刻。
在上述方法中，其中，通过所述第二蚀刻产生底切，并且所述第三蚀刻消除所述底切。
在上述方法中，其中，处于相同层级的所述导电部件和相邻导电部件具有间距，并且其中，对所述第二晶种层和所述金属区实施所述第三蚀刻包括在所述间距小于4μm时，对所述第二晶种层和所述金属区实施所述第三蚀刻。
在上述方法中，其中，镀所述金属区包括：第一镀工艺，以形成金属线；以及第二镀工艺，用于在所述金属线上方形成通孔并且所述通孔连接至所述金属线，其中，所述通孔比所述金属线更窄，并且在所述第三蚀刻期间，蚀刻所述金属线和所述通孔。
在上述方法中，其中，所述第一蚀刻和所述第二蚀刻是单独的蚀刻步骤。
本发明的另一实施例提供了一种形成封装件的方法，包括：形成粘合层；在所述粘合层上方形成多个含铜部件；选择性地蚀刻所述粘合层，从而去除所述粘合层的不位于所述多个含铜部件下方的部分和所述粘合层的位于所述多个含铜部件下方的横向底切部分，以形成底切；以及选择性地蚀刻所述多个含铜部件以减少所述底切。
在上述方法中，其中，蚀刻所述粘合层包括使用第一化学溶液实施的蚀刻步骤，并且使用与所述第一化学溶液不同的第二化学溶液对所述多个含铜部件实施蚀刻。
在上述方法中，其中，在选择性地蚀刻所述多个含铜部件之后，所述多个含铜部件和下面的粘合层的剩余部分形成通孔。
在上述方法中，其中，使用选自由H3PO4、H2O2和H2O的混合物，H2SO4、H2O2和H2O的混合物，(NH4)2S2O8和H2O的混合物，HCl溶液，HCl和CuCl2的混合物，FeCl3溶液以及它们的组合构成的组中的化学品来实施所述多个含铜部件的选择性蚀刻。
在上述方法中，其中，通过对所述多个含铜部件进行蚀刻来消除所述底切。
在上述方法中，其中，所述粘合层由与含铜部件的材料不同的材料形成。
在上述方法中，其中，使用酸性化学品蚀刻所述粘合层，并且使用碱性化学品蚀刻所述多个含铜部件。
本发明的又一实施例提供了一种封装件，包括：器件管芯；密封剂，将所述器件管芯密封在所述密封剂中；第一多个再分布线(RDL)，位于所述器件管芯上方并且电连接至所述器件管芯，其中，所述第一多个再分布线具有第一间距，并且所述第一多个再分布线没有底切；以及第二多个再分布线，位于所述器件管芯上方并且电连接至所述器件管芯，其中，所述第二多个再分布线具有大于所述第一间距的第二间距，并且所述第二多个再分布线具有底切。
在上述封装件中，其中，所述第二多个再分布线位于所述第一多个再分布线上方。
在上述封装件中，其中，与所述第一多个再分布线处于相同层级的所有再分布线没有底切，并且与所述第二多个再分布线处于相同层级的所有再分布线具有底切。
在上述封装件中，其中，位于所述第一多个再分布线下方和所述器件管芯上方的层级处的所有再分布线没有底切，并且位于比所述第二多个再分布线更高层级处的所有再分布线具有底切。
在上述封装件中，其中，位于所述器件管芯上方并且具有等于或大于阈值间距的间距的所有再分布线具有底切，并且位于所述器件管芯上方并且具有小于所述阈值间距的间距的所有再分布线没有底切。
在上述封装件中，其中，所述第二多个再分布线包括：粘合层；以及含铜区，位于所述粘合层中的相应粘合层上方，其中，所述底切与所述含铜区重叠并且与所述粘合层处于相同的层级。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成封装件的方法，包括：
将器件密封在密封材料中；
平坦化所述密封材料和所述器件；以及
在所述密封材料和所述器件上方形成导电部件，其中，形成所述导电部件包括：
沉积第一导电材料以形成第一晶种层；
在所述第一晶种层上方沉积与所述第一导电材料不同的第二导电材料以形成第二晶种层；
在所述第二晶种层上方镀金属区；
对所述第二晶种层实施第一蚀刻；
对所述第一晶种层实施第二蚀刻，其中，通过所述第二蚀刻产生底切；以及
在蚀刻所述第一晶种层之后，对所述第二晶种层和所述金属区实施第三蚀刻，其中，所述第三蚀刻消除所述底切。
2.根据权利要求1所述的方法，其中，所述第一晶种层包括钛、钽、氮化钛或氮化钽，并且所述第二晶种层和所述金属区均包括铜。
3.根据权利要求1所述的方法，其中，所述第三蚀刻包括湿蚀刻。
4.根据权利要求1所述的方法，其中，所述第三蚀刻包括各向同性蚀刻。
5.根据权利要求1所述的方法，其中，处于相同层级的所述导电部件和相邻导电部件具有间距，并且其中，对所述第二晶种层和所述金属区实施所述第三蚀刻包括在所述间距小于4μm时，对所述第二晶种层和所述金属区实施所述第三蚀刻。
6.根据权利要求1所述的方法，其中，镀所述金属区包括：
第一镀工艺，以形成金属线；以及
第二镀工艺，用于在所述金属线上方形成通孔并且所述通孔连接至所述金属线，其中，所述通孔比所述金属线更窄，并且在所述第三蚀刻期间，蚀刻所述金属线和所述通孔。
7.根据权利要求1所述的方法，其中，所述第一蚀刻和所述第二蚀刻是单独的蚀刻步骤。
8.一种形成封装件的方法，包括：
形成粘合层；
在所述粘合层上方形成多个含铜部件；
选择性地蚀刻所述粘合层，从而去除所述粘合层的不位于所述多个含铜部件下方的部分和所述粘合层的位于所述多个含铜部件下方的横向底切部分，以形成底切；以及
选择性地蚀刻所述多个含铜部件以减少所述底切。
9.根据权利要求8所述的方法，其中，蚀刻所述粘合层包括使用第一化学溶液实施的蚀刻步骤，并且使用与所述第一化学溶液不同的第二化学溶液对所述多个含铜部件实施蚀刻。
10.根据权利要求9所述的方法，其中，在选择性地蚀刻所述多个含铜部件之后，所述多个含铜部件和下面的粘合层的剩余部分形成通孔。
11.根据权利要求8所述的方法，其中，使用选自由H3PO4、H2O2和H2O的混合物，H2SO4、H2O2和H2O的混合物，(NH4)2S2O8和H2O的混合物，HCl溶液，HCl和CuCl2的混合物，FeCl3溶液以及它们的组合构成的组中的化学品来实施所述多个含铜部件的选择性蚀刻。
12.根据权利要求11所述的方法，其中，通过对所述多个含铜部件进行蚀刻来消除所述底切。
13.根据权利要求8所述的方法，其中，所述粘合层由与含铜部件的材料不同的材料形成。
14.根据权利要求8所述的方法，其中，使用酸性化学品蚀刻所述粘合层，并且使用碱性化学品蚀刻所述多个含铜部件。
15.一种封装件，包括：
器件管芯；
密封剂，将所述器件管芯密封在所述密封剂中；
第一多个再分布线(RDL)，位于所述器件管芯上方并且电连接至所述器件管芯，其中，所述第一多个再分布线具有第一间距，并且所述第一多个再分布线没有底切；以及
第二多个再分布线，位于所述器件管芯上方并且电连接至所述器件管芯，其中，所述第二多个再分布线具有大于所述第一间距的第二间距，并且所述第二多个再分布线具有底切，
其中，所述第一多个再分布线中的再分布线包括：
粘合层；和
含铜区，位于所述粘合层上方并且与所述粘合层接触，其中，所述粘合层的边沿横向延伸超过所述含铜区的相应边沿。
16.根据权利要求15所述的封装件，其中，所述第二多个再分布线位于所述第一多个再分布线上方。
17.根据权利要求15所述的封装件，其中，与所述第一多个再分布线处于相同层级的所有再分布线没有底切，并且与所述第二多个再分布线处于相同层级的所有再分布线具有底切。
18.根据权利要求15所述的封装件，其中，位于所述第一多个再分布线下方和所述器件管芯上方的层级处的所有再分布线没有底切，并且位于比所述第二多个再分布线更高层级处的所有再分布线具有底切。
19.根据权利要求15所述的封装件，其中，位于所述器件管芯上方并且具有等于或大于阈值间距的间距的所有再分布线具有底切，并且位于所述器件管芯上方并且具有小于所述阈值间距的间距的所有再分布线没有底切。
20.根据权利要求15所述的封装件，其中，所述第二多个再分布线包括：
粘合层；以及
含铜区，位于所述粘合层中的相应粘合层上方，其中，所述底切与所述含铜区重叠并且与所述粘合层处于相同的层级。
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