TW201923864A - 半導體結構及其形成方法 - Google Patents

半導體結構及其形成方法 Download PDF

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TW201923864A
TW201923864A TW107132241A TW107132241A TW201923864A TW 201923864 A TW201923864 A TW 201923864A TW 107132241 A TW107132241 A TW 107132241A TW 107132241 A TW107132241 A TW 107132241A TW 201923864 A TW201923864 A TW 201923864A
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Taiwan
Prior art keywords
etching
copper
metal
seed layer
layer
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TW107132241A
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English (en)
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TWI727205B (zh
Inventor
蔡惠榕
余振華
郭宏瑞
雷弋昜
彭竣翔
謝昀蓁
張岱民
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台灣積體電路製造股份有限公司
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Abstract

一種方法，包含：將裝置包封於包封材料中；平坦化包封材料及裝置；以及在包封材料及裝置上方形成導電特徵。導電特徵的形成包含：沈積第一導電材料以形成第一晶種層；在第一晶種層上方沈積不同於第一導電材料的第二導電材料以形成第二晶種層；在第二晶種層上方鍍覆金屬區；對第二晶種層執行第一蝕刻；對第一晶種層執行第二蝕刻；以及在蝕刻第一晶種層之後，對第二晶種層及金屬區執行第三蝕刻。

Description

半導體結構及其形成方法
隨著半導體技術的發展，半導體晶片/晶粒正變得愈來愈小。同時，更多功能需要整合至半導體晶粒中。因此，半導體晶粒需要具有包裝於較小區域中的愈來愈大數目個I/O襯墊，且I/O襯墊的密度隨時間推移而快速升高。結果，半導體晶粒的封裝變得較困難，此不利地影響封裝的良率。
習知封裝技術可劃分成兩種類別。在第一類別中，封裝晶圓上的晶粒，隨後對晶粒進行鋸割。此封裝技術具有一些有利的特徵，諸如較大產量及較低成本。另外，需要較少底部填充料或模製化合物。然而，此封裝技術亦遭逢缺點。由於晶粒的大小正變得愈來愈小，且各別封裝體可能僅為扇入型封裝體，其中每一晶粒的I/O襯墊限於在各別晶粒的表面正上方的區。隨著晶粒的面積受限，I/O襯墊的數目歸因於I/O襯墊的節距限制而受到限制。若襯墊的節距減小，則可能出現焊橋（solder bridge）。另外，在固定的球大小要求下，焊球必須具有某一大小，此舉又限制可包裝於晶粒的表面上的焊球的數目。
在封裝的另一類別中，自晶圓鋸割晶粒，隨後將晶粒封裝。此封裝技術的有利特徵為形成扇出型封裝體的可能性，此意謂可將晶粒上的I/O襯墊重佈至比晶粒大的區域，且因此可增大包裝於晶粒的表面上的I/O襯墊的數目。此封裝技術的另一有利特徵為封裝「已知良好晶粒」且捨棄有缺陷的晶粒，且因此不在有缺陷的晶粒上浪費成本及精力。
在扇出型封裝體中，裝置晶粒包封於模製化合物中，模製化合物接著經平坦化以暴露裝置晶粒。介電層形成於裝置晶片上方。重佈線形成於介電層中以連接至裝置晶粒。扇出型封裝體亦可包含穿透模製化合物的穿孔。
以下揭露內容提供用於實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及配置的特定實例以簡化本揭露內容。當然，此等組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方（on）或上（over）的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵及第二特徵可能不直接接觸的實施例。另外，本揭露內容可在各種實例中重複圖式元件符號及/或字母。此重複是出於簡化及清楚的目的，且本身並不指示所論述的各種實施例及/或組態之間的關係。
另外，為易於描述，可在本文中使用諸如「在……之下」、「在......下方」、「下部」、「上覆於」、「上部」及其類似者的空間相對術語以描述一個元件或特徵與另一元件或特徵的關係，如圖中所說明。除圖中所描繪的定向以外，空間相對術語意欲亦涵蓋裝置在使用或操作中的不同定向。設備可按其他方式定向（旋轉90度或處於其他定向）且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據各種例示性實施例提供積體扇出型（Integrated Fan-Out；InFO）封裝體以及形成封裝體的方法。根據一些實施例說明形成InFO封裝體的中間階段。論述一些實施例的一些變型。通篇的各視圖及說明性實施例，相同的圖式元件符號用以指明相同元件。
圖1至圖26說明根據一些實施例的封裝體的形成中的中間階段的橫截面圖。圖1至圖26中所繪示的步驟亦示意性地說明於圖38中所繪示的製程流程200中。
參看圖1，提供載體20，且將離型膜22塗佈於載體20上。各別製程在圖38中所繪示的製程流程中說明為步驟202。載體20由透明材料形成，且可為玻璃載體、陶瓷載體、有機載體或其類似者。載體20可具有圓形俯視形狀。離型膜22與載體20的頂表面實體接觸。離型膜22可由光熱轉換（Light-To-Heat-Conversion；LTHC）塗佈材料形成，且可經由塗佈而塗覆至載體20上。根據本揭露內容的一些實施例，LTHC塗佈材料在光/輻射（諸如，雷射）的熱量下能夠分解，且因此可自其上形成的結構釋放載體20。
根據本揭露內容的一些實施例，如圖1中所繪示，介電緩衝層24形成於LTHC塗佈材料22上。各別製程在圖38中所繪示的製程流程中亦說明為步驟202。根據一些實施例，介電緩衝層24由諸如聚苯并噁唑（polybenzoxazole；PBO）、聚醯亞胺、苯并環丁烯（benzocyclobutene；BCB）或其類似者的聚合物形成。
圖2及圖3說明金屬支柱32的形成。參看圖2，金屬晶種層26例如經由物理氣相沈積（Physical Vapor Deposition；PVD）形成。各別製程在圖38中所繪示的製程流程中說明為步驟204。根據本揭露內容的一些實施例，金屬晶種層26包含鈦層及在鈦層上方的銅層。光阻28形成於金屬晶種層26上方。接著使用光微影罩幕（未圖示）對光阻28執行曝光。在後續顯影之後，開口30形成於光阻28中。金屬晶種層26的一些部分經由開口30暴露。
接下來，例如藉由將金屬材料鍍覆於開口30中來形成金屬支柱32。各別製程在圖38中所繪示的製程流程中亦說明為步驟204。金屬支柱32替代地被稱作穿孔或模製穿孔（through-molding via），此是因為其將穿透最終封裝體中的後續形成的包封材料（其可為模製化合物）。經鍍覆金屬材料可為銅或銅合金。金屬支柱32的頂表面低於光阻28的頂表面，以使得金屬支柱32的形狀受開口30限制。金屬支柱32可具有實質上豎直且筆直的邊緣。替代地，金屬支柱32在橫截面圖中可具有砂時計（sand timer）形狀，其中金屬支柱32的中間部分比各別頂部部分及底部部分窄。
在後續步驟中，移除經圖案化光阻28，且因此暴露金屬晶種層26的下伏部分。接著在蝕刻步驟中，例如在非等向性蝕刻步驟或等向性蝕刻步驟中移除金屬晶種層26的所暴露部分。因此，剩餘晶種層26的邊緣可與金屬支柱32的各別上覆部分同邊界或實質上同邊界，或可自各別上覆鍍覆材料的各別邊緣側向地凹進（recess），因此具有底切割。所得金屬支柱32說明於圖3中，其中未繪示底切割。貫穿本說明書，金屬晶種層26（圖3）的剩餘部分被視為金屬支柱32的部分。金屬支柱32的俯視形狀包含但不限於圓形形狀、矩形、六邊形、八邊形以及其類似者。在形成金屬支柱32之後，暴露介電緩衝層24。
圖4說明裝置36（替代地被稱作封裝組件)的置放/附接。各別製程在圖38中所繪示的製程流程中說明為步驟206。裝置36可為裝置晶粒，且因此在下文中被稱作裝置晶粒36，同時裝置36亦可為封裝體、晶粒堆疊或其類似者。裝置晶粒36經由晶粒貼合膜（Die-Attach Film；DAF）34附接至介電緩衝層24，晶粒貼合膜34是在將裝置晶粒36置放於介電緩衝層24上之前預先附接於裝置晶粒36上的黏著膜。裝置晶粒36可包含具有與各別下伏DAF 34實體接觸的背表面（面朝下的表面）的半導體基底。裝置晶粒36可包含在半導體基底的前表面（面朝上的表面）處的積體電路裝置，諸如主動裝置，其包含電晶體（未圖示）。根據本揭露內容的一些實施例，裝置晶粒36包含一或多個邏輯晶粒，其可為中央處理單元（Central Processing Unit；CPU）晶粒、圖形處理單元（Graphic Processing Unit；GPU）晶粒、行動應用程式晶粒、微型控制單元（Micro Control Unit；MCU）晶粒、輸入輸出（input-output；IO）晶粒、基頻（BaseBand；BB）晶粒或應用程式處理器（Application processor；AP）晶粒。由於載體20為晶圓級載體，因此儘管說明一個裝置晶粒36，但裝置晶粒36的多個相同群組可在晶粒置放步驟中置放於介電緩衝層24上方，且裝置晶粒群組可作為包含多個列及多個行的陣列來分配。
根據一些例示性實施例，金屬柱42（諸如，銅柱）預成型為裝置晶粒36的部分，且金屬柱42經由可為例如鋁襯墊的下伏金屬襯墊40電耦接至裝置晶粒36中的積體電路裝置，諸如電晶體（未圖示）。儘管一個金屬襯墊40及一個金屬柱42說明為在裝置36中的每一者中，但裝置36中的每一者可包含多個金屬襯墊及多個上覆金屬柱42。根據本揭露內容的一些實施例，諸如聚合物層44的介電層作為頂部介電層填充同一裝置晶粒中的相鄰金屬柱42之間的間隙。保護層43亦可在聚合物層44之下。頂部介電層44亦可包含覆蓋及防護金屬柱42的部分。根據本揭露內容的一些實施例，聚合物層44可由PBO或聚醯亞胺形成。應瞭解，裝置晶粒36可具有包含由本揭露內容的實施例涵蓋的不同頂部介電層的不同設計。
接下來，參看圖5，裝置晶粒36及金屬支柱32包封於包封材料48中。各別製程在圖38中所繪示的製程流程中說明為步驟208。因此，金屬支柱32在下文中被稱作穿孔。包封材料48填充相鄰穿孔32之間的間隙以及穿孔32與裝置晶粒36之間的間隙。包封材料48可為模製化合物、模製底部填充料、環氧樹脂及/或樹脂。包封材料48的頂表面高於金屬柱42及穿孔32的頂端。包封材料48可包含基質材料48A，其可為聚合物、樹脂、環氧樹脂或其類似者，且填充劑粒子48B在基質材料48A中。填充劑粒子可為諸如SiO2 、Al2 O3 、二氧化矽或其類似者的介電材料的粒子，且可具有球面形狀。並且，球面填充劑粒子48B可具有相同或不同直徑，如根據一些實例所說明。
在後續步驟中，亦如圖5中所繪示，執行諸如化學機械研磨（Chemical Mechanical Polish；CMP）步驟或機械磨光（Mechanical grinding）步驟的平坦化步驟以使包封材料48及介電層44薄化，直至穿孔32及金屬柱42全部暴露。穿孔32及金屬柱42亦可經稍微研磨以確保暴露穿孔32及金屬柱42兩者。歸因於平坦化製程，穿孔32的頂端實質上與金屬柱42的頂表面齊平（共平面），且實質上與包封材料48的頂表面共平面。歸因於平坦化製程，模製的包封材料48的頂部處的一些填充劑粒子48B經部分研磨，使得一些填充劑粒子中的頂部部分被移除，且底部部分保留，如圖5中所繪示。所得部分填充劑粒子因此將具有平坦頂表面，此平坦頂表面與基質材料48A、穿孔32以及金屬柱42的頂表面共平面。
圖6至圖22說明前側重佈線結構的形成。圖6至圖10說明通孔及各別介電層的形成。參看圖6，金屬晶種層50形成為毯覆層（blanket layer），其可包含黏著層50A及含銅層50B。各別製程在圖38中所繪示的製程流程中說明為步驟210。黏著層50A包含不同於銅的金屬，且可包含鈦、鉭、氮化鈦、氮化鉭或其類似者。含銅層50B可由純銅或實質上純銅（例如，百分比大於約95百分比）或銅合金形成。經圖案化光阻52形成於金屬晶種層50上方，且開口54例如經由光微影製程形成。各別製程在圖38中所繪示的製程流程中亦說明為步驟210。
接下來，如圖7中所繪示，通孔56例如經由可為電化學鍍覆的鍍覆形成於開口54中。各別製程在圖38中所繪示的製程流程中說明為步驟212。通孔56可由銅或銅合金形成。在用於形成通孔56的鍍覆之後，移除光阻52。各別製程在圖38中所繪示的製程流程中說明為步驟214。
接下來，執行三步蝕刻製程。在三步蝕刻製程中的第一步中，移除含銅層50B的在經移除光阻52正下方的部分。各別製程在圖38中所繪示的製程流程中說明為步驟216。蝕刻可為濕式蝕刻或乾式蝕刻，且可為等向性蝕刻製程。蝕刻化學品可包含：H3 PO4 、H2 O2 以及H2 O的混合物；H2 SO4 、H2 O2 以及H2 O的混合物；(NH4 )2 S2 O8 及H2 O的混合物；HCl溶液；HCl及CuCl2 的混合物；FeCl3 溶液；以及其組合。
在蝕刻含銅層50B之後，暴露黏著層50A。接著執行第二蝕刻製程。各別製程在圖38中所繪示的製程流程中說明為步驟218。可使用濕式蝕刻來蝕刻黏著層50A。選擇蝕刻化學品/溶液以侵蝕黏著層50A，但不侵蝕含銅晶種層50B及通孔56。蝕刻化學品/溶液可包含酸性或鹼性化學品/溶液，諸如以下溶液：氟化氫（HF）、HF/H2 O2 的混合物、H2 O2 （具有一些其他添加劑）、NaHCO3 、NaOH、NaHCO3 /H2 O2 的混合物、NaHCO3 /NaOH/H2 O2 的混合物，或鹼金屬氫氧化物水溶液。鹼金屬氫氧化物水溶液可為NaOH、KOH或其類似者的溶液。通篇描述中，銅晶種層50B及上覆通孔56的剩餘部分組合地被稱作通孔60。
如圖8中所繪示，存在形成於通孔60的邊緣部分正下方的底切割58，底切割58是由黏著層50A的側向過度蝕刻引起。根據本揭露內容的一些實施例，底切割58的寬度W1大於約0.1 µm，且取決於各別蝕刻劑的蝕刻選擇性及蝕刻能力，可介於約0.1 µm與約0.5 µm之間。底切割使通孔60的可靠性降級，尤其在通孔60具有例如小於臨限節距（threshold pitch）的小節距及/或通孔60的寬度W2小於約2 µm時，臨限節距可在介於約1 µm與約6 µm之間的範圍內（諸如，約4 µm）。節距可為相鄰特徵的中間線之間的距離、相鄰特徵的左邊緣之間的距離或相鄰特徵的右邊緣之間的距離。當底切割58的寬度W1大於通孔60的W2的10%時，底切割可能引起通孔60的變形及/或分層（delamination）。
根據本揭露內容的一些實施例，執行再蝕刻（re-etching）製程(三步蝕刻中的第三蝕刻步驟)以減小通孔60的橫向尺寸，使得在減小的通孔60下方不存在底切割。各別製程在圖38中所繪示的製程流程中說明為步驟220。再蝕刻如此命名是因為通孔56及含銅層50B在第一蝕刻步驟中已被蝕刻。選擇蝕刻化學品/溶液以侵蝕通孔60，但不侵蝕黏著層50A。蝕刻化學品可包含：H3 PO4 、H2 O2 以及H2 O的混合物；H2 SO4 、H2 O2 以及H2 O的混合物；(NH4 )2 S2 O8 及H2 O的混合物；HCl溶液；HCl及CuCl2 的混合物；FeCl3 溶液；以及其組合。蝕刻化學品可為酸性的，包含前述酸性化學品中的一些。蝕刻可為濕式蝕刻，且可為等向性蝕刻製程。在再蝕刻中，通孔60相比黏著層50A側向收縮更多，且因此至少減小或消除底切割。在再蝕刻製程之後，可存在零底切割（例如，其中底切割的寬度為零或小於約0.1 µm）。在零底切割的情況下，通孔60的邊緣可與下伏黏著層50A的邊緣齊平或實質上齊平。歸因於製程變化，黏著層50A中的一些可具有與各別上覆通孔60的邊緣齊平的邊緣，而同一封裝體中的一些其他黏著層50A可側向地延伸超出各別上覆通孔60的邊緣（所述效應被稱作基腳（footing））。移除底切割致使通孔60可靠性之改良。
根據本揭露內容的一些實施例，為判定用於產生零底切割的合乎需要的製程條件，可經由實驗判定用於蝕刻通孔60的製程條件。舉例而言，可製造多個樣品晶圓，且包含具有底切割的通孔60的結構形成於樣品晶圓中。應理解，底切割的量與通孔60及黏著層50A的材料有關，且與用於蝕刻黏著層50A及通孔60的製程條件有關。因此，使用不同製程條件蝕刻多個樣品晶圓使得可產生零底切割的製程條件可被判定，不同製程條件包含例如不同蝕刻持續時間、蝕刻化學品的不同濃度、不同溫度、不同蝕刻化學品或其類似者。用於形成通孔60及蝕刻通孔60的製程條件接著用以在製造晶圓上形成通孔60以用於大批量生產。具有零底切割的所得通孔60說明於圖9中。
參看圖10，形成介電層62。根據本揭露內容的一些實施例，介電層62由諸如PBO、聚醯亞胺或其類似者的聚合物形成。形成包含塗佈具有可流動形式的介電層62，且接著固化介電層62。根據本揭露內容的替代實施例，介電層62由諸如氮化矽、氧化矽或其類似者的無機介電材料形成。形成方法可包含化學氣相沈積（Chemical Vapor Deposition；CVD）、原子層沈積（Atomic Layer Deposition；ALD）、電漿增強型化學氣相沈積（Plasma-Enhanced Chemical Vapor Deposition；PECVD）或其他可應用的沈積法。接著應用諸如CMP製程或機械磨光製程的平坦化製程以平坦化通孔60及介電層62的頂表面。各別製程在圖38中所繪示的製程流程中說明為步驟222。
接下來，圖11至圖18說明金屬線及上覆通孔的形成。參看圖11，形成金屬晶種層64。各別製程在圖38中所繪示的製程流程中說明為步驟224。金屬晶種層64形成為毯覆層，其可包含黏著層64A及含銅層64B。黏著層64A包含不同於銅的金屬，且可包含鈦、鉭、氮化鈦、氮化鉭或其類似者。經圖案化光阻66形成於金屬晶種層64上方，且開口68例如經由曝光及顯影形成。各別製程在圖38中所繪示的製程流程中亦說明為步驟224。
接下來，如圖12中所繪示，金屬線70例如經由可為電化學鍍覆的鍍覆形成於開口68中。各別製程在圖38中所繪示的製程流程中說明為步驟226。金屬線70可由銅或銅合金形成。在用於形成金屬線70的鍍覆之後，移除光阻66且所得結構繪示於圖13中。各別製程在圖38中所繪示的製程流程中說明為步驟228。
接下來，參看圖14，在不蝕刻金屬晶種層64的情況下，形成及圖案化光阻72以形成開口74，金屬線70經由開口暴露。各別製程在圖38中所繪示的製程流程中說明為步驟230。在後續步驟中，如圖15中所繪示，通孔76例如經由鍍覆形成於開口74中。各別製程在圖38中所繪示的製程流程中說明為步驟232。可不形成另一毯覆式晶種層來形成通孔76，此是因為毯覆式晶種層64此時仍存在以充當毯覆式導電層。通孔76可由可為銅或銅合金的均質材料形成。繪示虛線以標記金屬線70在何處接合上覆通孔76。
接著移除光阻72，從而顯露金屬晶種層64的下伏部分。所得結構繪示於圖16中。各別製程在圖38中所示出的製程流程中說明為步驟234。接下來，執行另一三步蝕刻製程中的第一蝕刻步驟及第二蝕刻步驟，從而形成圖17中所繪示的結構。在第一蝕刻製程中蝕刻含銅層64B。各別製程在圖38中所示出的製程流程中說明為步驟236。蝕刻可為使用侵蝕含銅層64B（以及金屬線70及通孔76）但不侵蝕黏著層64A的化學品進行的等向性蝕刻。接著執行第二蝕刻製程，其中蝕刻黏著層64A。各別製程在圖38中所示出的製程流程中說明為步驟238。蝕刻可為使用侵蝕黏著層64A但不侵蝕金屬線70及通孔76的化學品進行的等向性蝕刻。蝕刻層64A及64B的細節可分別見於蝕刻層50A及50B（圖8）的論述中且在本文中不重複。在所得結構中，含銅層64B及上覆金屬線70的部分組合地被稱作金屬線71。底切割77可形成於金屬線71下方。
接下來，在第三蝕刻步驟中，再蝕刻金屬線71及通孔76以消除或至少減小底切割77。各別製程在圖38中所示出的製程流程中說明為步驟240。所得結構繪示於圖18中。蝕刻可為使用同時侵蝕金屬線71及通孔76但不侵蝕黏著層64A的化學品進行的等向性蝕刻。蝕刻化學品及製程條件以及用於判定最佳蝕刻製程條件的製程類似於用於形成通孔60的彼等各者，且可見於形成通孔60的論述中。在蝕刻製程中，金屬線71及通孔76的橫向尺寸減小，使得消除或至少減小底切割。此外，金屬線71及通孔76的高度亦減小，且金屬線71及通孔76的拐角可能圓化。
參看圖18，形成介電層78。根據本揭露內容的一些實施例，介電層78由選自用於形成介電層62的相同候選材料群組的材料且使用選自用於形成介電層62的候選方法的方法形成。因此，在本文中不重複細節。接著執行諸如CMP製程或機械磨光製程的平坦化製程以平坦化通孔76及介電層78的頂表面。所得結構繪示於圖19中。
圖20及圖21說明黏著層80A、金屬線82、通孔84以及介電層86的形成。黏著層80A、金屬線82、通孔84以及介電層86的形成的細節可基本上與含金屬層64A、金屬線71、通孔76以及介電層78的形成相同，且因此在本文中不重複。
圖22及圖23說明黏著層88A、金屬線及金屬襯墊（在下文中被稱作金屬線/襯墊）90以及介電層92的形成。細節亦可基本上與黏著層64A、金屬線71、通孔76以及介電層78的形成相同，且因此在本文中不重複。根據替代實施例，選擇性地跳過黏著層88A的再蝕刻步驟，且底切割存在於金屬線/襯墊90之下。亦如圖23中所繪示，開口94形成於介電層92中以暴露金屬線/襯墊90中的金屬襯墊。
圖24說明根據一些例示性實施例的凸塊下金屬（Under-Bump Metallurgy；UBM）96及電連接件98的形成。根據本揭露內容的一些實施例，UBM 96形成為延伸至介電層92中的開口中以接觸金屬線/襯墊90中的金屬襯墊。UBM 96可由鎳、銅、鈦或其多層形成。根據一些例示性實施例，UBM 96包含鈦層及在鈦層上方的銅層。
接著形成電連接件98。電連接件98的形成可包含鍍覆非焊料金屬柱，其可為銅柱。亦可形成焊蓋100，其可被鍍覆且接著回焊。通篇描述中，包含上覆於離型膜22的所有組件的結構組合地被稱作封裝體102，其可為包含多個裝置晶粒36的複合晶圓（且在下文中亦被稱作複合晶圓102）。
接下來，在複合晶圓102例如藉由將光（此雷射光束）投射於離型膜22上而自載體20卸下之後，複合晶圓102可置放於載帶（未圖示）上，且光穿過透明載體20。由此分解離型膜22，且複合晶圓102自載體20釋放。所得複合晶圓102繪示於圖25中。
參考圖26，開口（由焊料區122佔據）形成於介電緩衝層24中，且因此暴露穿孔32。根據本揭露內容的一些實施例，開口經由雷射鑽孔形成。根據本揭露內容的替代實施例，開口經由微影製程中的蝕刻形成。
複合晶圓102包含彼此相同的多個封裝體102'（參看圖26），其中封裝體102'中的每一者包含多個穿孔32及一或多個裝置晶粒36。圖26說明將封裝體104接合至封裝體102'上，由此形成疊層封裝（Package-on-Package；PoP）結構/封裝體126。接合經由焊料區100來執行。根據本揭露內容的一些實施例，封裝體104包含封裝基底106及（多個）裝置晶粒108，裝置晶粒可為諸如靜態隨機存取記憶體（Static Random Access Memory；SRAM）晶粒、動態隨機存取記憶體（Dynamic Random Access Memory；DRAM）晶粒或其類似者的記憶體晶粒。底部填充料128亦安置至封裝體104與下伏封裝體102'之間的間隙中，且經固化。
執行單體化（晶片鋸割）製程以將複合晶圓102分離為彼此相同的個別封裝體。圖26亦說明經單體化封裝體經由焊料區122接合至封裝組件120。根據本揭露內容的一些實施例，封裝組件120為封裝基底，其可為無芯基底或具有芯的基底。根據本揭露內容的其他實施例，封裝組件120為印刷電路板或封裝體。圖26中的封裝體在下文中被稱作封裝體126。
圖27說明根據替代實施例的封裝體126的形成。除不形成圖26中的穿孔32以外，圖27中所繪示的封裝體類似於圖26中所繪示的封裝體。封裝組件120由此接合至封裝體102'。
圖28至圖35說明根據本揭露內容的一些實施例的封裝體的形成中的中間階段的橫截面圖。除非另外規定，否則此等實施例中的組件的材料及形成方法基本上與類似組件相同，類似組件由圖1至26中所繪示的實施例中的類似圖式元件符號表示。關於圖28至圖35中所繪示的組件的形成製程及材料的細節因此可見於圖1至圖26中所繪示的實施例的論述中。
此等實施例的初始步驟基本上與圖1至圖5中所繪示的步驟相同。接下來，形成介電層130，且通孔開口132形成於介電層130中以暴露穿孔32及金屬柱42。介電層130可由選自用於形成介電層62（圖10）的相同候選材料群組的材料形成。
參看圖29，金屬晶種層134形成，且可包含黏著層134A及含銅層134B。黏著層134A及含銅層134B的組成物及形成方法可分別類似於黏著層50A及含銅層50B（圖6）的組合物及形成方法，且因此在本文中不重複。接著形成經圖案化光阻136，其中開口138形成以暴露下伏晶種層134。接下來，如圖30中所繪示，執行鍍覆製程使得通孔140及金屬線142形成於金屬晶種層134上。通孔140及金屬線142在下文中組合地被稱作重佈線144。根據本揭露內容的一些實施例，通孔140及金屬線142可由銅或銅合金形成。
在後續步驟中，移除光阻136，且因此暴露金屬晶種層134的下伏部分。接著執行三步蝕刻製程。首先，在第一及第二蝕刻步驟中蝕刻金屬晶種層134的所暴露部分。蝕刻製程條件及對應化學品類似於參看圖7及圖8所論述的用於蝕刻金屬晶種層50的蝕刻製程條件及對應化學品。結果，形成底切割146，如圖31中所說明。通篇描述中，金屬線142及通孔140被視為包含下伏含銅晶種層134B（圖29）的剩餘部分作為其底部部分。
接下來，在等向性蝕刻製程中執行再蝕刻，且所得結構繪示於圖32中。可使用選自如參看圖8中繪示的製程所論述的用於蝕刻金屬晶種層50的相同化學品群組的化學品來執行再蝕刻。因此，本文中不重複製程細節。在再蝕刻之後，金屬線142的橫向尺寸減小，使得金屬線142的邊緣可與黏著層134A的各別邊緣齊平。若未實質上消除，則至少減小如圖31中所繪示的底切割146。
圖33說明介電層148、含金屬晶種層150A、通孔156以及金屬線158的形成。通孔156及金屬線158在下文中組合地被稱作RDL 160。形成製程可基本上與用於形成介電層130、黏著層134A、通孔140以及金屬線142的製程相同，且因此在本文中不論述細節。並且，通孔156及金屬線158包含下伏含銅晶種層的剩餘部分。
圖34說明介電層92、UBM 96、金屬柱98以及焊料區100的形成，由此形成複合晶圓102。在後續步驟中，自載體20卸下複合晶圓102。後續步驟類似於參看圖25及圖26所繪示及論述的步驟，且因此在本文中不論述細節。所得封裝體126繪示於圖35中。
藉由再蝕刻諸如含銅金屬線及通孔的含銅區，可消除或減小底切割且改良所得封裝體的可靠性。實驗結果指示當針對精細節距金屬線及通孔（例如，其中節距小於可介於約1 µm與約6 µm之間的臨限節距）形成底切割時，所得結構的可靠性受到不利影響。另一方面，當針對大節距金屬線及通孔（例如，其中節距大於臨限節距）形成底切割時，所得結構的可靠性不會受到不利影響。根據本揭露內容的一些實施例，可對樣品晶圓執行實驗以形成諸如RDL（包含金屬線及通孔）以及具有不同節距及寬度的金屬襯墊的導電特徵，且測試樣品導電特徵的可靠性。因此，可判定臨限節距，其中具有等於或大於臨限節距的節距的樣品導電特徵是可靠的且不會遭受變形及分層問題，且此等樣品導電特徵被視為具有大節距。具有小於臨限節距的節距的樣品導電特徵可能遭受變形及分層問題，且此等樣品導電特徵被視為具有精細節距。
根據本揭露內容的一些實施例，可對小節距RDL（導電特徵）執行再蝕刻以消除/減小底切割，但並不對大節距RDL執行再蝕刻以消除/減小底切割。藉由區分精細節距及大節距RDL的形成以及選擇性地對精細節距RDL執行再蝕刻，改良可靠性且不會不必要地增加製造成本，此是因為節省了對大節距RDL再蝕刻的額外成本。舉例而言，參考圖26中所繪示的結構，下部RDL層（諸如60、71、76以及84的金屬線及通孔，以及下伏黏著層）可具有小節距且因此可採用再蝕刻製程而形成，而上部層（諸如，金屬線/襯墊90及金屬柱98)可跳過再蝕刻製程而形成。結果，RDL（諸如，下部RDL層)及特徵中的一些可能不具有底切割，而一些其他RDL（諸如，上部RDL層及金屬柱98）可具有底切割。在例如參考圖35中所繪示的結構的一些其他例示性實施例中，下部RDL層（金屬線及通孔）（諸如，RDL 144）可具有小節距且因此可採用再蝕刻製程而形成，而上部層（諸如，RDL 160）可跳過再蝕刻製程而形成。結果，RDL（諸如，RDL 144)及特徵中的一些可能不具有底切割，而同一封裝體中的一些其他RDL（諸如，RDL 160及金屬柱98）可具有底切割。
此外，在封裝體的形成中，具有等於或大於臨限節距的節距的所有RDL及金屬襯墊可在不進行再蝕刻的情況下形成，且因此具有底切割。另一方面，可使用三步蝕刻形成具有小於臨限節距的節距的所有RDL及金屬襯墊。
圖36A、圖36B及圖37說明根據本揭露內容的一些實施例的RDL中的通孔及金屬線的可能剖面。在圖36A、圖36B及圖37中，黏著層172A表示圖26及圖35中所繪示的實施例中的金屬晶種層中的黏著層，且特徵174表示圖26及圖35中所繪示的實施例中的RDL中的金屬線及通孔。在用於減小底切割的再蝕刻中，由於特徵134的拐角區比平坦表面蝕刻更多，因此特徵174的拐角圓化。根據本揭露內容的一些實施例，圓化拐角的半徑R1可大於約0.05 µm，且取決於消除底切割的要求以及特徵174的尺寸，可在介於約0.05 µm與約1 µm的範圍內。另一方面，即使與特徵174在同一封裝體中，不執行再蝕刻的RDL具有較陡拐角。
並且，在圖36A、圖36B及圖37中，虛線用以表示黏著層172A可側向地延伸超出上覆特徵174的各別邊緣，其被稱作基腳剖面。此可由製程變化引起，使得一些特徵174比同一封裝體中的其他特徵174蝕刻更多。舉例而言，在同一晶片中，一些RDL可具有零底切割，而一些其他RDL可具有基腳剖面。
在上文所說明的例示性實施例中，根據本揭露內容的一些實施例論述一些例示性製程及特徵。亦可包含其他特徵及製程。舉例而言，可包含測試結構以輔助三維（three-dimensional；3D）封裝或3DIC裝置的驗證測試。測試結構可包含例如形成於重佈線層中或基底上的測試襯墊，其允許測試3D封裝或3DIC、使用探針及/或探針卡以及其類似者。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合併有對已知良好晶粒的中間驗證的測試方法使用，以提高良率及減小成本。
本揭露內容的實施例具有一些有利特徵。藉由執行三步蝕刻製程以形成RDL，消除或減小RDL中的底切割且改良RDL的可靠性。
根據本揭露內容的一些實施例，一種形成半導體結構的方法包含：將裝置包封於包封材料中；平坦化包封材料及裝置；以及在包封材料及裝置上方形成導電特徵。導電特徵的形成包含：沈積第一導電材料以形成第一晶種層；在第一晶種層上方沈積不同於第一導電材料的第二導電材料以形成第二晶種層；在第二晶種層上方鍍覆金屬區；對第二晶種層執行第一蝕刻；對第一晶種層執行第二蝕刻；以及在蝕刻第一晶種層之後，對第二晶種層及金屬區執行第三蝕刻。在實施例中，使用實質上不侵蝕第一晶種層的化學品執行第三蝕刻。在實施例中，第一晶種層包括鈦，且第二晶種層包括銅。在實施例中，第三蝕刻包括濕式蝕刻。在實施例中，藉由第二蝕刻產生底切割，且第三蝕刻消除底切割。在實施例中，所述方法包含形成多個樣品，其各自包括類似於導電特徵結構的結構，其中形成多個樣品包括使用不同的蝕刻製程條件蝕刻多個樣品；以及自不同的蝕刻製程條件選擇產生具有最小底切割的樣品的製程條件，其中形成導電特徵是使用所述製程條件執行。在實施例中，鍍覆金屬區包括：用以形成金屬線的第一鍍覆製程；以及用以形成在金屬線上方且接合至金屬線的通孔的第二鍍覆製程，其中通孔比金屬線窄，且在第三蝕刻期間，蝕刻金屬線及通孔兩者。
根據本揭露內容的一些實施例，一種形成半導體結構的方法包含：形成包括黏著層的金屬晶種層；在金屬晶種層上方形成多個含銅特徵；蝕刻金屬晶種層；其中金屬晶種層的剩餘部分被含銅特徵重疊且彼此實體上分離；以及對多個含銅特徵執行蝕刻，其中在蝕刻中，多個含銅特徵的橫向尺寸比金屬晶種層的剩餘部分中的黏著層的各別下伏部分減少更多。在實施例中，蝕刻金屬晶種層包括使用第一化學溶液執行的蝕刻步驟，且使用不同於第一化學溶液的第二化學溶液執行對多個含銅特徵的蝕刻。在實施例中，在蝕刻金屬晶種層之後執行對多個含銅特徵的蝕刻。在實施例中，在蝕刻金屬晶種層之後，在含銅特徵的邊緣部分之下產生底切割，且其中在對多個含銅特徵的蝕刻之後，底切割減小。在實施例中，藉由對多個含銅特徵的蝕刻消除底切割。在實施例中，黏著層由不同於含銅特徵的材料形成。在實施例中，在對多個含銅特徵的蝕刻期間，實質上未蝕刻黏著層。
根據本揭露內容的一些實施例，一種形成半導體結構的方法包含：沈積鈦晶種層；在鈦晶種層上方沈積銅晶種層；在銅晶種層上方形成第一經圖案化罩幕，其中第一開口形成於第一經圖案化罩幕中；在第一開口中鍍覆金屬線；移除第一經圖案化罩幕；在金屬線及銅晶種層上方形成第二經圖案化罩幕以暴露金屬線的一部分，其中第二開口形成於第二經圖案化罩幕中；在金屬線上方及在第二開口中鍍覆通孔；移除第二經圖案化罩幕；對銅晶種層執行第一蝕刻直至銅晶種層的未由金屬線覆蓋的所暴露部分被移除且鈦晶種層的一部分被暴露；對鈦晶種層執行第二蝕刻以移除鈦晶種層的部分，其中鈦晶種層比金屬線側向地凹進以形成底切割；以及對金屬線及銅晶種層執行第三蝕刻以至少減小底切割。在實施例中，藉由第三蝕刻消除底切割。在實施例中，在第三蝕刻中，蝕刻金屬線及通孔兩者。在實施例中，第三蝕刻為等向性蝕刻。在實施例中，第三蝕刻包括濕式蝕刻。在實施例中，在第三蝕刻中，實質上未蝕刻鈦晶種層。
前文概述若干實施例的特徵，使得熟習此項技術者可更佳地理解本揭露內容的態樣。熟習此項技術者應瞭解，其可易於使用本揭露內容作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。熟習此項技術者亦應認識到，此類等效構造並不脫離本揭露內容的精神及範疇，且其可在不脫離本揭露內容的精神及範疇的情況下在本文中進行各種改變、替代以及更改。
20‧‧‧載體
22‧‧‧離型膜
24‧‧‧介電緩衝層
26、50、64、134‧‧‧金屬晶種層
28、52、66、72、136‧‧‧光阻
30、54、68、74、94、138‧‧‧開口
32‧‧‧金屬支柱/穿孔
34‧‧‧晶粒貼合膜
36‧‧‧裝置/裝置晶粒
40‧‧‧金屬襯墊
42‧‧‧金屬柱
43‧‧‧保護層
44‧‧‧聚合物層
48‧‧‧包封材料
48A‧‧‧基質材料
48B‧‧‧填充劑粒子
50A、64A、80A、88A、134A、172A‧‧‧黏著層
50B、64B、134B‧‧‧含銅層
56、60、76、84、140、156‧‧‧通孔
58、77、146‧‧‧底切割
62、78、86、92、130、148‧‧‧介電層
70、71、82、142、158‧‧‧金屬線
90‧‧‧金屬線/襯墊
96‧‧‧凸塊下金屬
98‧‧‧電連接件/金屬柱
100‧‧‧焊蓋/焊料區
102‧‧‧封裝體/複合晶圓
102'、104、126‧‧‧封裝體
106‧‧‧封裝基底
108‧‧‧裝置晶粒
120‧‧‧封裝組件
122‧‧‧焊料區
128‧‧‧底部填充料
132‧‧‧通孔開口
134‧‧‧金屬晶種層
144、160‧‧‧重佈線（RDL）
150A‧‧‧含金屬晶種層
174‧‧‧特徵
200‧‧‧製程流程
202、204、206、208、210、212、214、216、218、220、222、224、226、228、230、232、234、236、238、240‧‧‧步驟
R1‧‧‧半徑
W1、W2‧‧‧寬度
當結合附圖閱讀時，自以下實施方式最佳地理解本揭露內容的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，可出於論述清楚起見而任意地增大或減小各種特徵的尺寸。 圖1至圖26說明根據一些實施例的封裝體的形成中的中間階段的橫截面圖。 圖27說明根據一些實施例的不具有穿孔的封裝體的橫截面圖。 圖28至圖35說明根據一些實施例的封裝體的形成中的中間階段的橫截面圖。 圖36A、圖36B以及圖37說明根據一些實施例的一些RDL的剖面。 圖38說明用於形成根據一些實施例的封裝體的製程流程。

Claims (20)

  1. 一種形成半導體結構的方法，包括： 將裝置包封於包封材料中； 平坦化所述包封材料及所述裝置；以及 在所述包封材料及所述裝置上方形成導電特徵，其中所述形成所述導電特徵包括： 沈積第一導電材料以形成第一晶種層； 在所述第一晶種層上方沈積不同於所述第一導電材料的第二導電材料以形成第二晶種層； 在所述第二晶種層上方鍍覆金屬區； 對所述第二晶種層執行第一蝕刻； 對所述第一晶種層執行第二蝕刻；以及 在蝕刻所述第一晶種層之後，對所述第二晶種層及所述金屬區執行第三蝕刻。
  2. 如申請專利範圍第1項所述的方法，其中所述第一晶種層包括鈦、鉭、氮化鈦或氮化鉭，且所述第二晶種層及所述金屬區各自包括銅。
  3. 如申請專利範圍第1項所述的方法，其中所述第三蝕刻包括濕式蝕刻。
  4. 如申請專利範圍第1項所述的方法，其中藉由所述第二蝕刻產生底切割，且所述第三蝕刻消除所述底切割。
  5. 如申請專利範圍第1項所述的方法，其中在同一層級處的所述導電特徵及相鄰導電特徵具有節距，且其中所述對所述第二晶種層及所述金屬區執行所述第三蝕刻包括在所述節距小於約4 μm時對所述第二晶種層及所述金屬區執行所述第三蝕刻。
  6. 如申請專利範圍第1項所述的方法，其中所述鍍覆所述金屬區包括： 用以形成金屬線的第一鍍覆製程；以及 用以形成在所述金屬線上方且接合至所述金屬線的通孔的第二鍍覆製程，其中所述通孔比所述金屬線窄，且在所述第三蝕刻期間，蝕刻所述金屬線及所述通孔兩者。
  7. 如申請專利範圍第1項所述的方法，其中所述第一蝕刻及所述第二蝕刻是個別的蝕刻步驟。
  8. 一種形成半導體結構的方法，包括： 形成黏著層； 在所述黏著層上方形成多個含銅特徵； 選擇性地蝕刻所述黏著層，藉此移除所述黏著層的不在所述多個含銅特徵之下的部分且側向地底切所述黏著層的在所述多個含銅特徵下方的部分以形成底切割；以及 選擇性地蝕刻所述多個含銅特徵以減小所述底切割。
  9. 如申請專利範圍第8項所述的方法，其中所述蝕刻所述黏著層包括使用第一化學溶液執行的蝕刻步驟，且對所述多個含銅特徵的所述蝕刻是使用不同於所述第一化學溶液的第二化學溶液執行。
  10. 如申請專利範圍第9項所述的方法，其中在所述選擇性地蝕刻所述多個含銅特徵之後，所述多個含銅特徵以及下伏黏著層的下伏剩餘部分形成通孔。
  11. 如申請專利範圍第8項所述的方法，其中使用選自實質上由以下各者組成的群組的化學品來執行所述選擇性地蝕刻所述多個含銅特徵：H3 PO4 、H2 O2 以及H2 O的混合物；H2 SO4 、H2 O2 以及H2 O的混合物；(NH4 )2 S2 O8 及H2 O的混合物；HCl溶液；HCl及CuCl2 的混合物；FeCl3 溶液；以及其組合。
  12. 如申請專利範圍第11項所述的方法，其中藉由對所述多個含銅特徵的所述蝕刻消除所述底切割。
  13. 如申請專利範圍第8項所述的方法，其中所述黏著層由不同於所述含銅特徵的材料形成。
  14. 如申請專利範圍第8項所述的方法，其中使用酸性化學品蝕刻所述黏著層，且使用鹼性化學品蝕刻所述多個含銅特徵。
  15. 一種半導體結構，包括： 裝置晶粒； 包封體，將所述裝置晶粒包封於其中； 第一多個重佈線（RDL），上覆於且電耦接至所述裝置晶粒，其中所述第一多個重佈線具有第一節距，且所述第一多個重佈線實質上無底切割；以及 第二多個重佈線，上覆於且電耦接至所述裝置晶粒，其中所述第二多個重佈線具有大於所述第一節距的第二節距，且所述第二多個重佈線具有底切割。
  16. 如申請專利範圍第15項所述的半導體結構，其中所述第二多個重佈線在所述第一多個重佈線上方。
  17. 如申請專利範圍第15項所述的半導體結構，其中與所述第一多個重佈線在同一層級處的所有重佈線實質上無底切割，且與所述第二多個重佈線在同一層級處的所有重佈線具有底切割。
  18. 如申請專利範圍第15項所述的半導體結構，其中在所述第一多個重佈線之下且在所述裝置晶粒上方的層級處的所有重佈線實質上無底切割，且在高於所述第二多個重佈線的層級處的所有重佈線具有底切割。
  19. 如申請專利範圍第15項所述的半導體結構，其中上覆於所述裝置晶粒且具有等於或大於臨限節距的節距的所有重佈線具有底切割，且上覆於所述裝置晶粒且具有小於所述臨限節距的節距的所有重佈線實質上無底切割。
  20. 如申請專利範圍第15項所述的半導體結構，其中所述第二多個重佈線包括： 黏著層；以及 含銅區，上覆於所述黏著層中的各別者，其中所述底切割被所述含銅區重疊且與所述黏著層在同一層級處。
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