TWI646609B - 三層封裝上封裝結構及其製造方法 - Google Patents

三層封裝上封裝結構及其製造方法 Download PDF

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TWI646609B
TWI646609B TW106107437A TW106107437A TWI646609B TW I646609 B TWI646609 B TW I646609B TW 106107437 A TW106107437 A TW 106107437A TW 106107437 A TW106107437 A TW 106107437A TW I646609 B TWI646609 B TW I646609B
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Taiwan
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device die
metal pillar
metal
encapsulating material
dielectric layer
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TW106107437A
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TW201806047A (zh
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洪瑞斌
許峰誠
鄭心圃
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台灣積體電路製造股份有限公司
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Abstract

一種方法包含形成第一複數個重佈線，形成第一金屬柱於該第一複數個重佈線上方並且電連接至該第一複數個重佈線，以及接合第一裝置晶粒至該第一複數個重佈線。該第一金屬柱與該第一裝置晶粒被囊封於第一囊封材料中。而後，平坦化該第一囊封材料。該方法另包含形成第二金屬柱於該第一金屬柱上方並且電連接至該第一金屬柱，經由黏著膜而附接第二裝置晶粒至該第一囊封材料，囊封該第二金屬柱與該第二裝置晶粒於第二囊封材料中，平坦化該第二囊封材料，以及形成第二複數個重佈線於該第二金屬柱與該第二裝置晶粒上方並且電耦合至該第二金屬柱與該第二裝置晶粒。

Description

三層封裝上封裝結構及其製造方法
本揭露係關於三層封裝上封裝結構及其製造方法。
現代電路製造通常涉及一些步驟。先於半導體晶圓上，製造多個積體電路，該半導體晶圓含有多個複製半導體晶片，各自含有多個積體電路。而後，將該半導體基晶片自該晶圓切割且封裝。封裝製程有兩個主要目的：保護半導體晶片以及連接內部積體電路至外部接腳。 隨著越來越需要更多功能，發展封裝上封裝(package-on-package，PoP)技術，接合二或多個封裝以擴張封裝的整合能力。藉由高程度整合，受益於組件之間的連接路徑縮短，可改良所得到的PoP封裝的電性效能。藉由使用PoP技術，封裝設計變得更能變通且較不複雜。亦縮短上市時間。
本揭露的一些實施例提供一種方法，包括形成一第一複數個重佈線；形成一第一金屬柱於該第一複數個重佈線上方並且電耦合至該第一複數個重佈線；經由覆晶接合而接合一第一裝置晶粒至該第一複數個重佈線；囊封該第一金屬柱與該第一裝置晶粒於一第一囊封材料中；平坦化該第一囊封材料，直到暴露該第一金屬柱；形成一第二金屬柱於該第一金屬柱上方，並且電連接該第二金屬柱至該第一金屬柱；經由一黏著膜，附接一第二裝置晶粒至該第一囊封材料；囊封該第二金屬柱與該第二裝置晶粒於一第二囊封材料中；平坦化該第二囊封材料，直到暴露該第二裝置晶粒的一表面上的該第二金屬柱與多個金屬特徵；以及形成一第二複數個重佈線於該第二金屬柱與該第二裝置晶粒上方，並且電耦合該第二複數個重佈線至該第二金屬柱與該第二裝置晶粒。 本揭露的一些實施例提供一種方法，包括囊封一第一裝置晶粒與一第一金屬柱於一第一囊封材料；平坦化該第一囊封材料，以暴露該第一金屬柱，其中該第一囊封材料的一層被留下直接位於該第一裝置晶粒上方；形成一圖案化遮罩層於該第一囊封材料上方，經由該圖案化遮罩層中的一開口，暴露該第一金屬柱的一中心部分；鍍一第二金屬柱於該開口中；移除該圖案化遮罩層；經由一黏著膜而附接一第二裝置晶粒至該第一囊封材料；囊封該第二裝置晶粒與該第二金屬柱於一第二囊封材料中；以及形成一第二複數個重佈線於該第二裝置晶粒的該第二金屬柱與多個金屬桿上方，並且電耦合該第二複數個重佈線至該第二裝置晶粒的該第二金屬柱與該等金屬桿。 本揭露的一些實施例提供一種封裝，包括一第一複數個重佈線；一第一囊封材料；一第一金屬柱，穿過該第一囊封材料，其中該第一金屬柱電耦合至該第一複數個重佈線；一第一裝置晶粒，被囊封於該第一囊封材料中，其中該第一裝置晶粒經由覆晶接合而接合至該第一複數個重佈線；一第二裝置晶粒，位於該第一囊封材料上方並且經由一黏著膜而附接至該第一囊封材料；一第二囊封材料，囊封該第二裝置晶粒於其中；一第二金屬柱，穿過該第二囊封材料並且電連接至該第一金屬柱；以及一第二複數個重佈線，位於該第二裝置晶粒與該第二金屬柱上方並且電耦合至該第二裝置晶粒與該第二金屬柱。
本揭露提供了數個不同的實施方法或實施例，可用於實現本發明的不同特徵。為簡化說明起見，本揭露也同時描述了特定零組件與佈置的範例。請注意提供這些特定範例的目的僅在於示範，而非予以任何限制。舉例而言，在以下說明第一特徵如何在第二特徵上或上方的敘述中，可能會包括某些實施例，其中第一特徵與第二特徵為直接接觸，而敘述中也可能包括其他不同實施例，其中第一特徵與第二特徵中間另有其他特徵，以致於第一特徵與第二特徵並不直接接觸。此外，本揭露中的各種範例可能使用重複的參考數字和/或文字註記，以使文件更加簡單化和明確，這些重複的參考數字與註記不代表不同的實施例與/或配置之間的關聯性。 另外，本揭露在使用與空間相關的敘述詞彙，如“在...之下”，“低”，“下”，“上方”，“之上”，“下”，“頂”，“底”和類似詞彙時，為便於敘述，其用法均在於描述圖示中一個元件或特徵與另一個（或多個）元件或特徵的相對關係。除了圖示中所顯示的角度方向外，這些空間相對詞彙也用來描述該裝置在使用中以及操作時的可能角度和方向。該裝置的角度方向可能不同（旋轉90度或其它方位），而在本揭露所使用的這些空間相關敘述可以同樣方式加以解釋。 根據各種例示實施例，提供扇出封裝上封裝(PoP)結構/封裝及該封裝的製造方法。討論該等實施例的變異。在不同的圖式與說明之實施例中，相同的元件符號用以代表相同的元件。 圖1至圖21係根據一些實施例說明形成封裝的中間階段之剖面圖。圖1至21所示之步驟亦概示說明於圖23所示之製程流程200中。 圖1說明載體20以及形成於載體20上的釋放層(release layer)22。載體20可為玻璃載體、陶瓷載體、或類似物。載體20可具有圓形俯視形狀，並且可具有矽晶圓的俯視形狀與尺寸。例如，載體20可具有8吋直徑、12吋直徑或類似者。釋放層22可由聚合物基底材料(例如光熱轉換(Light to Heat Conversion，LTHC)材料)形成，可自後續步驟將形成的上方結構，沿著載體20而被移除。根據本揭露的一些實施例，由環氧化合物為基底的熱釋放材料形成釋放層22。根據其他的實施例，由紫外光(UV)膠形成釋放層22。釋放層22可分配為液體且被硬化。根據其他的實施例，釋放層22為壓層至載體20上的壓層膜。釋放層22的頂表面平整，並且具有高程度的共平面性。 介電層24形成於釋放層22上。根據本揭露的一些實施例，介電層24由聚合物形成，其亦可為光敏材料，例如聚苯并噁唑(polybenzoxazole，PBO)、聚亞醯胺、苯并環丁烯(benzocyclobutene，BCB)、或類似物，其可經由曝光與顯影而輕易被圖案化。根據其他的實施例，介電層24是由無機材料形成，例如氮化物，例如氮化矽、氧化物，例如氧化矽、磷矽酸鹽玻璃(PhosphoSilicate Glass，PSG)、硼矽酸鹽玻璃(BoroSilicate Glass，BSG)、摻硼的磷矽酸鹽玻璃(Boron-doped PhosphoSilicate Glass，BPSG)、或類似物。 圖2至4係說明重佈線(Redistribution Line，RDL)的形成。個別步驟係如圖23所示之製程流程的步驟201所示。參閱圖2，介電層26形成於介電層24上方。介電層26可選自於與形成介電層24相同的候選材料群組。再者，形成介電層26的材料可與介電層24的材料不同或相同。將介電層26圖案化以形成開口28，經由該開口28暴露下方的介電層24。 接著，參閱圖3，於介電層26上方，形成晶種層30。晶種層30的多個部分進一步延伸至多個開口28中。根據一些實施例，晶種層30包含鈦層以及位於鈦層上方的銅層。根據其他的實施例，晶種層30包含單一銅層或是單一銅合金層。例如，使用物理氣相沉積(Physical Vapor Deposition，PVD)形成晶種層30。於晶種層30上方形成圖案化遮罩32，其可為光阻，而後圖案化以暴露晶種層30。多個開口28亦暴露至圖案化遮罩32中的該等開口。 參閱圖4，形成RDL 34。形成製程包含在暴露的晶種層30上進行鍍金屬。而後，移除圖案化遮罩32(圖3)。例如，使用無電鍍進行該鍍製程。而後，在蝕刻步驟中，移除先前受到圖案化遮罩32所覆蓋的晶種層30之多個部分，留下圖4所示之RDL 34。 參閱圖5，形成介電層36，而後圖案化介電層36。個別步驟係如圖23所示之製程流程中所示的步驟204。可由或可不由形成介電層24與/或26的相同候選材料群組所選擇的材料形成介電層36，並且介電層36可由聚合物或無機材料形成。而後，圖案化介電層36，並且暴露RDL 34的一些部分。 圖6說明晶種層40與上方圖案化遮罩42之形成。晶種層40與圖案化遮罩42之材料與形成製程類似於晶種層30與圖案化遮罩32，此處不再重述。 而後，進行鍍製程，形成RDL 44，如圖7所示。個別步驟係如圖23所示之製程流程中的步驟206所示。而後，移除圖6所示之圖案化遮罩42。根據一些實施例，所得之RDL 44的頂表面高於介電層36的頂表面。根據一些例示實施例，在介電層36之頂表面上方的RDL 44之該等部分的高度H1係於約20微米至約30微米之間的範圍中。在移除圖案化遮罩42之後，受到所移除之圖案化遮罩42覆蓋的晶種層40之該等部分係被暴露。晶種層40的這 些部分未被移除，並且用於後續之金屬柱(metal post)的形成。 參閱圖8，形成且圖案化圖案化遮罩46，其可由光阻形成，並且於該圖案化遮罩46中形成多個開口48。晶種層40的一些部分以及一些RDL 44被暴露。而後，進行鍍步驟以形成金屬柱50，如圖9所示。個別步驟係如圖23所示之製程流程中的步驟208所示。在該鍍製程之後，移除圖案化遮罩46，而後移除先前受到圖案化遮罩46覆蓋的晶種層40之該等部分。所得到的結構係如圖9所示。可理解雖然一些金屬柱50繪示為分離的，但這些金屬柱實際上連接至RDL 44的一些部分，該等部分未在所繪示的平面中。在本揭露的說明中，晶種層40的剩餘部分被解讀為對應之RDL 44與金屬柱50的部分。 在先前的製程步驟中，使用相同的晶種層40進行兩個鍍製程，使用不同的遮罩進行該兩個鍍製程。第一鍍製程如圖6至圖7所示，以及第二鍍製程如圖8至圖9所示。兩個鍍製程共用相同的晶種層有利地節省製造成本。 圖10至20說明形成PoP封裝的後續步驟。在接續的圖式中，概示說明介電層26與36以及RDL 34與44的細節，而這些特徵細節可參閱圖1至9。 圖10說明裝置晶粒52與被動裝置54的設置。個別步驟係如圖23所示之製程流程中的步驟210所示。根據本揭露的一些實施例，裝置晶粒52為記憶體晶粒，例如動態隨機存取記憶體(DRAM)晶粒。根據其他的實施例，裝置晶粒52為邏輯晶粒，例如應用處理器(Application processor，AP)晶粒。被動裝置54可包含例如電容器、電阻器、電感器、或類似物。當裝置晶粒52為DRAM晶粒時，被動裝置54可包含電容器，用於穩定裝置晶粒52的電源供應電壓。裝置晶粒52與被動裝置54包含多個焊料區56與RDL 44接觸。 接著，如圖11所示，進行回焊製程，回焊該等焊料區56，將裝置晶粒52與被動裝置54接合至RDL 44。而後，將裝置晶粒52、被動裝置54以及金屬柱50囊封於囊封材料58中，如圖12所示。個別步驟係如圖23所示之製程流程中的步驟212所示。囊封材料58可為模塑料，因而在本揭露的說明中稱為模塑料58。模塑料58亦可為成形底膠填充(molding underfill)、環氧化合物、以及/或樹脂。模塑料58填充相鄰金屬柱50之間的間隙以及金屬柱50與裝置晶粒52之間的間隙。模塑料58的頂表面高於金屬柱50的頂表面。 接著，進行平坦化步驟，例如化學機械拋光(Chemical Mechanical Polish，CMP)或機械研磨製程，薄化模塑料58，直到暴露金屬柱50。所得到的結構係如圖12所示。由於研磨，金屬柱50的頂端與模塑料58的頂表面實質齊平(共平面)。根據一些實施例，在完成平坦化之後，留下模塑料58的薄層，覆蓋裝置晶粒52。根據其他的實施例，在平坦化之後，暴露裝置晶粒52的背面，其中所示虛線59係根據這些實施例說明所得之模塑料58的頂表面。 圖13說明於該等金屬柱50的頂部上形成多個金屬柱60。個別步驟係如圖23所示之製程流程中的步驟214所示。形成製程可包含形成遮罩61，例如光阻，以及暴露且顯影/蝕刻該遮罩以形成多個開口，其中該等金屬柱50的多個中心部分係暴露於圖案化遮罩61中的該等開口。該等開口的俯視尺寸小於該等金屬柱50的俯視尺寸。據此，金屬柱50可作為晶種層用於鍍金屬柱60。而後，移除圖案化遮罩61。在所得到的結構中，金屬柱50橫向延伸超出個別上方金屬柱60的邊緣，金屬柱50的橫向尺寸以陡峭的方式轉至金屬柱60的橫向尺寸。金屬柱60可由均質材料形成，例如銅或銅合金。 圖14說明附接多個裝置晶粒62，其中該等裝置晶粒62的背面面對該等裝置晶粒52的背面。個別步驟係如圖23所示之製程流程中的步驟216所示。裝置晶粒62可經由晶粒附接膜64而黏附至模塑料58與/或該等裝置晶粒52的背面。晶粒附接膜64的邊緣與該等裝置晶粒62的個別邊緣對齊(垂直對準)。晶粒附接膜64為黏著膜，在附接至模塑料58之前，黏著至該等裝置晶粒62。該等裝置晶粒62可包含多個半導體基板，該等半導體基板具有背面(該表面朝下)實體接觸該等晶粒附接膜64。該等裝置晶粒62另包含多個積體電路裝置(例如主動裝置，其包含例如電晶體，未繪示)於該等半導體基板的正面。根據一些例示實施例，裝置晶粒62為應用處理器晶粒，該應用處理器晶粒為邏輯晶粒，例如中央處理單元(CPU)晶粒、圖形處理單元(GPU)晶粒、行動應用晶粒、或類似物。再者，重疊於相同裝置晶粒52的每一對裝置晶粒62可包含數位晶粒與類比晶粒。 裝置晶粒62可包含金屬桿(metal pillar)66於其頂表面。金屬桿66電耦合至裝置晶粒62內部的積體電路。金屬桿66可為銅桿，並且亦可包含其他傳導/金屬材料，例如鋁、鎳、或類似物。根據本揭露的一些例示實施例，如圖14所示，金屬桿66位於介電層68中，以及金屬桿66的頂表面與介電層68的頂表面為共平面。根據本揭露的其他實施例，金屬桿66嵌埋於介電層68中，個別介電層68的頂表面高於金屬桿66的頂表面。介電層68可由聚合物形成，該聚合物可包含PBO、聚亞醯胺、或類似物。 參閱圖15，於該等裝置晶粒62與金屬柱60上，囊封/塑形囊封材料70。個別步驟係如圖23所示之製程流程中的步驟218所示。囊封材料70可包含模塑料、成形底膠填充、環氧化合物、與/或樹脂。在成形製程之後，囊封材料70的頂表面高於金屬桿66與金屬柱60的頂端。接著，進行平坦化步驟，例如CMP步驟，或是機械研磨步驟，以平坦化囊封材料70，直到暴露金屬柱60與金屬桿66。由於平坦化，該等金屬柱60的頂表面與該等金屬柱66的頂表面實質齊平(共平面)，並且與囊封材料70的頂表面實質齊平(共平面)。 參閱圖16，於囊封材料70、金屬柱60以及金屬桿66上方，形成一或多層的介電層72與個別的RDL 74。個別步驟係如圖23所示之製程流程中的步驟220所示。根據本揭露的一些實施例，介電層72係由聚合物形成，例如PBO、聚亞醯胺、或類似物。根據本揭露的其他實施例，介電層72係由無機介電材料形成，例如氮化矽、氧化矽、氮氧化矽、或類似物。 形成RDL 74以電耦合至金屬桿66與金屬柱60。RDL 74亦可使金屬桿66與金屬柱60彼此互連。RDL 74可包含多個金屬跡線(金屬線)與多個通路，該等通路位於該等金屬跡線下方且連接至該等金屬跡線。根據本揭露的一些實施例，經由鍍製程，形成RDL 74，其中各個RDL 74包含晶種層(未繪示)以及位於該晶種層上方的被鍍金屬材料。該晶種層與該被鍍金屬材料可由相同材料或不同材料形成。 圖17係根據本揭露的一些實施例說明多個電連接器76的形成。個別步驟係圖如23所示之製程流程的步驟220所示。該等電連接器76係電耦合至該等RDL 74、金屬桿66、與/或金屬柱60。電連接器76的形成可包含放置多個焊球於該等RDL 74上方，而後回焊該等焊球。根據本揭露的其他實施例，電連接器76的形成包含進行鍍步驟，以於該等RDL 74上方形成焊料區，而後回焊該焊料區。該等電連接器76亦可包含多個金屬桿、或多個金屬桿與多個焊料蓋(solder cap)，焊料蓋亦可經由鍍製程而形成。在本揭露的說明中，包含該等裝置晶粒62、金屬柱60、囊封材料70、RDL 74、以及介電層72的組合結構稱為封裝80，其可為複合晶圓。 被動裝置75亦接合至RDL 74。被動裝置78可包含電容器、電阻器、電感器、或類似物，並且可為分離的裝置，其中未形成主動裝置，例如電晶體與二極體。 接著，封裝80自載體20脫離。根據一些例示的脫離製程(de-bonding process)，切割帶82(圖18)附接至封裝80，以保護電連接器76，其中切割帶82係固定至切割架(dicing frame)83。例如，藉由投射UV光或雷射於釋放層22(圖17)上，進行脫離。例如，當釋放層由LTHC形成時，由光或雷射產生的熱造成LTHC分解，因而載體20自封裝80脫離。所得到的結構如圖18所示。 圖19說明於介電層24中圖案化形成開口84。個別步驟係如圖23所示之製程流程中的步驟22所示。例如，可使用雷射鑽孔，圖案化介電層24，以移除多個部分，該等部分重疊於RDL 74中的一些金屬墊，因而經由多個開口84暴露該等金屬墊。 圖20說明接合封裝86至封裝80，因而形成PoP封裝。個別步驟係如圖23所示之製程流程中的步驟224所示。封裝86與80亦分別稱為PoP封裝的頂部封裝與底部封裝。經由焊料區88，進行該接合，將RDL 44接合至上方封裝86中的該等金屬墊。根據本揭露的一些實施例，封裝86包含裝置晶粒90，其可為記憶體晶粒，例如快閃記憶體晶粒、靜態隨機存取記憶體(SRAM)晶粒、動態隨機存取記憶體(DRAM)晶粒、或類似物。根據一些例示實施例，記憶體晶粒亦可接合至封裝基板92。 在頂部封裝86接合至底部封裝80之後，配置底膠填充94於頂部封裝86與底部封裝80之間的間隙中。在後續的步驟中，圖20所示的封裝被切割分為複數個封裝。所得之多個封裝90的其中之一係如圖21所示。個別步驟係如圖23所示的製程流程中的步驟224所示。 在圖20與21所示的封裝中，裝置晶粒52與裝置晶粒62係背對背放置。根據一些實施例，有一囊封材料層58，將裝置晶粒52與個別裝置晶粒62分隔。當裝置晶粒62為應用處理器晶粒時，在操作期間，其溫度通常很高，有時高達110°C。另一方面，記憶體晶粒，例如裝置晶粒52，無法承受如此高溫，並且可能受到裝置晶粒62散熱破壞。有利的是，囊封材料層58可作為熱絕緣層，用以減少裝置晶粒62至裝置晶粒52的散熱量。根據一些實施例，例如，當晶粒52與62的散熱不會顯著影響彼此時，DAF 64直接接觸裝置晶粒52的背面。 不論囊封材料58與70彼此相同或是彼此不同，囊封材料58與70之間的介面係可區分的。例如，圖22說明封裝96中的區98(圖21)之放大圖。可理解囊封材料58與70各自可包含基底材料，其可為聚合物、樹脂、環氧化合物、或類似物，以及在該基底材料中的填充物顆粒。該填充物顆粒可為SiO2 、Al2 O3 或類似物的介電質顆粒。例如，囊封材料58可包含基底材料104A與填充物顆粒102A，以及囊封材料70可包含基底材料104B與填充物顆粒102B。填充物顆粒102A與102B可具有圓形表面，其可為球形。由於圖12所示的平坦化，顆粒102A亦被研磨而具有平坦表面。據此，研磨的顆粒120A可包含球形表面於基底材料104A內部，以及具有平坦表面接觸DAF 64與囊封材料70。另一方面，囊封材料70面對囊封材料58之側未被平坦化。據此，與囊封材料58實體接觸的顆粒102B未被研磨，因而將以其圓形/球形表面接觸囊封材料58。因此，研磨的填充物顆粒可用以判定囊封材料58與70何者已經被研磨，以及何處為研磨的表面。此外，囊封材料58與70亦可由不同材料形成，因而可經由其材料的差異而判定它們的介面。同樣地，囊封材料70(參閱圖15)的研磨表面可具有類似特性，並且該研磨表面可被區分。 本揭露的實施例具有一些優點特徵。雖然PoP封裝總共有三層，然而僅兩個囊封材料層用於囊封。由於囊封材料具有不同的熱膨脹係數(Coefficients of Thermal Expansion，CTE)，因而使用越多囊封材料層，所得之封裝將具有更多的翹曲(warpage)。據此，藉由使用兩個囊封材料層囊封兩層(而非三層)裝置晶粒，顯著減少封裝80的翹曲(圖19)。第三層裝置晶粒經由焊料接合而接合至底部封裝。再者，在完成封裝80之後，進行該接合，因而不會對於所得之封裝形成顯著翹曲。 此外，在最終步驟中，裝置晶粒90(圖20與21)被整合於PoP封裝中，因而裝置晶粒90不會受到進行的封裝製程中的熱預算(thermal budget)。例如，可在高於約200°C的溫度(例如約230°C)，進行聚合物層的硬化與囊封材料的硬化，該溫度可能破壞快閃記憶體。因此，快閃記憶體晶粒90可被併入封裝86，以避免熱預算，因而改良封裝產率。 根據本揭露的一些實施例，方法包含形成第一複數個重佈線，形成第一金屬柱於該第一複數個重佈線上並且電連接至該第一複數個重佈線，以及經由覆晶接合，將一第一裝置晶粒接合至該第一複數個重佈線。該第一金屬柱與該第一裝置晶粒囊封於第一囊封材料中。將第一囊封材料平坦化，直到暴露該第一金屬柱。該方法另包含形成一第二金屬柱於該第一金屬柱上方並且連接至該第一金屬柱，經由一黏著膜而附接一第二裝置晶粒至該第一囊封材料，囊封該第二金屬柱與該第二裝置晶粒於第二囊封材料中，平坦化該第二囊封材料，直到暴露該第二裝置晶粒的表面上之該第二金屬柱與金屬特徵，以及形成第二複數個重佈線於該第二金屬柱與該第二裝置晶粒上方並且電耦合至該第二金屬柱與該第二裝置晶粒。 根據本揭露的一些實施例，方法包含囊封一第一裝置晶粒與一第一金屬柱於第一囊封材料中，以及平坦化該第一囊封材料以暴露該第一金屬柱。留下第一囊封材料層以直接位於該第一裝置晶粒上方。形成一圖案化遮罩層於該第一囊封材料上方，經由該圖案化遮罩層中的一開口而暴露該第一金屬柱的一中心部分。於該開口中，鍍第二金屬柱。而後，移除該圖案化遮罩層。該方法另包含晶由一黏著膜而覆接一第二裝置晶粒至該第一囊封材料，囊封該第二裝置晶粒與該第二金屬柱於第二囊封材料中，以及形成第二複數個重佈線於該第二裝置晶粒的第二金屬柱與金屬桿上方並且電耦合至該第二裝置晶粒的第二金屬柱與金屬桿。 根據本揭露的一些實施例，封裝包含第一複數個重佈線、第一囊封材料、以及穿過該第一囊封材料的第一金屬柱。該第一金屬柱電耦合至第一複數個重佈線。第一裝置晶粒囊封於該第一囊封材料中。該第一裝置晶粒經由覆晶接合而接合至該第一複數個重佈線。該封裝另包含位於該第一囊封材料上方且經由一黏著膜而附接至該第一囊封材料的一第二裝置晶粒，第二囊封材料囊封該第二裝置晶粒於其中，一第二金屬柱穿過該第二囊封材料且連接至該第一金屬柱，以及第二複數個重佈線位於該第二裝置晶粒與該第二金屬柱上方並且電耦合至該第二裝置晶粒與該第二金屬柱。 前述內容概述一些實施方式的特徵，因而熟知此技藝之人士可更加理解本揭露之各方面。熟知此技藝之人士應理解可輕易使用本揭露作為基礎，用於設計或修飾其他製程與結構而實現與本申請案所述之實施例具有相同目的與/或達到相同優點。熟知此技藝之人士亦應理解此均等架構並不脫離本揭露揭示內容的精神與範圍，並且熟知此技藝之人士可進行各種變化、取代與替換，而不脫離本揭露之精神與範圍。
20‧‧‧載體
22‧‧‧釋放層
24‧‧‧介電層
26‧‧‧介電層
28‧‧‧開口
30‧‧‧晶種層
32‧‧‧圖案化遮罩
34‧‧‧重佈線
36‧‧‧介電層
40‧‧‧晶種層
42‧‧‧圖案化遮罩
44‧‧‧重佈線
46‧‧‧圖案化遮罩
48‧‧‧開口
50‧‧‧金屬柱
52‧‧‧裝置晶粒
54‧‧‧被動裝置
56‧‧‧焊料區
58‧‧‧囊封材料
59‧‧‧虛線
60‧‧‧金屬柱
61‧‧‧遮罩
62‧‧‧裝置晶粒
64‧‧‧晶粒附接膜
66‧‧‧金屬桿
68‧‧‧介電層
70‧‧‧囊封材料
72‧‧‧介電層
74‧‧‧重佈線
76‧‧‧電連接器
78‧‧‧被動裝置
80‧‧‧封裝
82‧‧‧切割帶
83‧‧‧切割架
84‧‧‧開口
86‧‧‧封裝
88‧‧‧焊料區
90‧‧‧裝置晶粒
92‧‧‧裝置基板
94‧‧‧底膠填充
96‧‧‧封裝
98‧‧‧區
102A‧‧‧填充物顆粒
102B‧‧‧填充物顆粒
104A‧‧‧基底材料
104B‧‧‧基底材料
為協助讀者達到最佳理解效果，建議在閱讀本揭露時同時參考附件圖示及其詳細文字敘述說明。請注意為遵循業界標準作法，本專利說明書中的圖式不一定按照正確的比例繪製。在某些圖式中，尺寸可能刻意放大或縮小，以協助讀者清楚了解其中的討論內容。 圖1至圖21係根據一些實施例說明形成扇出封裝上封裝(PoP)之中間階段的剖面圖。 圖22係根據一些實施例說明封裝之一部分的剖面圖。 圖23係根據一些實施例說明形成PoP結構之製程流程圖。

Claims (10)

  1. 一種製造半導體封裝的方法，包括：形成一第一複數個重佈線；形成一第一金屬柱於該第一複數個重佈線上方並且電耦合至該第一複數個重佈線；經由覆晶接合而接合一第一裝置晶粒至該第一複數個重佈線；囊封該第一金屬柱與該第一裝置晶粒於一第一囊封材料中；平坦化該第一囊封材料，直到暴露該第一金屬柱；形成一第二金屬柱於該第一金屬柱上方，並且電連接該第二金屬柱至該第一金屬柱；經由一黏著膜，附接一第二裝置晶粒至該第一囊封材料；囊封該第二金屬柱與該第二裝置晶粒於一第二囊封材料中；平坦化該第二囊封材料，直到暴露該第二裝置晶粒的一表面上的該第二金屬柱與多個金屬特徵；以及形成一第二複數個重佈線於該第二金屬柱與該第二裝置晶粒上方，並且電耦合該第二複數個重佈線至該第二金屬柱與該第二裝置晶粒。
  2. 如申請專利範圍第1項所述之方法，其中該第一複數個重佈線形成於一第一介電層上方，以及該方法另包括：圖案化該第一介電層，以暴露該第一複數個重佈線的多個部分；以及接合一封裝至該第一複數個重佈線的該等部分。
  3. 如申請專利範圍第1項所述之方法，其中當第二裝置晶粒附接至該第一裝置晶粒時，一第一黏著膜包括一第一側與一第二側，該第一側接觸該第一裝置晶粒的一背面，以及該第二側接觸該第二裝置晶粒的一背面。
  4. 如申請專利範圍第1項所述之方法，其中在該第二裝置晶粒附接至該第一囊封材料之前，預先附接該黏著膜至該第二裝置晶粒。
  5. 如申請專利範圍第1項所述之方法，其中形成該第一複數個重佈線包括：形成一第二介電層於一第一介電層上方；圖案化該第二介電層，以暴露該第一介電層；以及形成該第一複數個重佈線的一第一層，該第一層包括多個第一部分與多個第二部分，該等第一部分延伸至該第二介電層中，以及該等第二部分位於該第二介電層上方。
  6. 一種製造半導體封裝的方法，包括：囊封一第一裝置晶粒與一第一金屬柱於一第一囊封材料；平坦化該第一囊封材料，以暴露該第一金屬柱，其中該第一囊封材料的一層被留下直接位於該第一裝置晶粒上方；形成一圖案化遮罩層於該第一囊封材料上方，經由該圖案化遮罩層中的一開口，暴露該第一金屬柱的一中心部分；鍍一第二金屬柱於該開口中；移除該圖案化遮罩層；經由一黏著膜而附接一第二裝置晶粒至該第一囊封材料；囊封該第二裝置晶粒與該第二金屬柱於一第二囊封材料中；以及形成一第二複數個重佈線於該第二裝置晶粒的該第二金屬柱與多個金屬桿上方，並且電耦合該第二複數個重佈線至該第二裝置晶粒的該第二金屬柱與該等金屬桿。
  7. 如申請專利範圍第6項所述之方法，另包括：形成一第一介電層；圖案化該第一介電層，以形成複數個開口；形成一晶種層，該晶種層包括多個第一部分與多個第二部分，該等第一部分延伸至該複數個開口中，以及該等第二部分位於該第一介電層上方；進行一第一鍍製程於該晶種層上，以形成一第一複數個重佈線；以及進行一第二鍍製程於該晶種層上，以形成該第一金屬柱，其中使用不同的遮罩層，進行該第一鍍製程與該第二鍍製程。
  8. 如申請專利範圍第7項所述之方法，其中重疊於該複數個開口的該第一複數個重佈線的多個第一部分具有多個頂表面，該等頂表面高於該第一介電層的一頂表面。
  9. 如申請專利範圍第6項所述之方法，其中在該第二裝置晶粒附接至該第一囊封材料之前，預先附接該黏著膜至該第二裝置晶粒。
  10. 一種半導體封裝，包括：一第一複數個重佈線；一第一囊封材料；一第一金屬柱，穿過該第一囊封材料，其中該第一金屬柱電耦合至該第一複數個重佈線；一第一裝置晶粒，被囊封於該第一囊封材料中，其中該第一裝置晶粒經由覆晶接合而接合至該第一複數個重佈線；一第二裝置晶粒，位於該第一囊封材料上方並且經由一黏著膜而附接至該第一囊封材料；一第二囊封材料，囊封該第二裝置晶粒於其中；一第二金屬柱，穿過該第二囊封材料並且電連接至該第一金屬柱；以及一第二複數個重佈線，位於該第二裝置晶粒與該第二金屬柱上方並且電耦合至該第二裝置晶粒與該第二金屬柱。
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