CN107403733B - 三层叠层封装结构及其形成方法 - Google Patents

三层叠层封装结构及其形成方法 Download PDF

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CN107403733B
CN107403733B CN201710286638.XA CN201710286638A CN107403733B CN 107403733 B CN107403733 B CN 107403733B CN 201710286638 A CN201710286638 A CN 201710286638A CN 107403733 B CN107403733 B CN 107403733B
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device die
metal pillar
layer
forming
dielectric layer
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CN107403733A (zh
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洪瑞斌
许峰诚
郑心圃
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明实施例公开了一种方法，其包含：形成多个第一重布线，在多个第一重布线的上方形成与其电连接的第一金属柱，并将第一器件管芯接合到多个第一重布线上。将第一金属柱和第一器件管芯密封在第一密封材料中。然后平坦化第一密封材料。方法还包含：在第一金属柱上方形成与其电连接的第二金属柱，通过粘合膜将第二器件管芯附接到第一密封材料，将第二金属柱和第二器件管芯密封在第二密封材料中，平坦化第二密封材料，并在第二金属柱和第二器件管芯的上方形成与其电连接的多个第二重布线。本发明实施例涉及三层叠层封装结构及其形成方法。

Description

三层叠层封装结构及其形成方法
技术领域
本发明实施例涉及三层叠层封装结构及其形成方法。
背景技术
现代电路的制造通常涉及若干步骤。集成电路首先在半导体晶圆上制造，半导体晶圆包含多个重复的半导体芯片，每一半导体芯片包含集成电路。然后，半导体芯片从晶圆上切割下来并进行封装。封装工艺具有两个主要目的：保护半导体芯片和将内部集成电路连接到外部引脚。
随着对更多功能的需求的增加，发展了叠层封装(PoP)技术，在PoP技术中，两个或多个封装件接合在一起，以扩大封装件的集成能力。随着高度的集成化，产生的PoP封装件的电性能能够提高，得益于组件之间缩短的连接路径。通过使用PoP技术，封装件设计变得更灵活和简单。也缩短了上市时间。
发明内容
根据本发明的一些实施例，提供了一种形成封装件的方法，包括：形成多个第一重布线；在所述多个第一重布线的上方形成电连接至所述多个第一重布线的第一金属柱；通过倒装芯片接合将第一器件管芯接合到所述多个第一重布线；将所述第一金属柱和所述第一器件管芯密封在第一密封材料中；平坦化所述第一密封材料，直至暴露所述第一金属柱；在所述第一金属柱上方形成电连接至所述第一金属柱的第二金属柱；通过粘合膜将第二器件管芯附接到所述第一密封材料；将所述第二金属柱和所述第二器件管芯密封在第二密封材料中；平坦化所述第二封装材料，直到暴露位于所述第二器件管芯的表面上的金属部件和所述第二金属柱；以及在所述第二金属柱和所述第二器件管芯的上方形成电连接至所述第二金属柱和所述第二器件管芯的多个第二重布线。
在上述方法中，在第一介电层的上方形成所述多个第一重布线，并且所述方法还包括：图案化所述第一介电层，以暴露所述多个第一重布线的部分，以及将封装件接合至所述多个第一重布线的部分。
在上述方法中，当所述第二器件管芯附接至所述第一密封材料时，所述第一密封材料的层仍覆盖所述第一密封材料。
在上述方法中，当所述第二器件管芯通过粘合膜附接到所述第一器件管芯时，所述粘合膜包括接触所述第一器件管芯的背面的第一侧和接触所述第二器件管芯的背面的第二侧。
在上述方法中，所述第二器件管芯通过粘合膜附接到所述第一密封材料。
在上述方法中，形成所述多个第一重布线包括：在第一介电层上方形成第二介电层；图案化所述第二介电层以暴露所述第一介电层；以及形成所述多个第一重布线的第一层，所述第一层包括延伸至所述第二介电层内的第一部分，和位于所述第二介电层上方的第二部分。
在上述方法中，形成所述多个第一重布线包括：在所述第二介电层的上方形成第三介电层；图案化所述第三介电层以形成开口；形成包括延伸至所述第三介电层内的第一部分的晶种层；执行第一镀以形成所述多个第一重布线的第二层，其中，所述第二层在所述晶种层上形成并填充所述第三介电层中的开口；以及通过第二镀执行形成所述第一金属柱的步骤，从所述晶种层来镀所述第一金属柱。
在上述方法中，还包括蚀刻所述晶种层的未被所述第一金属柱和所述多个第一重布线的第二层覆盖的部分。
在上述方法中，所述多个第一重布线的第二层的部分的顶面高于所述第三介电层的顶面。
在上述方法中，还包括将无源器件接合到所述多个第一重布线，其中，所述无源器件密封在所述第一密封材料中。
根据本发明的另一些实施例，还提供了一种形成封装件的方法，包括：将第一器件管芯和第一金属柱密封在第一密封材料中；平坦化所述第一密封材料以暴露所述第一金属柱，其中，所述第一密封材料的层直接位于所述第一器件管芯的上面；在所述第一密封材料的上方形成图案化掩模层，所述第一金属柱的中心部分通过所述图案化掩模层中的开口暴露；在所述开口中镀第二金属柱；去除所述图案化掩模层；通过粘合膜将第二器件管芯附接到所述第一密封材料；将所述第二器件管芯和所述第二金属柱密封在第二密封材料中；以及在所述第二金属柱和所述第二器件管芯的金属柱的上方形成电连接至所述第二金属柱和所述第二器件管芯的金属柱的多个第二重布线。
在上述方法中，还包括：形成第一介电层；图案化所述第一介电层以形成多个开口；形成包括第一部分和第二部分的晶种层，所述第一部分延伸至所述多个开口内，所述第二部分位于所述第一介电层的上方；在所述晶种层上执行第一镀以形成多个第一重布线；以及在所述晶种层上执行第二镀以形成所述第一金属柱，其中，通过使用不同的掩模层来执行所述第一镀和所述第二镀。
在上述方法中，与所述多个开口重叠的所述多个第一重布线的第一部分的顶面高于所述第一介电层的顶面。
在上述方法中，在所述第二器件管芯附接到所述第一密封材料之前，所述粘合膜已预先附接至所述第二器件管芯。
在上述方法中，所述第二器件管芯的背面面向所述第一器件管芯的背面，并且所述第二密封材料与所述第一密封材料接触。
根据本发明的又一些实施例，还提供了一种封装件，包括：多个第一重布线；第一密封材料；第一金属柱，穿透所述第一密封材料，其中，所述第一金属柱电连接到所述多个第一重布线；第一器件管芯，密封在所述第一密封材料中，其中，所述第一器件管芯通过倒装芯片接合被接合到所述多个第一重布线；第二器件管芯，位于所述第一密封材料的上方，并通过粘合膜附接至所述第一密封材料；第二密封材料，将所述第二器件管芯密封在所述第二密封材料种；第二金属柱，穿透所述第二密封材料并电连接到所述第一金属柱；以及多个第二重布线，位于所述第二器件管芯和所述第二金属柱的上方并电连接至所述第二器件管芯和所述第二金属柱。
在上述封装件中，所述第一器件管芯和所述第二器件管芯背对背。
在上述封装件中，所述第二密封材料与所述第一密封材料物理接触。
在上述封装件中，所述第二金属柱的横向尺寸小于所述第一金属柱的横向尺寸，并且所述第二金属柱与所述第一金属柱的中心部分接触。
在上述封装件中，还包括其中含有第三器件管芯的封装件，其中，所述封装件通过倒装芯片接合被接合到所述多个第一重布线。
附图说明
结合附图阅读以下详细说明，可更好地理解本发明的各方面。应注意到，根据本行业中的标准惯例，各种部件未按比例绘制。实际上，为论述清除，各部件的尺寸可任意增加或减少。
图1至图21示出了根据一些实施例的形成扇出叠层封装(PoP)结构的中间阶段的截面图。
图22示出了根据一些实施例的封装件的部分的截面图。
图23示出了根据一些实施例的形成PoP结构的工艺流程。
具体实施方式
以下公开提供了许多不同的实施例或示例，用于实现本发明的不同功能。下文描述了组件和布置的具体实例，以简化本发明。当然，这些仅仅是示例，并非旨在限制本发明。例如，在以下说明书中的第二部件上或上方的第一部件的形成可包括第一部件和第二部件形成为直接接触的实施例，还可包括在第一部件和第二部件之间形成附加部件、使第一部件和第二部件不可直接接触的实施例。此外，本发明可能会在各种实例中重复参考数字和/或字母。此重复是为了简化和清楚的目的，且本身并不决定所讨论的各种实施例和/或配置之间的关系。
此外，为了便于描述，本文使用空间相对术语，例如“下面的”、“下面”、“下方”、“上面的”、“上部”等来描述如图中所示的一个元件或部件与另一元件或部件的关系。空间相对术语旨在包含除附图所示的方向之外使用或操作中的器件的不同方向。该装置可调整为其他方向(旋转90度或者面向其他方向)，而其中所使用的空间相关叙词可做相应解释。
根据多个示例性实施例提供了扇出型叠层封装(PoP)结构/封装件及形成封装件的方法。也会进行讨论实施例的变形方案。在各附图和说明性实施例中，相同的参考标号用于代表相同的元件。
图1至图21示出了根据一些实施例的形成封装件的中间阶段的截面图。图1至图21所示出的步骤也在图23所示的工艺流程200中进行了示意性图示。
图1示出了载体20和在载体20上形成的脱模层22。载体20可为玻璃载体、陶瓷载体等。载体20呈圆形的俯视形状并可具有硅晶圆的俯视形状和大小。例如，载体20的直径可为8英尺、12英尺等。脱模层22可由聚合物基材料形成(例如光热转换(LTHC)层)，其可以与载体20一起从将在随后的步骤中形成的上面的结构去除。根据本发明的一些实施例，脱模层22由环氧基热释放材料形成。根据其他实施例，脱模层22由紫外(UV)胶形成。脱模层22可以以液态分配并固化。根据可选实施例，脱模层22为层压至载体22上的层压膜。脱模层22的顶面被调平且具有高共面度。
介电层24在脱模层22上形成。根据本发明的一些实施例，介电层24由聚合物形成，其也可为感光材料，例如，聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等，通过光曝光和显影可容易地将其图案化。根据可选实施例，介电层24由无机材料形成，例如，诸如氮化硅的氮化物，诸如氧化硅、磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)的氧化物等。
图2到图4示出了重布线(RDL)的形成。相应的步骤如图23中所示的工艺流程中的步骤202所示。参照图2，介电层26在介电层24的上方形成。介电层26可从形成介电层24的同组候选材料中选择。此外，介电层26可由与介电层24不同或相同的材料形成。介电层26经过图案化以形成开口28，通过开口28暴露下面的介电层24。
然后，参照图3，晶种层30在介电层26的上方形成。晶种层30的部分还延伸至开口28内。根据一些实施例，晶种层30包含钛层和位于钛层上方的铜层。根据替代实施例，晶种层30包含单个铜层或单个铜合金层。晶种层30可使用，例如物理汽相沉积(PVD)而形成。图案化掩模32，其可为光刻胶，在晶种层30的上方形成，然后经图案化以暴露晶种层30。开口28也暴露于图案化掩模32中的开口。
参照图4，形成RDL34。形成工艺包括在暴露的晶种层30上执行金属镀。然后去除图案化掩模32(图3)。可使用，例如化学镀，执行镀。先前被图案化掩模32覆盖的晶种层30的部分接下来在蚀刻步骤中被去除，留下图4中的RDL34。
参照图5，形成介电层36并图案化介电层36。相应的步骤如图23中所示的工艺流程中的步骤204所示。介电层36可以/可以不从形成介电层24和/或26的同组候选材料中选择，并可由聚合物或无机材料形成。然后图案化介电层36，和暴露RDL一些部分。
图6示出了晶种层40和上面的图案化掩模42的形成。晶种层40和图案化掩模42的材料和形成工艺与晶种层30和图案化掩模32的材料和形成过程相似，本文将不再重复。
然后执行镀工艺，形成图7所示的RDL44。相应的步骤如图23中所示的工艺流程中的步骤206所示。然后去除图6所示的图案化掩模42。根据一些实施例，所产生的RDL44的顶面高于介电层36的顶面。根据一些示例性实施例，位于介电层36的顶面上方的RDL44的部分的高度H1约介于约20μm到约30μm之间。在去除图案化掩模42后，暴露出被去除的图案化掩模42所覆盖的晶种层40的部分。晶种层40的未被去除的部分用于接下来的金属柱的形成。
参考图8，形成可由光刻胶形成的图案化掩模46并对其进行图案化，且在图案化掩模46中形成开口48。晶种层40的一些部分和RDL44的一些部分被暴露。然后执行镀步骤，形成图9所示的金属柱50。相应的步骤如图23中所示的工艺流程中的步骤208所示。在镀之后，去除图案化掩模46，然后去除先前被图案化掩模46覆盖的晶种层40的部分。产生的结构如图9所示。应了解，虽然一些金属柱50显示为离散的，这些金属柱实际上与RDL44的一些部分连接，RDL44的一些部分不在示出的平面中。在本说明书上下文中，晶种层40的剩余部分被认为是相应的RDL44和金属柱50的部分。
在前面的工艺步骤中，使用相同的晶种层40来执行两个电镀工艺，其中，两个电镀工艺使用不同的掩模。图6到图7示出第一电镀工艺，并且图8到图9示出第二电镀工艺。两个电镀工艺共享同一晶种层，有利地节约了制造成本。
图10到图20示出了用于形成PoP封装件的随后的步骤。在接下来的图中，示意性地示出了介电层26和36、RDL34和44的细节，而这些部件的细节可参照图1到图9。
图10示出了器件管芯52和无源器件54的放置。相应的步骤如图23中所示的工艺流程中的步骤210所示。根据本发明的一些实施例，器件管芯52为存储器管芯，例如动态随机存取存储器(DRAM)管芯。根据替代实施例，器件管芯52为逻辑管芯，例如，应用处理器(AP)管芯。无源器件包含，例如，电容器、电阻器和电感器等。当器件管芯52为DRAM管芯时，无源器件54可包含用作稳定器件管芯52的电源电压的电容器。器件管芯52和无源器件54包含与RDL44接触的焊料区56。
接下来，如图11所示，执行回流工艺，回流焊料区56以将器件管芯52和无源器件54接合到RDL44中。然后，如图12所示，器件管芯52、无源器件54和金属柱50然后密封在密封材料58中。相应的步骤如图23中所示的工艺流程中的步骤212所示。密封材料58可为模塑料，因此，在本文中，其可称为模塑料58。模塑料58也可为模塑底部填充物、环氧基树脂和/或树脂。模塑料58填充相邻金属柱50之间的间隙和金属柱50与器件管芯52之间的间隙。模塑料58的顶面高于金属柱50的顶端。
接下来，对薄模塑料58执行平坦化步骤，例如化学机械抛光(CMP)或机械研磨工艺，直至暴露金属柱50。产生的结构如图12所示。由于研磨，金属柱的顶端大体与模塑料58的顶面平齐(共面)。根据一些实施例，模塑料58的薄层在完成平坦化步骤后，覆盖器件管芯52。根据替代实施例，平坦化步骤完成之后，会暴露器件管芯52的背面，其中，示出的虚线59展示了根据一些实施例的模塑料58的产生的顶面。
图13示出了在金属柱50的顶部上形成金属柱60。相应的步骤如图23中所示的工艺流程中的步骤214所示。形成工艺可包含形成诸如光刻胶的掩模61，并曝光和显影/蚀刻此掩模以形成开口，其中，金属柱502的中心部分暴露于图案化掩模61中的开口。开口的俯视尺寸小于金属柱50的俯视尺寸。因此，金属柱50可用作用于镀金属柱60的晶种层。然后去除图案化掩模61。在生成的结构中，金属柱50横向延伸超过相应的上面的金属柱60的边缘，金属柱50的横向尺寸急剧过渡到金属柱60的横向尺寸。金属柱60可由均质材料形成，例如铜或者铜合金。
图14示出了器件管芯62的附接，其中，器件管芯62的背面面向器件管芯52的背面。相应的步骤如图23中所示的工艺流程中的步骤216所示。器件管芯62可通过管芯附接膜64粘附到模塑料58和/或器件管芯52的背面上。管芯附接膜64的边缘与器件管芯62的相应边缘共终点(垂直对齐)。管芯附接膜64在被附接到模塑料58之前是被粘附到器件管芯62的粘合膜。器件管芯62可包含具有与管芯附接膜64物理接触的背面(面向下的表面)的半导体衬底。器件管芯62还包含位于半导体衬底的正面(面向上的表面)上的集成电路器件(例如，有源器件，其包含，例如晶体管，未示出)。根据一些示例性实施例，器件管芯62为应用处理器管芯，其为逻辑管芯，例如，中央处理单元(CPU)管芯、图形处理单元(GPU)管芯和移动应用管芯等。此外，重叠同一器件管芯52的每对器件管芯62可包含数字管芯和模拟管芯。
器件管芯62可在其顶面处包含金属柱66。金属柱66电连接到器件管芯62内的集成电路。金属柱66可为铜柱，并且还可包含其他导电/金属材料，例如，铝、镍等。根据本发明的一些示例性实施例，如图14所示，金属柱66位于介电层68中，且金属柱66的顶面与介电层68的顶面共面。根据本发明的替代实施例，金属柱66嵌入到介电层68中，相应的介电层68的顶面高于金属柱66的顶面。介电层68可由聚合物形成，其可包含PBO、聚酰亚胺等。
参照图15，密封材料70在器件管芯62和金属柱60上进行密封/模制。相应的步骤如图23中所示的工艺流程中的步骤218。密封材料70可包含模塑料、模塑底部填充物、环氧基树脂和/或树脂。在模制工艺之后，密封材料70的顶面高于金属柱66和金属柱60的顶端。接下来，执行平坦化步骤，例如CMP步骤或机械研磨步骤来平坦化密封材料70，直至暴露金属柱60和金属柱66。由于平坦化，金属柱60的顶面大体上与金属柱66的顶面平齐(共面)，且大体与密封材料70的顶面大体上平齐(共面)。
参照图16，一层或多层介电层72的和相应的RDL74在密封材料70、金属柱60和金属柱66的上方形成。相应的步骤如图23中所示的工艺流程中的步骤220所示。根据本发明的一些实施例，介电层72由聚合物形成，例如PBO、聚酰亚胺等。根据本发明的一些实施例，介电层72由无机材料形成，例如氮化硅、氧化硅、氮氧化硅等。
形成RDL74以电连接到金属柱66和金属柱60。RDL74还使金属柱66和金属柱60互相连接。RDL74可包含金属迹线(金属线)和位于其下方并且连接至金属迹线的通孔。根据本发明的一些实施例，RDL74通过镀工艺形成，其中，每一RDL74包含晶种层(未示出)和位于晶种层上方的电镀的金属材料。晶种层和电镀的金属材料可由相同或不同的材料制成。
图17示出了根据本发明的一些示例性实施例的电连接件76的形成。相应的步骤如图23中所示的工艺流程中的步骤220所示。电连接件76电连接到RDL74、金属柱66和/或金属柱60。形成电连接件76可包含将焊球放置在RDL74上方，然后回流此焊球。根据本发明的替代实施例，形成电连接件76包含执行电镀步骤以在RDL74上方形成焊料区，和然后回流此焊料区。电连接件76还可包含金属柱，或金属柱和焊帽，其也可通常镀形成。在本文的上下文中，包含器件管芯62、金属柱60、密封材料70、RDL74和介电层72的组合结构称为封装件80，其可为复合晶圆。
无源器件也接合到RDL74中。无源器件78可包含电容器、电阻器、电感器等，且可为离散器件，其中，不形成诸如晶体管和二极管的有源器件。
接下来，封装件80从载体20中剥离。根据一些示例性剥离工艺，切割带82(图18)附接到封装件80以保护电连接件76，其中，切割带82固定到切割框83上。例如，通过在脱模层22(图17)上投射UV光线或激光来执行剥离操作。例如，当脱模层22由LTHC形成时，由光或激光产生的热量使得LTHC分解，并且因此，载体20脱离封装件80。产生的结构如图18所示。
图19示出了图案化以在介电层24中形成开口84。相应的步骤如图23中所示的工艺流程中的步骤222所示。例如，可利用激光钻孔图案化介电层24，以去除与RDL74中的一些金属焊盘重叠的部分，从而使得金属焊盘通过开口84暴露。
图20示出了封装件86接合到封装件80上，因此形成PoP封装件。相应的步骤如图23中所示的工艺流程中的步骤224所示。封装件86和80也分别称为PoP封装件的顶部封装件和底部封装件。通过焊料区88执行接合，焊料区88将RDL44接合到上面的封装件86中的金属焊盘。根据本发明的一些实施例，封装件86包含器件管芯90，其可为存储器管芯，例如闪速存储器管芯、静态随机存取存储器(SRAM)管芯和动态随机存取存储器(DRAM)管芯等。存储器管芯还可根据一些示例性实施例接合到封装件衬底92上。
在顶部封装件86接合到底部封装件80后，底部填充物94设置进入顶部封装件86和底部封装件80之间的间隙中。在接下来的步骤中，图20所示的封装件被切割成多个封装件。图21示出了所产生的封装件96的其中一个。相应的步骤如图23中所示的工艺流程中的步骤224所示。
在图20和21所示的封装件中，器件管芯52和器件管芯62背对背放置。根据一些实施例，存在密封材料58的层，其将器件管芯52从相应的的器件管芯62中分离。当器件管芯62为应用处理器管芯时，在操作过程中它们的温度通常很高，有时候高达110℃。另一方面，诸如器件管芯52的存储器管芯，不能承受如此高温，并可被器件管芯62散逸出来的热量所损坏。有利的是，密封材料58的层可作为热绝缘层，用于减少从器件管芯62中散逸至器件管芯52中的热量。根据其他实施例，当从管芯52和60中散逸的热量互相影响不大时，DAF64与器件管芯52的背面直接接触。
密封材料58和70之间的界面是可识别的，不管密封材料58和70彼此相同或彼此不同。例如，图22示出了封装件96中的区98(图21)的放大图。应了解，每一密封材料58和70可包含基底材料，其可为聚合物、环氧基树脂或树脂等，和基底材料中的填料颗粒。填料颗粒可为SiO2、Al2O3等的介电颗粒。例如，密封材料58可包含基底材料104A和填料颗粒102A，且密封材料70可包含基底材料104B和填料颗粒102B。填料颗粒102A和102B可具有可为球形的圆形表面。由于图12所示的平坦化，颗粒102A还研磨以具有平面。因此，研磨颗粒102A可包含位于基底材料104A内的球形表面和与DAF64和密封材料70接触的平坦表面。另一方面，密封材料70的面向密封材料58的一侧并未被平坦化。因此，与密封材料58物理接触的颗粒102B并未被研磨，并且因此，其圆形/球形表面将接触密封材料58。因此接地填充颗粒可用于确定密封材料58和70中的哪个已被研磨以及确定研磨表面的位置。此外，密封材料58和70也可由不同材料形成，并且因此，其界面可通过它们的材料上的不同加以确定。类似地，密封材料70(参照图15)的研磨表面可具有相似特性，且研磨表面是可识别的。
本发明的实施例具有有利特征。虽然PoP封装件总共有三层，只有两密封材料用于密封。因为密封材料具有不同的热膨胀系数(CTE)，所使用的密封材料层越多，产生的封装件的翘曲就越高。因此，通过使用两种密封材料密封器件管芯的两层(不是三层)，极大减少了封装件80(图19)的翘曲。器件管芯的第三层通过焊料接合，接合到底部封装件上。此外，完成封装件80之后执行接合，因此，不会在产生的封装件中产生大量翘曲。
此外，器件管芯90(图20和21)在最后步骤中集成到PoP封装件中，因此，器件管芯90不会遭受前面封装件工艺中的热预算。例如，可在温度高于约200℃(例如230℃)下执行聚合物层的固化和密封材料的固化，此温度会损坏闪速存储器。因此，闪速存储器管芯90可集成到封装件86中以避免热预算，从而提高封装产量。
根据本发明的一些实施例，一种方法包含：形成多个第一重布线，在多个第一重布线的上方形成与其电连接的第一金属柱，并通过倒装芯片接合将第一器件管芯接合到多个第一重布线上。将第一金属柱和第一器件管芯密封在第一密封材料中。平坦化第一密封材料直至暴露第一金属柱。此方法还包含：在第一金属柱上方形成与其电连接的第二金属柱，通过粘合膜将第二器件管芯附接到第一密封材料，在第二密封材料中密封第二金属柱和第二器件管芯，平坦化第二密封材料直至暴露第二金属柱和位于第二器件管芯表面上的金属部件，并在第二金属柱和第二器件管芯的上方形成与其电连接的多个第二重布线。
根据本发明的一些实施例，一种方法，包含在第一密封材料中密封第一器件管芯和第一金属柱，并平坦化第一密封材料直至暴露第一金属柱。第一密封材料的一层直接覆在第一器件管芯上。图案化掩模层在第一密封材料的上方形成，第一金属柱的中心部分通过在图案化掩模层中的开口得以暴露。在开口中镀第二金属柱。然后去除图案化掩模层。此方法还包含：通过粘合膜将第二金属管芯附接到第一密封材料，在第二密封材料中密封第二金属柱和第二器件管芯，并且在第二金属柱和第二器件管芯的金属柱上方形成与其电连接的多个第二重布线。
根据本发明的一些实施例，封装件包含多个第一重布线、第一密封材料和穿透第一密封材料的第一金属柱。第一金属柱电连接到多个第一重布线。第一器件管芯在第一密封材料中密封。第一器件管芯通过倒装芯片接合被接合到多个第一重布线。封装件还包含位于第一密封材料上方并通过粘合膜与其粘附的第二器件管芯；第二密封材料在其中密封第二器件管芯。第二金属柱穿透第二密封材料并连接到第一金属柱，和位于第二器件管芯和第二金属柱上方并与之电连接的多个第二重布线。
根据本发明的一些实施例，提供了一种形成封装件的方法，包括：形成多个第一重布线；在所述多个第一重布线的上方形成电连接至所述多个第一重布线的第一金属柱；通过倒装芯片接合将第一器件管芯接合到所述多个第一重布线；将所述第一金属柱和所述第一器件管芯密封在第一密封材料中；平坦化所述第一密封材料，直至暴露所述第一金属柱；在所述第一金属柱上方形成电连接至所述第一金属柱的第二金属柱；通过粘合膜将第二器件管芯附接到所述第一密封材料；将所述第二金属柱和所述第二器件管芯密封在第二密封材料中；平坦化所述第二封装材料，直到暴露位于所述第二器件管芯的表面上的金属部件和所述第二金属柱；以及在所述第二金属柱和所述第二器件管芯的上方形成电连接至所述第二金属柱和所述第二器件管芯的多个第二重布线。
在上述方法中，在第一介电层的上方形成所述多个第一重布线，并且所述方法还包括：图案化所述第一介电层，以暴露所述多个第一重布线的部分，以及将封装件接合至所述多个第一重布线的部分。
在上述方法中，当所述第二器件管芯附接至所述第一密封材料时，所述第一密封材料的层仍覆盖所述第一密封材料。
在上述方法中，当所述第二器件管芯通过粘合膜附接到所述第一器件管芯时，所述粘合膜包括接触所述第一器件管芯的背面的第一侧和接触所述第二器件管芯的背面的第二侧。
在上述方法中，所述第二器件管芯通过粘合膜附接到所述第一密封材料。
在上述方法中，形成所述多个第一重布线包括：在第一介电层上方形成第二介电层；图案化所述第二介电层以暴露所述第一介电层；以及形成所述多个第一重布线的第一层，所述第一层包括延伸至所述第二介电层内的第一部分，和位于所述第二介电层上方的第二部分。
在上述方法中，形成所述多个第一重布线包括：在所述第二介电层的上方形成第三介电层；图案化所述第三介电层以形成开口；形成包括延伸至所述第三介电层内的第一部分的晶种层；执行第一镀以形成所述多个第一重布线的第二层，其中，所述第二层在所述晶种层上形成并填充所述第三介电层中的开口；以及通过第二镀执行形成所述第一金属柱的步骤，从所述晶种层来镀所述第一金属柱。
在上述方法中，还包括蚀刻所述晶种层的未被所述第一金属柱和所述多个第一重布线的第二层覆盖的部分。
在上述方法中，所述多个第一重布线的第二层的部分的顶面高于所述第三介电层的顶面。
在上述方法中，还包括将无源器件接合到所述多个第一重布线，其中，所述无源器件密封在所述第一密封材料中。
根据本发明的另一些实施例，还提供了一种形成封装件的方法，包括：将第一器件管芯和第一金属柱密封在第一密封材料中；平坦化所述第一密封材料以暴露所述第一金属柱，其中，所述第一密封材料的层直接位于所述第一器件管芯的上面；在所述第一密封材料的上方形成图案化掩模层，所述第一金属柱的中心部分通过所述图案化掩模层中的开口暴露；在所述开口中镀第二金属柱；去除所述图案化掩模层；通过粘合膜将第二器件管芯附接到所述第一密封材料；将所述第二器件管芯和所述第二金属柱密封在第二密封材料中；以及在所述第二金属柱和所述第二器件管芯的金属柱的上方形成电连接至所述第二金属柱和所述第二器件管芯的金属柱的多个第二重布线。
在上述方法中，还包括：形成第一介电层；图案化所述第一介电层以形成多个开口；形成包括第一部分和第二部分的晶种层，所述第一部分延伸至所述多个开口内，所述第二部分位于所述第一介电层的上方；在所述晶种层上执行第一镀以形成多个第一重布线；以及在所述晶种层上执行第二镀以形成所述第一金属柱，其中，通过使用不同的掩模层来执行所述第一镀和所述第二镀。
在上述方法中，与所述多个开口重叠的所述多个第一重布线的第一部分的顶面高于所述第一介电层的顶面。
在上述方法中，在所述第二器件管芯附接到所述第一密封材料之前，所述粘合膜已预先附接至所述第二器件管芯。
在上述方法中，所述第二器件管芯的背面面向所述第一器件管芯的背面，并且所述第二密封材料与所述第一密封材料接触。
根据本发明的又一些实施例，还提供了一种封装件，包括：多个第一重布线；第一密封材料；第一金属柱，穿透所述第一密封材料，其中，所述第一金属柱电连接到所述多个第一重布线；第一器件管芯，密封在所述第一密封材料中，其中，所述第一器件管芯通过倒装芯片接合被接合到所述多个第一重布线；第二器件管芯，位于所述第一密封材料的上方，并通过粘合膜附接至所述第一密封材料；第二密封材料，将所述第二器件管芯密封在所述第二密封材料种；第二金属柱，穿透所述第二密封材料并电连接到所述第一金属柱；以及多个第二重布线，位于所述第二器件管芯和所述第二金属柱的上方并电连接至所述第二器件管芯和所述第二金属柱。
在上述封装件中，所述第一器件管芯和所述第二器件管芯背对背。
在上述封装件中，所述第二密封材料与所述第一密封材料物理接触。
在上述封装件中，所述第二金属柱的横向尺寸小于所述第一金属柱的横向尺寸，并且所述第二金属柱与所述第一金属柱的中心部分接触。
在上述封装件中，还包括其中含有第三器件管芯的封装件，其中，所述封装件通过倒装芯片接合被接合到所述多个第一重布线。
前述概括了多个实施例的部件，以使本领域技术人员可以更好地理解本发明的方面。本领域的技术人员应理解，其可以轻松地将本发明作为基础，用于设计或修改其他工艺或结构，从而达成与本文所介绍实施例的相同目的和/或实现相同的优点。本领域技术人员还应当意识到，这种等效结构不脱离本发明的精神和范围，并且在不脱离本发明的精神和范围的情况下，他们可以作出多种修改、替换和改变。

Claims (20)

1.一种形成封装件的方法，包括：
在多个介电层中形成多个第一重布线，包括：在所述多个介电层中的最上介电层中形成开口，形成在所述最上介电层上和所述开口内延伸的晶种层，在所述开口内填充所述多个第一重布线的最上层；
在所述多个第一重布线的上方并且直接从所述晶种层形成电连接至所述多个第一重布线的第一金属柱；
通过倒装芯片接合将第一器件管芯接合到所述多个第一重布线；
将所述第一金属柱和所述第一器件管芯密封在第一密封材料中；
平坦化所述第一密封材料，直至暴露所述第一金属柱；
在所述第一密封材料和所述第一金属柱上方形成图案化掩模层，所述第一金属柱的中心部分通过所述图案化掩模层中的开口暴露；
在所述开口中形成电连接至所述第一金属柱的第二金属柱；
通过粘合膜将第二器件管芯附接到所述第一密封材料，其中，当所述第二器件管芯附接至所述第一密封材料时，所述第一密封材料的层仍覆盖所述第一器件管芯；
将所述第二金属柱和所述第二器件管芯密封在第二密封材料中；
平坦化所述第二密封材料，直到暴露位于所述第二器件管芯的表面上的金属部件和所述第二金属柱；以及
在所述第二金属柱和所述第二器件管芯的上方形成电连接至所述第二金属柱和所述第二器件管芯的多个第二重布线。
2.根据权利要求1所述的方法，其中，所述多个第一重布线形成在第一介电层的上方，并且所述方法还包括：
图案化所述第一介电层，以暴露所述多个第一重布线的部分，以及
将所述第一器件管芯接合至所述多个第一重布线的部分。
3.根据权利要求1所述的方法，其中，所述第二器件管芯的背面面向所述第一器件管芯的背面。
4.根据权利要求1所述的方法，其中，当通过所述粘合膜将所述第二器件管芯附接到所述第一密封材料时，所述粘合膜包括接触所述第一器件管芯的背面的第一侧和接触所述第二器件管芯的背面的第二侧。
5.根据权利要求1所述的方法，其中，在所述第二器件管芯附接到所述第一密封材料之前，所述粘合膜已预先附接至所述第二器件管芯。
6.根据权利要求1所述的方法，其中，形成所述多个第一重布线包括：
在第一介电层上方形成第二介电层；
图案化所述第二介电层以暴露所述第一介电层；以及
形成所述多个第一重布线的第一层，所述第一层包括延伸至所述第二介电层内的第一部分，和位于所述第二介电层上方的第二部分。
7.根据权利要求6所述的方法，其中，形成所述多个第一重布线包括：
在所述第二介电层的上方形成用作所述最上介电层的第三介电层；
图案化所述第三介电层以形成所述开口；
形成所述晶种层；
执行第一镀以形成用作所述多个第一重布线的所述最上层的第二层，其中，所述第二层填充所述第三介电层中的开口；以及
通过第二镀执行形成所述第一金属柱的步骤，从所述晶种层来镀所述第一金属柱。
8.根据权利要求7所述的方法，还包括蚀刻所述晶种层的未被所述第一金属柱和所述多个第一重布线的第二层覆盖的部分。
9.根据权利要求7所述的方法，其中，所述多个第一重布线的第二层的部分的顶面高于所述第三介电层的顶面。
10.根据权利要求1所述的方法，还包括将无源器件接合到所述多个第一重布线，其中，所述无源器件密封在所述第一密封材料中。
11.一种形成封装件的方法，包括：
将第一器件管芯和第一金属柱密封在第一密封材料中；
平坦化所述第一密封材料以暴露所述第一金属柱，其中，所述第一密封材料的层直接位于所述第一器件管芯的上面；
在所述第一密封材料的上方形成图案化掩模层，所述第一金属柱的中心部分通过所述图案化掩模层中的开口暴露；
在所述开口中镀第二金属柱；
去除所述图案化掩模层；
通过粘合膜将第二器件管芯附接到所述第一密封材料；
将所述第二器件管芯和所述第二金属柱密封在第二密封材料中；以及
在所述第二金属柱和所述第二器件管芯的金属柱的上方形成电连接至所述第二金属柱和所述第二器件管芯的金属柱的多个第二重布线。
12.根据权利要求11所述的方法，还包括：
形成第一介电层；
图案化所述第一介电层以形成多个开口；
形成包括第一部分和第二部分的晶种层，所述第一部分延伸至所述多个开口内，所述第二部分位于所述第一介电层的上方；
在所述晶种层上执行第一镀以形成多个第一重布线；以及
在所述晶种层上执行第二镀以形成所述第一金属柱，其中，通过使用不同的掩模层来执行所述第一镀和所述第二镀。
13.根据权利要求12所述的方法，其中，与所述多个开口重叠的所述多个第一重布线的第一部分的顶面高于所述第一介电层的顶面。
14.根据权利要求11所述的方法，其中，在所述第二器件管芯附接到所述第一密封材料之前，所述粘合膜已预先附接至所述第二器件管芯。
15.根据权利要求11所述的方法，其中，所述第二器件管芯的背面面向所述第一器件管芯的背面，并且所述第二密封材料与所述第一密封材料接触。
16.一种封装件，包括：
多个第一重布线；
第一密封材料；
第一金属柱，穿透所述第一密封材料，其中，所述第一金属柱电连接到所述多个第一重布线；
第一器件管芯，密封在所述第一密封材料中，其中，所述第一器件管芯通过倒装芯片接合被接合到所述多个第一重布线；
第二器件管芯，位于所述第一密封材料的上方，并通过粘合膜附接至所述第一密封材料；
第二密封材料，将所述第二器件管芯密封在所述第二密封材料中；
第二金属柱，穿透所述第二密封材料并电连接到所述第一金属柱，在所述第二金属柱与所述第一金属柱直接接触的界面处，所述第二金属柱的宽度小于所述第一金属柱的宽度；以及
多个第二重布线，位于所述第二器件管芯和所述第二金属柱的上方并电连接至所述第二器件管芯和所述第二金属柱；
含有第三器件管芯的子封装件，其中，所述子封装件通过倒装芯片接合被接合到所述多个第一重布线。
17.根据权利要求16所述的封装件，其中，所述第一器件管芯和所述第二器件管芯背对背。
18.根据权利要求16所述的封装件，其中，所述第二密封材料与所述第一密封材料物理接触。
19.根据权利要求16所述的封装件，其中，所述第二金属柱的横向尺寸小于所述第一金属柱的横向尺寸，并且所述第二金属柱与所述第一金属柱的中心部分接触。
20.根据权利要求16所述的封装件，还包括：
无源器件，接合到所述多个第一重布线，其中，所述无源器件密封在所述第一密封材料中。
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