CN113539980A - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN113539980A
CN113539980A CN202110255812.0A CN202110255812A CN113539980A CN 113539980 A CN113539980 A CN 113539980A CN 202110255812 A CN202110255812 A CN 202110255812A CN 113539980 A CN113539980 A CN 113539980A
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semiconductor device
layer
semiconductor
substrate
encapsulant
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CN113539980B (zh
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陈宪伟
陈明发
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
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    • H01L25/0657—Stacked arrangements of devices
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Abstract

提供了半导体器件及其制造方法，其中，在半导体衬底上方附接半导体器件。在半导体衬底上方的金属化层和半导体衬底内形成开口，并且放置密封剂以填充开口。一旦放置密封剂，则分割半导体衬底以分隔器件。通过使金属化层的材料凹进并且形成开口，可以减少或消除分层损坏。

Description

半导体器件及其制造方法
技术领域
本申请的实施例涉及半导体器件及其制造方法。
背景技术
由于各种电子组件(例如，晶体管、二极管、电阻器、电容器等)的集成密度的不断提高，半导体工业经历了快速的增长。在大多数情况下，集成密度的提高来自最小部件尺寸的重复减小(例如，将半导体工艺节点朝着20nm以下节点缩小)，这允许将更多的组件集成至给定区域中。随着近来对小型化、更高速度和更大带宽以及更低功耗和等待时间的需求增长，对半导体管芯的更小且更具创造性的封装技术的需求日益增长。
随着半导体技术的进一步进步，已经出现作为进一步减小半导体器件的物理尺寸的有效选择的堆叠和接合的半导体器件。在堆叠的半导体器件中，诸如逻辑、存储器、处理器电路等的有源电路至少部分在不同的衬底上制造，并且然后物理和电接合在一起以形成功能器件。这种接合工艺利用复杂的技术，并且期望改进。
发明内容
本申请的一些实施例提供了一种半导体器件，包括：金属化层，连接半导体衬底上的有源器件；第一半导体器件，连接至所述金属化层；第二半导体器件，连接至所述金属化层；以及密封剂，密封所述第一半导体器件和所述第二半导体器件，所述密封剂与所述金属化层和所述半导体衬底物理接触。
本申请的另一些实施例提供了一种半导体器件，包括：第一半导体管芯，接合至半导体衬底上方的金属化层；第二半导体管芯，接合至所述金属化层；密封剂，在所述第一半导体管芯和所述第二半导体管芯之间延伸，所述密封剂也延伸穿过所述金属化层以与所述半导体衬底物理接触。
本申请的又一些实施例提供了一种制造半导体器件的方法，所述方法包括：将第一半导体管芯接合至器件，所述器件包括半导体衬底；将第二半导体管芯接合至所述器件；在所述半导体衬底中形成开口；用填充材料填充所述开口；以及通过所述开口内的所述填充材料分割所述半导体衬底。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该指出，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的具有附接至半导体晶圆的半导体器件的半导体晶圆。
图2示出了根据一些实施例的开口的形成。
图3示出了根据一些实施例的用密封剂填充开口。
图4示出了根据一些实施例的半导体晶圆的减薄。
图5示出了根据一些实施例的再分布结构的形成。
图6示出了根据一些实施例的分割工艺。
图7示出了根据一些实施例的集成扇出工艺。
图8示出了根据一些实施例的支撑结构的放置。
图9示出了根据一些实施例的具有支撑结构的再分布结构的形成。
图10示出了根据一些实施例的具有支撑结构的分割工艺。
图11示出了根据一些实施例的第二开口的形成。
图12示出了根据一些实施例的通过第二开口的分割工艺。
图13示出了根据一些实施例的第二开口的填充。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。器件可以以其它方式定向(旋转90度或在其它方位上)，而本文使用的空间相对描述符可以同样地作出相应的解释。
现在将关于在完全分割之前利用部分分割工艺的具体实施例来描述实施例。这种步骤顺序及其产生的结构提供了有助于减小或消除否则可能发生介电层剥离的改进的工艺和结构。
现在参考图1，半导体晶圆100示出为具有由并且在半导体晶圆100上方形成的多个第一半导体器件101。在特定实施例中，第一半导体器件101可以是存储器器件，诸如具有大量I/O接口(诸如大于256个接口)的宽I/O动态随机存取存储器(DRAM)器件，使得即使在低时钟速度下也可以实现大数据带宽。但是，第一半导体器件101也可以是具有高数据传输速率的任何其它合适类型的存储器器件，诸如具有高数据传输速率的LPDDRn存储器器件等，或可以是任何其它合适的器件，诸如逻辑管芯、中央处理单元(CPU)管芯、输入/输出管芯、这些的组合等。此外，半导体晶圆100可以由制造商从第三方制造商接收，或可以在室中制造。
在实施例中，第一半导体器件101可以包括第一衬底103、第一有源器件、第一金属化层105、第一晶圆接合层109和第一导电晶圆接合材料107。第一衬底103可以包括掺杂或未掺杂的块状硅或绝缘体上硅(SOI)衬底的有源层。通常，SOI衬底包括半导体材料层，诸如硅、锗、硅锗、SOI、绝缘体上的硅锗(SGOI)或它们的组合。可以使用的其它衬底包括多层衬底、梯度衬底或混合取向衬底。
第一有源器件包括可以用于生成第一半导体器件101的设计所期望的结构和功能要求的很多有源器件和无源器件，诸如电容器、电阻器、电感器等。可以使用任何合适的方法在第一衬底103内或上形成第一有源器件。
在第一衬底103和第一有源器件上方形成第一金属化层105，并且设计为连接各个有源器件以形成功能电路。在实施例中，第一金属化层105由介电材料(例如，低k介电材料、极低k介电材料、超低k介电材料、这些的组合等)和导电材料的交替层形成，并且可以通过任何合适的工艺(诸如沉积、镶嵌、双重镶嵌等)形成。在实施例中，可以存在由至少一个层间介电层(ILD)与第一衬底103分隔开的四层金属化层，但是第一金属化层105的精确数量取决于第一半导体器件101的设计。
可以在第一金属化层105上方的第一衬底103上形成第一晶圆接合层109。第一晶圆接合层109可以用于混合接合或融合接合(也称为氧化物至氧化物接合)。根据一些实施例，第一晶圆接合层109由诸如氧化硅、氮化硅等的含硅介电材料形成。可以使用任何合适的方法(诸如原子层沉积(ALD)、CVD、高密度等离子体化学汽相沉积(HDPCVD)、PVD等)将第一晶圆接合层109沉积至约1nm和约1000nm之间的厚度，诸如约5nm。但是，可以利用任何合适的材料、工艺和厚度。
一旦已经形成第一晶圆接合层109，则可以在第一晶圆接合层109内形成接合开口，以准备形成第一导电晶圆接合材料107。在实施例中，接合开口可以通过首先在第一晶圆接合层109的顶面上方施加并且图案化光刻胶形成。然后光刻胶用于蚀刻第一晶圆接合层109以形成开口。可以通过干蚀刻(例如，反应离子蚀刻(RIE)或中性束蚀刻(NBE))、湿蚀刻等蚀刻第一晶圆接合层109。根据本发明的一些实施例，蚀刻在第一金属化层105上停止，从而使得通过第一晶圆接合层109中的开口暴露第一金属化层105。
一旦已经暴露了第一金属化层105，则第一导电晶圆接合材料107可以形成为与第一金属化层105物理和电接触。在实施例中，第一导电晶圆接合材料107可以包括阻挡层、晶种层、填充金属或它们的组合(未单独示出)。例如，可以在第一金属化层105上方毯式沉积阻挡层。阻挡层可以包括钛、氮化钛、钽、氮化钽等。晶种层可以是诸如铜的导电材料，并且可以使用诸如溅射、蒸发或等离子体增强化学汽相沉积(PECVD)等的工艺在阻挡层上方毯式沉积，取决于期望的材料。填充金属可以是诸如铜或铜合金的导体，并且可以在晶种层上方沉积，以通过诸如电镀或化学镀的镀工艺填充或过填充开口。一旦已经沉积填充金属，则可以通过诸如化学机械抛光的平坦化工艺从开口的外部去除填充金属、晶种层和阻挡层的过量材料。但是，虽然已经描述了单重镶嵌工艺，但是也可以利用任何合适的方法，诸如双重镶嵌工艺。
但是，形成、图案化第一晶圆接合层109并且在平坦化之前将第一导电晶圆接合材料107镀至开口中的以上描述的实施例旨在说明，并不旨在限制实施例。相反，可以利用形成第一晶圆接合层109和第一导电晶圆接合材料107的任何合适的方法。在其它实施例中，第一导电晶圆接合材料107可以首先使用例如光刻图案化和镀工艺形成，并且然后在使用平坦化工艺平坦化之前，介电材料用于间隙填充第一导电晶圆接合材料107周围的区域。任何这种制造工艺完全旨在包括在实施例的范围内。
此外，在制造工艺中的任何期望的点，可以在第一衬底103和(如果期望)一层或多层第一金属化层105内形成衬底通孔111，以提供从第一衬底103的前侧至第一衬底103的背侧的电连接。在实施例中，TSV 111可以通过首先在第一衬底103和(如果期望)任何上面的第一金属化层105(例如，在形成期望的第一金属化层105之后但在形成下一个上面的第一金属化层105之前)中形成硅通孔(TSV)的开口形成。TSV开口可以通过施加并且显影合适的光刻胶，并且去除暴露于期望深度的下面的材料的部分形成。可以形成TSV开口以延伸至第一衬底103中至大于第一衬底103的最终期望高度的深度。因此，虽然深度取决于整体设计，但是深度可以在约20μm和约200μm之间，诸如约50μm的深度。
一旦在第一衬底103和/或任何第一金属化层105内已经形成TSV开口，则可以用衬垫内衬TSV开口。衬垫可以是例如由正硅酸乙酯(TEOS)或氮化硅形成的氧化物，但是可以使用任何合适的介电材料。衬垫可以使用等离子体增强化学汽相沉积(PECVD)工艺形成，但是可以使用其它合适的工艺，诸如物理汽相沉积或热工艺。此外，衬垫可形成为约0.1μm和约5μm之间的厚度，诸如约1μm。
一旦已经沿着TSV开口的侧壁和底部形成衬垫，则可以形成阻挡层，并且可以用第一导电材料填充TSV开口的剩余部分。第一导电材料可以包括铜，但是也可以利用其它合适的材料，诸如铝、合金、掺杂的多晶硅、它们的组合等。第一导电材料可以通过在晶种层上电镀铜、填充和过填充TSV开口形成。一旦已经填充TSV开口，则可以通过诸如化学机械抛光(CMP)的平坦化工艺去除TSV开口之外的过量的衬垫、阻挡层、晶种层和第一导电材料，但是可以使用任何合适的去除方法。
此外，在不同的第一半导体器件101之间形成划线区域102。在实施例中，划线区域102可以是可以实施分割以将第一半导体器件101中的第一个与第一半导体器件101中的第二个分隔的区域。划线区域102可以通过简单地不形成将在第一半导体器件101的操作期间利用的任何结构形成，但是可以在划线区域102内形成诸如测试结构的一些结构。
图1额外示出了第二半导体器件113和第三半导体器件115至第一导电晶圆接合材料107和第一晶圆接合层109的接合。在实施例中，第二半导体器件113和第三半导体器件115的每个可以各自是旨在与第一半导体器件101(例如，宽I/O DRAM器件)一起工作的片上系统器件，诸如逻辑器件。但是，可以利用任何合适的功能，诸如逻辑管芯、中央处理单元(CPU)管芯、输入/输出管芯、这些的组合等。
在实施例中，第二半导体器件113和第三半导体器件115可以每个具有第二衬底117、第二有源器件、第二金属化层119、第二晶圆接合层121和第二导电晶圆接合材料123。在实施例中，可以类似于第一衬底103、第一有源器件、第一金属化层105、第一晶圆接合层109和第一导电晶圆接合材料107形成第二衬底117、第二有源器件、第二金属化层119、第二晶圆接合层121和第二导电晶圆接合材料123，以上关于图1描述的。但是，在其它实施例中，这些结构可以使用不同的工艺和不同的材料形成。
一旦已经准备好第二半导体器件113和第三半导体器件115，则使用例如混合接合将第二半导体器件113和第三半导体器件115接合至第一半导体器件101。在实施例中，可以首先激活第一半导体器件101的表面(例如，第一晶圆接合层109和第一导电晶圆接合材料107)以及第二半导体器件113和第三半导体器件115的表面(例如，第二晶圆接合层121和第二导电晶圆接合材料123)。作为实例，激活第一半导体器件101、第二半导体器件113、第三半导体器件115可以包括干处理、湿处理、等离子体处理、暴露于惰性气体等离子体、暴露于H2、暴露于N2、暴露于O2或它们的组合。在使用湿处理的实施例中，例如，可以使用RCA清洁。在另一实施例中，激活工艺可以包括其它类型的处理。激活工艺有助于第一半导体器件101、第二半导体器件113和第三半导体器件115的混合接合。
在激活工艺之后，第二半导体器件113和第三半导体器件115可以放置为与第一半导体器件101接触。在利用混合接合的特定实施例中，第一导电晶圆接合材料107放置为与第二导电晶圆接合材料123物理接触，同时第一晶圆接合层109放置为与第二晶圆接合层121物理接触。在激活工艺化学修改表面的情况下，材料之间的接合工艺开始物理接触。
一旦物理接触已经开始接合工艺，则然后可以通过使组装经受热处理来加强接合。在实施例中，可以使第一半导体器件101、第二半导体器件113和第三半导体器件115经受约200℃和约400℃之间的温度，以增强第一晶圆接合层109和第二晶圆接合层121之间的接合。然后，可以使第一半导体器件101、第二半导体器件113和第三半导体器件115经受第一导电晶圆接合材料107和第二导电晶圆接合材料123的材料的共晶点或更高的温度。以这种方式，第一半导体器件101、第二半导体器件113和第三半导体器件115的融合形成混合接合器件。
此外，虽然具体工艺已经描述为开始和加强第一半导体器件101、第二半导体器件113和第三半导体器件115之间的混合接合，但是这些描述旨在说明，并不旨在限制实施例。相反，可以利用烘烤、退火、压制或其它接合工艺或工艺的组合的任何合适的组合。所有这种工艺完全旨在包括在实施例的范围内。
而且，虽然混合接合已经描述为将第一半导体器件101接合至第二半导体器件113和第三半导体器件115的一种方法，但是这也仅旨在说明，并不旨在限制实施例。相反，也可以利用任何合适的接合方法，诸如融合接合、铜至铜接合等或甚至使用例如球栅阵列的焊料接合。可以利用将第一半导体器件101接合至第二半导体器件113和第三半导体器件115的任何合适的方法。
图2示出了预先切割成位于第一半导体器件101之间的划线区域102的第一开口201的形成。第一开口201用于从第一金属化层105和其它层(例如，来自第一金属化层105的极低k材料)中去除在随后的分隔工艺(诸如锯切工艺(下面进一步描述))期间可能更易于分层的材料。通过在工艺中的这点上以可控的方式在划线区域102内去除并且使这些材料凹进，这些材料在之后的分割工艺期间不接触，并且可以减少由于分层造成的损坏。
在实施例中，第一开口201可以使用激光烧蚀工艺(在图2中由标有203的虚线圆柱表示)形成。例如，激光指向第一金属化层105的期望去除的那些部分。在激光钻孔工艺期间，钻孔角度与第一金属化层105的法线成约0度(垂直于第一金属化层105)至约30度。但是，可以利用用于激光烧蚀工艺203的任何合适的参数。
通过利用激光烧蚀工艺203，第一开口201可以形成为约11μm和约20μm之间的第一深度D1，诸如约15μm。因此，第一开口201将延伸至第一衬底103中至约3μm和约8μm之间的第二深度D2，诸如约5μm。此外，第一开口201可以形成为具有约50μm和约80μm之间的第一宽度W1，诸如约60μm。但是，可以利用任何合适的尺寸。
此外，通过利用激光烧蚀工艺203，第一开口201的形状将是不规则的。例如，第一开口201可以具有大致圆形的形状，而不是由激光烧蚀工艺203形成的笔直的侧壁。此外，激光烧蚀工艺203的指向将导致材料去除不均匀，从而导致在第一衬底103的材料内存在缺口。
但是，虽然激光烧蚀工艺203描述为形成第一开口201的一个可能的实施例，但是激光烧蚀工艺203的描述旨在说明，并不旨在限制。相反，也可以利用可以去除期望的材料的任何合适的工艺，诸如可以产生笔直侧壁的光刻掩模和蚀刻工艺。所有这种工艺完全旨在包括在实施例的范围内。
图3示出了一旦已经形成第一开口201，则可以用第一密封剂301密封第二半导体器件113、第三半导体器件115和第一半导体器件101。在实施例中，可以在模制器件中实施封装，该模制器件可以包括顶部模制部分和可与顶部模制部分分隔开的底部模制部分。当顶部模制部分降低至与底部模制部分相邻时，可以形成用于第一半导体器件101、第二半导体器件113和第三半导体器件115的模制腔。
在密封工艺期间，顶部模制部分可以与底部模制部分相邻放置，从而将第一半导体器件101、第二半导体器件113和第三半导体器件115封闭在模制腔内。一旦封闭，顶部模制部分和底部模制部分可以形成气密密封，以控制气体从模制腔的流入和流出。一旦密封，则可以将第一密封剂301放置在模制腔内。
第一密封剂301可以是环氧树脂或模塑料树脂，诸如聚酰亚胺、聚苯硫醚(PPS)、聚醚醚酮(PEEK)、聚醚砜(PES)、耐热结晶树脂、这些的组合等。可以在顶部模制部分和底部模制部分对准之前将第一密封剂301放置在模制腔中，或可以使用压缩模制、传递模制等通过注射口注射至模制腔中。
一旦将第一密封剂301放置至模制腔中，从而使得第一密封剂301密封第一半导体器件101、第二半导体器件113和第三半导体器件115，可以固化第一密封剂301以硬化第一密封剂301用于最佳保护。虽然精确的固化工艺至少部分取决于为第一密封剂301选择的特定材料，但是在模塑料选为第一密封剂301的实施例中，固化可以通过诸如将第一密封剂301加热至约100℃和约200℃之间，诸如约125℃进行约60秒至约3000秒，诸如约600秒的工艺发生。此外，引发剂和/或催化剂可以包括在第一密封剂301内以更好控制固化工艺。
但是，如本领域普通技术人员将认识到的，以上描述的固化工艺仅是示例性工艺，并不意味着限制当前的实施例。也可以使用其它固化工艺，诸如辐射或甚至允许第一密封剂301在环境温度下硬化。可以使用任何合适的固化工艺，并且所有这种工艺完全旨在包括在本文所讨论的实施例的范围内。
图3还示出了减薄第一密封剂301以暴露第二半导体器件113和第三半导体器件115用于进一步处理。可以例如使用机械研磨、化学方法或化学机械抛光(CMP)工艺实施减薄，由此利用化学蚀刻剂和研磨剂以反应并且研磨掉第一密封剂301，使得已经暴露第二半导体器件113和第三半导体器件115，并且第一密封剂301具有在约100μm和约150μm之间的厚度。因此，第二半导体器件113和第三半导体器件115可以具有也与第一密封剂301共面的平面。在另一实施例中，可以省略研磨。例如，如果在密封之后已经暴露第二半导体器件113和第三半导体器件115，则可以省略研磨。
此外，虽然以上描述的CMP工艺呈现为一个说明性实施例，但是其并不旨在限制实施例。任何其它合适的去除工艺可以用于减薄第一密封剂301。例如，可以利用一系列化学蚀刻。该工艺和任何其它合适的工艺可以用于平坦化第一密封剂301，并且所有这种工艺完全旨在包括在实施例的范围内。
图4示出了第一载体衬底401的放置和第一衬底103的背侧的减薄以暴露TSV 111。在实施例中，第一载体衬底401包括例如基于硅的材料(诸如玻璃或氧化硅的)或其它材料(诸如氧化铝)、任何这些材料中的组合等。第一载体衬底401是平面的，以容纳第二半导体器件113和第三半导体器件115的附接，其可以通过接合工艺或通过使用粘合层(未单独示出)附接。
一旦附接，可以减薄第一衬底103的第二侧以暴露TSV 111。在实施例中，第一衬底103的第二侧的减薄可以使TSV 111暴露。可以通过诸如CMP或蚀刻的平坦化工艺实施第一衬底103的第二侧的减薄。但是，可以使用减薄第一衬底103的第二侧的任何合适方法。
图5示出了具有位于第一衬底103的第二面上方并且与TSV 111连接的一层或多层的再分布结构501的形成。在实施例中，再分布结构501可以通过在TSV 111上方并且与TSV111电连接首先形成第一再分布层503形成。在实施例中，第一再分布层503可以通过诸如CVD或溅射的合适的形成工艺首先形成钛铜合金的晶种层(未示出)形成。然后可以形成光刻胶(也未示出)以覆盖晶种层，并且然后可以图案化光刻胶以暴露晶种层的位于期望第一再分布层503定位的那些部分。
一旦已经形成并且图案化光刻胶，则可以通过诸如镀的沉积工艺在晶种层上形成诸如铜的导电材料。导电材料可以形成为具有在约1μm和约10μm之间的厚度，诸如约4μm。但是，虽然所讨论的材料和方法适合于形成导电材料，但是这些材料仅是示例性的。任何其它合适的材料(诸如AlCu或Au)和任何其它合适的形成工艺(诸如CVD或PVD)可以用于形成第一再分布层503。
一旦已经形成导电材料，则可以通过诸如化学剥离和/或灰化的合适的去除工艺去除光刻胶。此外，在去除光刻胶之后，可以通过例如使用导电材料作为掩模的合适的蚀刻工艺去除由光刻胶覆盖的晶种层的那些部分。
一旦已经形成第一再分布层503，则可以形成再分布钝化层505。在实施例中，再分布钝化层505可以是聚苯并恶唑(PBO)，但是可以可选地利用任何合适的材料，诸如聚酰亚胺或聚酰亚胺衍生物，诸如低温固化的聚酰亚胺。可以使用例如旋涂工艺将再分布钝化层505放置为约5μm和约17μm之间的厚度，诸如约7μm，但是可以使用任何合适的方法和厚度。
一旦已经形成再分布钝化层505，则可以图案化再分布钝化层505以允许电接触至下面的第一再分布层503。在实施例中，可以使用例如光刻掩模和蚀刻工艺图案化再分布钝化层505。但是，任何合适的工艺可以用于暴露下面的第一再分布层503。
此外，如果期望，可以形成第一再分布层503和再分布钝化层505的额外的层以提供额外的互连选择。特别地，可以使用本文描述的工艺和材料形成任何合适数量的导电层和介电层。所有这种层完全旨在包括在实施例的范围内。
一旦已经形成并且图案化再分布钝化层505，则可以形成第一外部连接件507。在实施例中，第一外部连接件507可以是导电柱，诸如铜柱。在实施例中，导电柱可以通过首先形成晶种层，并且然后利用暴露期望导电柱定位的晶种层的开口施加并且图案化光刻胶形成。然后可以使用诸如电镀、化学镀等的工艺在光刻胶内形成诸如铜、钨、其它导电金属等的导电材料。一旦形成，则去除光刻胶并且使用导电材料作为掩模图案化晶种层。
可选地，如果期望，可以用焊料材料(未单独示出)覆盖第一外部连接件507。在这种实施例中，焊料凸块可以通过首先通过诸如蒸发、电镀、印刷、焊料转移以放置盖的材料的任何合适的方法形成锡层形成。一旦在适当位置，则可以实施回流以将材料成形为期望的凸块形状。
一旦已经形成第一外部连接件507，则第一钝化层509形成为保护第一外部连接件507。在实施例中，第一钝化层509可以由一种或多种合适的介电材料制成，诸如氧化硅、氮化硅或聚苯并恶唑(PBO)，但是可以使用任何合适的材料，诸如聚酰亚胺或聚酰亚胺衍生物，诸如低温固化的聚酰亚胺、这些的组合等。第一钝化层509可以使用诸如CVD、PVD、ALD、这些的组合等的工艺形成。但是，可以利用任何合适的材料和工艺。
但是，形成、图案化第一外部连接件507并且在平坦化之前放置第一钝化层509的以上描述的实施例旨在说明，并不旨在限制实施例。相反，可以利用形成第一外部连接件507和第一钝化层509的任何合适的方法。在其它实施例中，可以首先形成并且然后使用例如光刻图案化工艺图案化第一钝化层509，并且然后在使用平坦化工艺平坦化之前，在第一钝化层509内镀第一外部连接件507。任何这种制造工艺完全旨在包括在实施例的范围内。
图5也示出了在用于分割工艺的准备中的第一载体衬底401的去除。在实施例中，可以通过在粘合层处定向能量去除第一载体衬底401，从而减小其粘合性并且允许去除粘合层和第一载体衬底401。
图6示出了一旦已经去除第一载体衬底401，则通过第一开口201(并且因此通过位于第一开口201内的第一密封剂301)分割结构以形成分割的半导体器件600，诸如集成电路上的系统。在用于分割工艺的准备中，将第一密封剂301、第二半导体器件113和第三半导体器件115放置在诸如膜框架601的支撑结构上。但是，可以利用任何合适的支撑结构。
一旦在膜框架601上位于适当位置，则可以通过使用锯片(在图6中由虚线框603表示)实施分割以在第一半导体器件101之间切穿第一密封剂301，从而将第一半导体器件101中的一个(具有接合至它的第二半导体器件113和第三半导体器件115的每个)与第一半导体器件101中的另一个分隔开。
但是，因为来自第一金属化层105的一些材料已经从锯片603的路径中被去除并且凹进，并且剩余的材料已经通过第一密封剂301的放置而被增强，所以在分割工艺期间较少发生损坏。例如，当锯片603切穿半导体晶圆100时呈现的应力没有直接转化为存在于第一金属化层105内的易碎的极低k材料，因为锯片603非常简单，不接触易碎的极低k材料。此外，通过将第一密封剂301放置在锯片603和易碎材料之间，第一密封剂301可以用作缓冲区以帮助保护材料。所有这些有助于防止在分割工艺期间发生诸如分层的损坏。
通过形成第一开口201、用第一密封剂301填充第一开口201并且然后通过第一密封剂301分割，随着第一密封剂301进一步延伸至第一衬底103中，第一密封剂301将具有减小的宽度。例如，在分割之后，第一密封剂301具有与第一金属化层105相邻的在约3μm和约10μm之间(诸如约5μm)的第二宽度W2，同时也具有与所述第一衬底103的顶面相邻的在约2μm和约8μm之间(诸如约4μm)的第三宽度W3。但是，可以利用任何合适的尺寸。
图7示出了一旦已经形成分割的半导体器件600，则可以将分割的半导体器件600合并至集成扇出工艺中，以将分割的半导体器件600与其它器件集成。在实施例中，集成扇出工艺可以利用第二载体衬底(图7中未示出)、第二粘合层(在图7中也未示出)、聚合物层705、第二再分布层706和第二集成扇出通孔(TIV)708。在实施例中，第二载体衬底用作基于制造的初始材料，并且包括例如基于硅的材料(诸如玻璃或氧化硅)或其它材料(诸如氧化铝)、任何这些材料的组合等。第二载体衬底是平面的，以容纳诸如分割的半导体器件600的器件的附接。
可以在第二载体衬底上方放置第二粘合层，以有助于上面的结构至第二载体衬底的附接。在实施例中，第二粘合层是管芯粘附膜(DAF)，诸如环氧树脂、酚醛树脂、丙烯酸橡胶、二氧化硅填料或它们的组合，并且使用层压技术施加。但是，可以利用任何其它合适的材料和形成方法。
首先在第二粘合层上方形成聚合物层705。在实施例中，聚合物层705可以由一种或多种合适的介电材料制成，诸如氧化硅、氮化硅、低k电介质(诸如碳掺杂的氧化物)、极低k电介质(诸如多孔碳掺杂的二氧化硅)、这些的组合等。聚合物层705可以通过诸如化学汽相沉积(CVD)的工艺形成，但是可以利用任何合适的工艺，并且可以具有在约0.5μm和约5μm之间的厚度。
一旦已经形成聚合物层705，则可以在聚合物层705上方形成凸块下金属化层和第二再分布层706。在实施例中，凸块下金属化层可以包括三层导电材料，诸如钛层、铜层和镍层。但是，本领域的普通技术人员将认识到，存在适合于形成凸块下金属化层的许多合适的材料和层布置，诸如铬/铬-铜合金/铜/金的布置、钛/钛钨/铜的布置或铜/镍/金的布置。可以用于凸块下金属化层的任何合适的材料或材料层完全旨在包括在实施例的范围内。
在实施例中，通过在聚合物层705上方形成每层来创建凸块下金属化层。可以使用诸如电化学镀的镀工艺实施每层的形成，但是，可选地可以使用诸如溅射、蒸发或PECVD工艺的其它形成工艺，取决于期望的材料。凸块下金属化层可以形成为具有约0.7μm和约10μm之间的厚度，诸如约5μm。
在实施例中，第二再分布层706包括嵌入在一系列介电层内的一系列导电层。在实施例中，在聚合物层705上方形成一系列介电层中的第一个，并且一系列介电层中的第一个可以是诸如聚苯并恶唑(PBO)的材料，但是可以利用任何合适的材料，诸如聚酰亚胺或聚酰亚胺衍生物。可以使用诸如旋涂工艺放置一系列介电层中的第一个，但是可以使用任何合适的方法。
在已经形成一系列介电层中的第一个之后，可以通过去除一系列介电层中的第一个的部分穿过一系列介电层中的第一个制成开口。开口可以使用合适的光刻掩模和蚀刻工艺形成，但是任何合适的工艺可以用于图案化一系列介电层中的第一个。
一旦已经形成并且图案化一系列介电层中的第一个，则在一系列介电层中的第一个上方并且穿过形成在一系列介电层中的第一个内的开口形成一系列导电层中的第一个。在实施例中，一系列导电层中的第一个可以通过首先通过诸如CVD或溅射的合适的形成工艺形成钛铜合金的晶种层(未示出)形成。然后可以形成光刻胶(也未示出)以覆盖晶种层，并且然后可以图案化光刻胶以暴露晶种层的位于期望一系列导电层中的第一个定位的那些部分。
一旦已经形成并且图案化光刻胶，则可以通过诸如镀的沉积工艺在晶种层上形成诸如铜的导电材料。导电材料可以形成为具有约1μm和约10μm之间的厚度，诸如约5μm。但是，虽然所讨论的材料和方法适合于形成导电材料，但是这些材料仅是示例性的。任何其它合适的材料(诸如AlCu或Au)和任何其它合适的形成工艺(诸如CVD或PVD)可以用于形成一系列导电层中的第一个。一旦已经形成导电材料，则可以通过诸如灰化的合适去除工艺去除光刻胶。此外，在去除光刻胶之后，可以通过例如使用导电材料作为掩模的合适的蚀刻工艺去除晶种层的由光刻胶覆盖的那些部分。
一旦已经形成一系列导电层中的第一个，则一系列介电层中的第二个和一系列导电层中的第二个可以通过重复类似于一系列介电层中的第一个和一系列导电层中的第一个的重复步骤形成。可以根据期望重复这些步骤，以将一系列导电层的每个电连接至一系列导电层中的下面的一个，并且可以根据期望重复多次，直至已经形成一系列导电层中的最上部一个和一系列介电层中的最上部一个。在实施例中，可以继续一系列导电层和一系列介电层的沉积和图案化，直至第二再分布层706具有期望数量的层，但是可以利用任何合适数量的单个层。
一旦在第二载体衬底上方已经形成第二再分布层706，则形成与第二再分布层706电连接的第二TIV 708。在实施例中，第二TIV 708可以通过首先形成晶种层(未单独示出)形成。在实施例中，晶种层是有助于在随后的处理步骤期间形成更厚的层的导电材料的薄层。晶种层可以包括约
Figure BDA0002966998950000161
厚的钛层，随后是约
Figure BDA0002966998950000162
厚的铜层。可以使用诸如溅射、蒸发或PECVD工艺的工艺创建晶种层，取决于期望的材料。晶种层可以形成为具有在约0.3μm和约1μm之间的厚度，诸如约0.5μm。
一旦已经形成晶种层，则在晶种层上方放置光刻胶(也未示出)。在一实施例中，可以使用例如旋涂技术将光刻胶放置在晶种层上约50μm和约250μm之间的高度，诸如约120μm。一旦在适当位置，然后可以通过将光刻胶暴露于图案化的能量源(例如，图案化的光源)图案化光刻胶，以引起化学反应，从而在光刻胶的暴露于图案化光源的那些部分中引起物理变化。然后将显影剂施加至暴露的光刻胶，以利用物理变化，并且选择性去除光刻胶的暴露部分或者光刻胶的未暴露部分，这取决于期望的图案。在实施例中，形成在光刻胶中的图案是用于第二TIV 708的图案。第二TIV 708形成为位于随后附接的器件的不同侧上的这样的布置中。但是，可以利用用于第二TIV 708的图案的任何合适的布置。
在实施例中，第二TIV 708由一种或多种导电材料(诸如铜、钨、其它导电金属等)形成在光刻胶内，并且可以例如通过电镀、化学镀等形成。例如，使用电镀工艺，其中将晶种层和光刻胶浸没或浸入电镀液中。晶种层表面电连接至外部DC电源的负极侧，从而使得晶种层在电镀工艺中用作阴极。固态导电阳极(诸如铜阳极)也浸入溶液中，并且附接至电源的正极侧。来自阳极的原子溶解至阴极(例如晶种层)获取溶解的原子的溶液中，从而在光刻胶的开口内镀晶种层的暴露导电区域。
一旦使用光刻胶和晶种层已经形成第二TIV 708，则可以使用合适的去除工艺去除光刻胶。在实施例中，等离子体灰化工艺可以用于去除光刻胶，由此可以提高光刻胶的温度直至光刻胶经历热分解并且可以被去除。但是，可以利用任何其它合适的工艺，诸如湿剥离。光刻胶的去除可以暴露晶种层的下面部分。
一旦暴露，则可以实施晶种层的暴露部分的去除。在实施例中，可以通过例如湿或干蚀刻工艺去除晶种层的暴露部分(例如，未被第二TIV 708覆盖的那些部分)。例如，在干蚀刻工艺中，可以使用第二TIV 708作为掩模将反应物指向晶种层。在另一实施例中，可以将蚀刻剂喷雾或以其它方式与晶种层接触，以去除晶种层的暴露部分。在已经蚀刻掉晶种层的暴露部分之后，在第二TIV 708之间暴露第二再分布层706的部分。
一旦已经形成第二TIV 708，则可以在第二再分布层706上放置分割的半导体器件600。在实施例中，可以使用例如拾取和放置工艺放置分割的半导体器件600。但是，可以使用放置分割的半导体器件600的任何其它的方法。
图7额外示出了一旦已经放置分割的半导体器件600，则可以用第二密封剂712密封分割的半导体器件600和第二TIV 708。在实施例中，可以使用类似于以上关于图3描述的第二半导体器件113和第三半导体器件115的密封的工艺密封分割的半导体器件600和第二TIV 708。一旦密封，则可以平坦化分割的半导体器件600和第二TIV 708和第二密封剂712以暴露分割的半导体器件600和第二TIV 708。
图7也示出了一旦密封分割的半导体器件600和第二TIV 708，则形成第三再分布层701，以互连分割的半导体器件600和第二TIV 708。在实施例中，可以类似于第二再分布层706的形成(以上关于图7描述的)形成第三再分布层701。例如，沉积并且平坦化一系列钝化层和导电层以形成一层或多层导电布线。但是，可以利用任何合适的方法和材料。
在特定实施例中，可以形成三个导电层。但是，使用三个导电层旨在说明，并不旨在限制。相反，可以利用任何合适数量的导电层和钝化层，并且所有这样数量的层完全旨在包括在实施例的范围内。
图7进一步示出了第三外部连接件703的形成，以制成与第三再分布层701电接触。在实施例中，可以在第三再分布层701上放置第三外部连接件703，并且可以是包括诸如焊料的共晶材料的球栅阵列(BGA)，但是可以使用任何合适的材料。可选地，可以在第三外部连接件703和第三再分布层701之间利用凸块下金属。在第三外部连接件703是焊料凸块的实施例中，第三外部连接件703可以使用诸如直接落球工艺的落球方法形成。在另一实施例中，焊料凸块可以通过首先通过任何合适的方法(诸如蒸发、电镀、印刷、焊料转移)并且然后实施回流以将材料成形为期望的凸块形状形成。一旦已经形成第三外部连接件703，则可以实施测试以确保结构适合于进一步的处理。
在测试之后，第二载体衬底可以从分割的半导体器件600剥离。在实施例中，第三外部连接件703和因此包括分割的半导体器件600的结构可以附接至环形结构(图7中未示出)。环形结构可以是旨在在剥离工艺期间和之后为结构提供支撑和稳定性的金属环。在实施例中，第三外部连接件703使用例如紫外胶带附接至环形结构，但是可以使用任何其它合适的粘合或附接。一旦附接，则可以照射第二粘合层，并且可以物理去除第二粘合层和第二载体衬底。
一旦已经去除第二载体衬底并且暴露聚合物层705，可以使用例如激光钻孔方法图案化聚合物层705，通过该方法激光指向聚合物层705中期望去除的那些部分，以暴露下面的第二再分布层706。在激光钻孔工艺期间，钻孔能量可以在从0.1mJ至约60mJ的范围内，并且钻孔角度与聚合物层705的法线成约0度(垂直于聚合物层705)至约85度。
图7额外示出了第四外部连接件707的放置。在实施例中，第四外部连接件707可以是接触凸块，诸如微凸块或可控塌陷芯片连接(C4)凸块，并且可以包括诸如锡的材料或诸如焊膏、银或铜的其它合适材料。在第四外部连接件707是锡焊料凸块的实施例中，第四外部连接件707可以通过诸如蒸发、电镀、印刷、焊料转移、焊球放置等任何合适的方法首先形成锡层至例如约100μm的厚度形成。一旦在结构上已经形成锡层，则实施回流以将材料成形为期望的凸块形状。
图7额外示出了第四外部连接件707至第一封装件710的接合。在实施例中，第一封装件710可以包括第三衬底709、第五半导体器件711、第六半导体器件713(接合至第五半导体器件711)、第三接触焊盘715(用于电连接至第四外部连接件707)和第三密封剂717。在实施例中，第三衬底709可以是例如包括内部互连件(例如，衬底通孔)的封装衬底，以将第五半导体器件711和第六半导体器件713连接至第四外部连接件707。
在另一实施例中，第三衬底709可以是用作中间衬底的中介层，以将第五半导体器件711和第六半导体器件713连接至第四外部连接件707。在该实施例中，第三衬底709可以是例如掺杂或未掺杂的硅衬底或绝缘体上硅(SOI)衬底的有源层。但是，第三衬底709也可以是玻璃衬底、陶瓷衬底、聚合物衬底或可以提供合适的保护和/或互连功能的任何其它衬底。这些和任何其它合适的材料可以用于第三衬底709。
第五半导体器件711可以是为预期目的而设计的半导体器件，例如是逻辑管芯、中央处理单元(CPU)管芯、存储器管芯(例如，DRAM管芯)、这些的组合等。在实施例中，第五半导体器件711根据特定功能的期望在其中包括集成电路器件，诸如晶体管、电容器、电感器、电阻器、第一金属化层(未示出)等。在实施例中，第五半导体器件711设计并且制造成与分割的半导体器件600结合或同时工作。
第六半导体器件713可以类似于第五半导体器件711。例如，第六半导体器件713可以是为预期目的而设计的半导体器件(例如，DRAM管芯)，并且包括用于期望功能的集成电路器件。在实施例中，第六半导体器件713设计成与分割的半导体器件600和/或第五半导体器件711结合或同时工作。
第六半导体器件713可以接合至第五半导体器件711。在实施例中，第六半导体器件713仅与第五半导体器件711物理接合，诸如通过使用粘合剂。在该实施例中，第六半导体器件713和第五半导体器件711可以使用例如布线接合719电连接至第三衬底709，但是可以使用任何合适的电接合。
在另一实施例中，第六半导体器件713可以物理和电接合至第五半导体器件711。在该实施例中，第六半导体器件713可以包括与第五半导体器件711上的第五外部连接件(图7中也未单独示出)连接的第四外部连接件(图7中未单独示出)，以将第六半导体器件713与第五半导体器件711互连。
可以在第三衬底709上形成第三接触焊盘715，以在第五半导体器件711和例如第四外部连接件707之间形成电连接。在实施例中，可以在第三衬底709内的电布线上方并且与第三衬底709内的电布线(诸如衬底通孔)电接触形成第三接触焊盘715。第三接触焊盘715可以包括铝，但是也可以使用其它材料，诸如铜。第三接触焊盘715可以使用诸如溅射的沉积工艺形成，以形成材料层(未示出)，并且然后可以通过合适的工艺(诸如光刻掩模和蚀刻)去除材料层的部分，以形成第三接触焊盘715。但是，任何其它合适的工艺可以用于形成第三接触焊盘715。第三接触焊盘715可以形成为具有在约0.5μm和约4μm之间的厚度，诸如约1.45μm。
第三密封剂717可以用于密封和保护第五半导体器件711、第六半导体器件713和第三衬底709。在实施例中，第三密封剂717可以是模塑料并且可以使用模制器件(图7中未示出)放置。例如，可以在模制器件的腔内放置第三衬底709、第五半导体器件711和第六半导体器件713，并且可以气密密封腔。可以在气密密封腔之前放置第三密封剂717或可以通过注射口注射至腔中。在实施例中，第三密封剂717可以是模塑料树脂，诸如聚酰亚胺、PPS、PEEK、PES、耐热晶体树脂、这些的组合等。
一旦已经将第三密封剂717放置至腔中，从而使得第三密封剂717密封第三衬底709、第五半导体器件711和第六半导体器件713周围的区域，可以固化第三密封剂717以硬化第三密封剂717用于最佳的保护。虽然精确的固化工艺至少部分取决于为第三密封剂717选择的特定材料，但在模塑料选为第三密封剂717的实施例中，固化可以通过诸如将第三密封剂717加热至约100℃和约130℃之间，诸如约125℃进行约60秒至约3000秒，诸如约600秒的工艺发生。此外，引发剂和/或催化剂可以包括在第三密封剂717内以更好控制固化工艺。
但是，如本领域普通技术人员将认识到的，以上描述的固化工艺仅是示例性工艺，并不意味着限制当前的实施例。也可以使用其它固化工艺，诸如辐射或甚至允许第三密封剂717在环境温度下硬化。可以使用任何合适的固化工艺，并且所有这种工艺完全旨在包括在本文所讨论的实施例的范围内。
一旦已经形成第四外部连接件707，则将第四外部连接件707与第三接触焊盘715对准并且放置成与第三接触焊盘715物理接触，并且实施接合。例如，在第四外部连接件707是焊料凸块的实施例中，接合工艺可以包括回流工艺，由此第四外部连接件707的温度升高至第四外部连接件707将液化和流动的点，从而一旦第四外部连接件707重新固化，则将第一封装件710接合至第四外部连接件707。
图7也示出了在第一封装件710和聚合物层705之间的底部填充材料721的放置。在实施例中，底部填充材料721是用于缓冲和支撑第一封装件710免受操作和环境退化(诸如由操作期间的热量生成导致的应力)的保护材料。可以在第一封装件710和聚合物层705之间的间隔中注射或以其它方式形成底部填充材料721，并且可以例如包括在第一封装件710和聚合物层705之间分配并且然后固化以硬化的液态环氧树脂。
图7额外示出了分割。在实施例中，可以通过使用锯片(未单独示出)实施分割，以切穿底部填充材料721和第二密封剂712。但是，如本领域的普通技术人员将认识到的，利用用于分割的锯片仅仅是一个说明性实施例，并不旨在限制。可以利用用于实施分割(诸如利用一个或多个蚀刻)的任何方法。这些方法和任何其它合适的方法可以用于分割结构。
通过在分割之前去除划线区域102的部分，可以以减小的损坏可能性(诸如极低k介电材料的分层)制造分割的半导体器件600。通过减小损坏的可能性，可以在制造工艺期间实现更大的良率，并且可以制造更可靠的半导体器件。
图8示出了另一实施例，其中在第一密封剂301是较软的材料(诸如间隙填充材料801)而不是诸如模塑料的材料的实施例中，支撑结构803用于帮助提供支撑。在实施例中，间隙填充材料801可以是非聚合物介电材料，诸如氧化硅、氮化硅、这些的组合等，其使用任何合适的工艺代替第一密封剂301沉积。例如，间隙填充材料可以通过CVD、PECVD或ALD沉积工艺、FCVD或旋涂玻璃工艺形成，以填充和/或过填充第二半导体器件113和第三半导体器件115之间的间隔，并且也填充第一开口201。一旦已经沉积间隙填充材料801，则可以用第二半导体器件113和第三半导体器件115将间隙填充材料801平坦化至约20μm和约50μm之间的厚度。
但是，在利用较软的材料的实施例中，支撑结构803可以用于提供额外支撑以支持间隙填充材料801。因此，图8也示出了支撑结构803的放置，以帮助支撑器件并且补偿间隙填充材料801中的不同材料。在实施例中，支撑结构803可以是诸如硅的半导体材料(例如，硅晶圆)。但是，也可以使用合适的支撑材料，诸如玻璃支撑结构或甚至金属支撑结构。
支撑结构803可以使用例如接合工艺(诸如融合接合工艺)附接至间隙填充材料801。在其它实施例中，可以利用粘合剂或任何其它合适的材料或方法附接支撑结构803，以附接支撑结构803和间隙填充材料801。所有这些材料和工艺完全旨在包括在实施例的范围内。
一旦已经附接支撑结构803，则可以随后进行以上关于图4描述的工艺的剩余部分。例如，可以附接第一载体衬底401(至该实施例中的支撑结构803)，并且可以减薄第一衬底103以暴露TSV 111。但是，可以利用任何合适的工艺。
图9示出了具有仍附接的支撑结构803的再分布结构501、第一外部连接件507和第一钝化层509的形成。在实施例中，可以如以上关于图5所描述的那样形成再分布结构501、第一外部连接件507和第一钝化层509。但是，可以利用任何合适的工艺和材料。
图10示出了该结构以及支撑结构803的分割。在实施例中，可以如以上关于图6所描述的那样实施分割。例如，锯片可以用于切穿半导体晶圆100以及间隙填充材料801和支撑结构803，以形成具有仍附接的支撑结构803的分割的半导体器件600。但是，可以利用分割器件以形成分割的半导体器件600的任何合适方法。
此外，在一些实施例中，可以使用用于去除支撑结构803的任一剥离工艺、减薄工艺或任何其它合适的工艺去除支撑结构803。但是，在其它实施例中，支撑结构803可以作为分割的半导体器件600的一部分留在适当的位置，其中，支撑结构803不仅可以提供结构支撑，而且用作散热器，以去除在第二半导体器件113和第三半导体器件115的操作期间产生的热量。
通过利用支撑结构803，可以利用更广泛的材料以密封第二半导体器件113和第三半导体器件115，以帮助减小在分割期间由于分层而造成的损坏。此外，通过使用支撑结构803作为集成散热器，可以避免散热器的随后的附接。这与减小由分割造成的损坏一起有助于增大制造良率并且减少操作问题。
图11示出了另一实施例，第二开口1101与第一开口201(见图2)一起用于帮助保护结构免于在随后的分割工艺期间的分层损坏。在该实施例中，如以上关于图1至图5所描述的那样形成结构。但是，一旦已经形成再分布结构501、第一外部连接件507和第一钝化层509，在再分布结构501、第一外部连接件507、第一钝化层509和第一衬底103内形成第二开口1101，以提供分割工艺(例如，锯片)可以通过的额外间隔。
在实施例中，第二开口1101可以使用第二激光烧蚀工艺(在图11中由标有1103的虚线圆柱表示)形成。例如，在一些实施例中，激光指向第一钝化层509的期望被去除的那些部分。在第二激光烧蚀工艺1103期间，钻孔角度与第一钝化层509的法线成约0度(垂直于第一金属化层105)至约30度。但是，可以利用用于第二激光烧蚀工艺1103的任何合适的参数。
通过利用第二激光烧蚀工艺1103，第二开口1101可以形成为在约20μm和约30μm之间的第三深度D3，诸如约25μm之间。因此，第二开口1101将延伸至第一衬底103中至约3μm和约8μm之间的第四深度D4，诸如约5μm。此外，第二开口1101可以形成为具有在约50μm和约80μm之间的第四宽度W4，诸如约60μm之间。但是，可以利用任何合适的尺寸。
此外，通过利用第二激光烧蚀工艺1103，第二开口1101的形状将是不规则的。例如，第二开口1101可以具有大致圆形的弯曲形状，而不是由第二激光烧蚀工艺1103形成的笔直的侧壁。此外，第二激光烧蚀工艺1103的指向将导致材料去除不均匀，从而导致在第一衬底103的材料内存在缺口。
但是，虽然激光钻孔工艺描述为形成第二开口1101的一个可能的实施例，但是激光钻孔工艺的描述旨在说明，并不旨在限制。相反，也可以利用可以去除期望的材料的任何合适的工艺，诸如可以产生笔直侧壁的光刻掩模和蚀刻工艺。所有这种工艺完全旨在包括在实施例的范围内。
图12示出了一旦已经形成第二开口1101，则可以通过第一开口201和第二开口1101分割半导体晶圆100。在实施例中，可以如以上关于图6所描述的那样实施分割。例如，锯片603可以用于通过第二开口1101和第一开口201切穿半导体晶圆100。但是，可以利用任何合适的分割工艺。
图13示出了也填充第二开口1101而不是简单制成，以在分割工艺期间提供额外的结构支撑的又一实施例。在实施例中，可以用第四密封剂1301填充第二开口1101。此外，第四密封剂1301可以是与以上关于图3描述的第一密封剂301或以上关于图8描述的间隙填充材料801类似的材料，并且可以使用与以上关于图3描述的第一密封剂301或以上关于图8描述的间隙填充材料801类似的方法形成。例如，第四密封剂1301可以是模塑料或间隙填充材料，并且可以使用任一模制工艺或沉积工艺施加以填充和/或过填充第二开口1101。一旦在适当位置，如果期望，则可以使用诸如化学机械抛光的工艺平坦化第四密封剂1301，以将第四密封剂1301嵌入第二开口1101中。
图13也示出了一旦已经施加第四密封剂1301，则可以通过第一开口201、第二开口1101和第四密封剂1301分割结构。在实施例中，可以如以上关于图6所描述的那样实施分割。例如，锯片603可以用于通过第二开口1101和第四密封剂1301切穿半导体晶圆100。但是，可以利用任何合适的分割工艺。
通过在分割之前去除与半导体晶圆100的两侧相邻的划线区域102的部分，分割的半导体器件600可以制造为具有减小的损坏可能性(诸如第一金属化层105和再分布结构501中的介电材料分层)。通过减小损坏的可能性，可以在制造工艺期间实现更大的良率，并且可以制造更可靠的半导体器件。
根据实施例，半导体器件包括：金属化层，连接半导体衬底上的有源器件；第一半导体器件，连接至金属化层；第二半导体器件，连接至金属化层；以及密封剂，密封第一半导体器件和第二半导体器件，密封剂与金属化层和半导体衬底物理接触。在实施例中，密封剂包括模塑料。在实施例中，密封剂包括氧化硅。在实施例中，支撑结构附接至氧化硅。在实施例中，随着密封剂延伸至半导体衬底中，密封剂在宽度上减小。在实施例中，半导体器件还包括：衬底通孔，延伸穿过半导体衬底；再分布层，连接至衬底通孔；以及钝化层，与再分布层相邻。在实施例中，钝化层具有弯曲的侧壁。
根据另一实施例，半导体器件包括：第一半导体管芯，接合至半导体衬底上方的金属化层；第二半导体管芯，接合至金属化层；密封剂，在第一半导体管芯和第二半导体管芯之间延伸，密封剂也延伸穿过金属化层以与半导体衬底物理接触。在实施例中，密封剂具有与金属化层相邻的第一宽度和小于与半导体衬底相邻的第一宽度的第二宽度。在实施例中，密封剂具有与半导体衬底的第二表面共面的第一表面。在实施例中，密封剂是氧化物材料。在实施例中，半导体器件还包括：支撑结构，附接至氧化物材料。在实施例中，半导体器件还包括：衬底通孔，延伸穿过半导体衬底；再分布层，连接至衬底通孔；以及钝化层，与再分布层相邻。在实施例中，半导体器件还包括：第二密封剂，延伸穿过再分布层以与半导体衬底物理接触。
在又一实施例中，制造半导体器件的方法，方法包括：将第一半导体管芯接合至器件，器件包括半导体衬底；将第二半导体管芯接合至器件；在半导体衬底中形成开口；用填充材料填充开口；以及通过开口内的填充材料分割半导体衬底。在实施例中，方法还包括：减薄半导体衬底以暴露衬底通孔；形成与衬底通孔电连接的再分布层；以及在再分布层上方施加钝化层。在实施例中，方法还包括：在分割半导体衬底之前形成延伸穿过钝化层并且至半导体衬底中的第二开口。在实施例中，填充开口用氧化物材料填充开口。在实施例中，方法还包括将支撑结构附接至氧化物材料。在实施例中，填充开口用模塑料填充开口。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (10)

1.一种半导体器件，包括：
金属化层，连接半导体衬底上的有源器件；
第一半导体器件，连接至所述金属化层；
第二半导体器件，连接至所述金属化层；以及
密封剂，密封所述第一半导体器件和所述第二半导体器件，所述密封剂与所述金属化层和所述半导体衬底物理接触。
2.根据权利要求1所述的半导体器件，其中，所述密封剂包括模塑料。
3.根据权利要求1所述的半导体器件，其中，所述密封剂包括氧化硅。
4.根据权利要求3所述的半导体器件，其中，支撑结构附接至所述氧化硅。
5.根据权利要求1所述的半导体器件，其中，所述密封剂的宽度随着所述密封剂延伸至所述半导体衬底中而减小。
6.根据权利要求1所述的半导体器件，还包括：
衬底通孔，延伸穿过所述半导体衬底；
再分布层，连接至所述衬底通孔；以及
钝化层，与所述再分布层相邻。
7.根据权利要求6所述的半导体器件，其中，所述钝化层具有弯曲的侧壁。
8.一种半导体器件，包括：
第一半导体管芯，接合至半导体衬底上方的金属化层；
第二半导体管芯，接合至所述金属化层；
密封剂，在所述第一半导体管芯和所述第二半导体管芯之间延伸，所述密封剂也延伸穿过所述金属化层以与所述半导体衬底物理接触。
9.根据权利要求8所述的半导体器件，其中，所述密封剂具有与所述金属化层相邻的第一宽度和小于与所述半导体衬底相邻的所述第一宽度的第二宽度。
10.一种制造半导体器件的方法，所述方法包括：
将第一半导体管芯接合至器件，所述器件包括半导体衬底；
将第二半导体管芯接合至所述器件；
在所述半导体衬底中形成开口；
用填充材料填充所述开口；以及
通过所述开口内的所述填充材料分割所述半导体衬底。
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