TWI773216B - 半導體元件及製造方法 - Google Patents

半導體元件及製造方法 Download PDF

Info

Publication number
TWI773216B
TWI773216B TW110110734A TW110110734A TWI773216B TW I773216 B TWI773216 B TW I773216B TW 110110734 A TW110110734 A TW 110110734A TW 110110734 A TW110110734 A TW 110110734A TW I773216 B TWI773216 B TW I773216B
Authority
TW
Taiwan
Prior art keywords
semiconductor
layer
semiconductor element
substrate
opening
Prior art date
Application number
TW110110734A
Other languages
English (en)
Other versions
TW202203404A (zh
Inventor
陳憲偉
陳明發
Original Assignee
台灣積體電路製造股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW202203404A publication Critical patent/TW202203404A/zh
Application granted granted Critical
Publication of TWI773216B publication Critical patent/TWI773216B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/2105—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/80048—Thermal treatments, e.g. annealing, controlled pre-heating or pre-cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80053—Bonding environment
    • H01L2224/80095—Temperature settings
    • H01L2224/80096—Transient conditions
    • H01L2224/80097—Heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80801—Soldering or alloying
    • H01L2224/80815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80905—Combinations of bonding methods provided for in at least two different groups from H01L2224/808 - H01L2224/80904
    • H01L2224/80906—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1041—Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Transistors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

本發明實施例提供一種半導體元件及製造方法，其中半導體元件附接在半導體基底上方。在半導體基底上方的金屬化層及半導體基底內形成開口，且放置包封體以填充開口。一旦放置包封體，即將半導體基底單體化以分離元件。藉由使金屬化層的材料凹進且形成開口，可減少或消除分層損壞。

Description

半導體元件及製造方法
本發明實施例是有關於一種半導體元件及製造方法。
半導體產業歸因於各種電子組件(例如電晶體、二極體、電阻器、電容器等)的積體密度持續改良而經歷快速增長。主要地，此積體密度改良來自最小特徵尺寸的反覆減小(例如，使半導體製程節點朝向次20奈米節點縮小)，其允許更多組件整合至給定區域中。隨著近來對小型化、較高速度以及較大頻寬以及較低功率消耗及潛時的需求增長，因此對於更小且更具創造性的半導體晶粒的封裝技術的需要增長。
隨著半導體技術進一步發展，經堆疊及接合的半導體元件已作為有效替代物出現以進一步減小半導體元件的實體尺寸。在經堆疊半導體元件中，將諸如邏輯、記憶體、處理器電路以及其類似者的主動電路至少部分地製造於獨立基底上，且接著實體接合且電接合在一起以形成功能元件。此類接合製程利用複雜的技術，且需要改良。
根據本發明的一些實施例，一種半導體元件包含：連接半導體基底上的主動元件的金屬化層；連接至所述金屬化層的第一半導體元件；連接至所述金屬化層的第二半導體元件；以及包封所述第一半導體元件及所述第二半導體元件的包封體，所述包封體與所述金屬化層及所述半導體基底實體接觸。
根據本發明的一些實施例，一種半導體元件包含：接合至半導體基底上方的金屬化層的第一半導體晶粒；接合至所述金屬化層的第二半導體晶粒；在所述第一半導體晶粒與所述第二半導體晶粒之間延伸的包封體，所述包封體亦延伸穿過所述金屬化層以與所述半導體基底實體接觸。
根據本發明的一些實施例，一種製造半導體元件的方法，所述方法包含：將第一半導體晶粒接合至元件，所述元件包括半導體基底；將第二半導體晶粒接合至所述元件；在所述半導體基底中形成開口；用填充材料填充所述開口；以及經由所述開口內的所述填充材料單體化所述半導體基底。
100:半導體晶圓
101:第一半導體元件
102:切割區
103:第一基底
105:第一金屬化層
107:第一導電晶圓接合材料
109:第一晶圓接合層
111:基底穿孔
113:第二半導體元件
115:第三半導體元件
117:第二基底
119:第二金屬化層
121:第二晶圓接合層
123:第二導電晶圓接合材料
201:第一開口
203:雷射消熔製程
301:第一包封體
401:第一載體基底
501:重佈線結構
503:第一重佈線層
505:重佈線鈍化層
507:第一外部連接件
509:第一鈍化層
600:單體化半導體元件
601:膜框架
603:鋸刀
701:第三重佈線層
703:第三外部連接件
705:聚合物層
706:第二重佈線層
707:第四外部連接件
708:第二積體扇出型穿孔
709:第三基底
710:第一封裝
711:第五半導體元件
712:第二包封體
713:第六半導體元件
715:第三接觸焊墊
717:第三包封體
719:線接合件
721:填充材料
801:間隙填充材料
803:支撐結構
1101:第二開口
1103:第二雷射消熔製程
1301:第四包封體
D1:第一深度
D2:第二深度
D3:第三深度
D4:第四深度
W1:第一寬度
W2:第二寬度
W3:第三寬度
W4:第四寬度
當結合隨附圖式閱讀時，將自以下實施方式最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，為了論述清楚起見，可任意增加或減小各種特徵的尺寸。
圖1示出根據一些實施例的具有附接至半導體晶圓的半導體元件的半導體晶圓。
圖2示出根據一些實施例的開口的形成。
圖3示出根據一些實施例的用包封體對開口的填充。
圖4示出根據一些實施例的半導體晶圓的薄化。
圖5示出根據一些實施例的重佈線結構的形成。
圖6示出根據一些實施例的單體化製程。
圖7示出根據一些實施例的積體扇出製程。
圖8示出根據一些實施例的支撐結構的放置。
圖9示出根據一些實施例的具有支撐結構的重佈線結構的形成。
圖10示出根據一些實施例的具有支撐結構的單體化製程。
圖11示出根據一些實施例的第二開口的形成。
圖12示出根據一些實施例的經由第二開口的單體化製程。
圖13示出根據一些實施例的第二開口的填充。
以下揭露內容提供用以實施本發明的不同特徵的許多不同實施例或實例。下文描述組件及配置的具體實例以簡化本揭露。當然，此等組件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複圖式元件符號及/或字母。此重複是出於簡單及清晰的目的，且本身不規定所論述的各種實施例及/或組態之間的關係。
此外，為了便於描述，在本文中可使用諸如「在、、、下 方(beneath)」、「下方(below)」、「下部(lower)」、「在、、、上方(above)」、「上部(upper)」等空間相對術語來描述如圖式中所示出的一個元件或特徵與另一(些)元件或特徵的關係。除圖式中所描繪的定向外，空間相對術語亦意欲涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於其他定向)，且本文中所使用的空間相對描述詞亦可相應地解釋。
現將關於在完全單體化之前利用局部單體化製程的具體實施例描述實施例。此類步驟次序及其所得結構得到有助於減少或消除原本可能發生的介電層剝落的經改良製程及結構。
現參考圖1，示出半導體晶圓100，其具有與半導體晶圓100一起形成且在半導體晶圓100上方的多個第一半導體元件101。在一特定實施例中，第一半導體元件101可為記憶體元件，諸如寬I/O動態隨機存取記憶體(dynamic random access memory；DRAM)元件，其具有大量I/O介面，諸如多於256個介面，使得即使在低時脈速度下亦可實現較大的資料頻寬。然而，第一半導體元件101亦可為具有較高資料傳送速率的任何其他合適類型的記憶體元件，諸如具有較高資料傳送速率的LPDDRn記憶體元件或其類似者，或可為任何其他合適的元件，諸如邏輯晶粒、中央處理單元(central processing unit；CPU)晶粒、輸入/輸出晶粒、此等者的組合或其類似者。另外，半導體晶圓100可由製造商自第三方製造商接收，或可內部製造。
在一實施例中，第一半導體元件101可包括第一基底103、第一主動元件、第一金屬化層105、第一晶圓接合層109以及第一導電晶圓接合材料107。第一基底103可包括經摻雜或未經 摻雜的塊狀矽，或絕緣層上矽(silicon-on-insulator；SOI)基底的主動層。一般而言，SOI基底包括諸如矽、鍺、矽鍺、SOI、絕緣層上矽鍺(silicon germanium on insulator；SGOI)或其組合的半導體材料的層。可使用的其他基底包含多層基底、梯度基底或混合定向基底。
第一主動元件包括可用於產生針對第一半導體元件101設計的所需結構及功能要求的廣泛多種主動元件及被動元件，諸如電容器、電阻器、電感器以及其類似者。可使用任何合適的方法在第一基底103內或在第一基底103上形成第一主動元件。
第一金屬化層105形成於第一基底103及第一主動元件上方，且經設計以連接各種主動元件以形成功能電路。在一實施例中，第一金屬化層105由交替的介電材料(例如，低k介電材料、極低k介電材料、超低k介電材料、此等者的組合或其類似者)層及導電材料層形成，且可經由任何合適的製程(諸如沉積、鑲嵌、雙鑲嵌等)形成。在一實施例中，可存在與第一基底103間隔至少一個層間介電層(interlayer dielectric layer；ILD)的四個金屬化層，但第一金屬化層105的確切數目取決於第一半導體元件101的設計。
第一晶圓接合層109可形成於第一金屬化層105上方的第一基底103上。第一晶圓接合層109可用於混合接合或熔融接合(亦被稱作氧化物至氧化物接合)。根據一些實施例，第一晶圓接合層109由含矽的介電材料(諸如氧化矽、氮化矽或其類似者)形成。可使用任何合適的方法將第一晶圓接合層109沉積至約1奈米與約1000奈米之間(諸如約5奈米)的厚度，所述方法諸如 原子層沉積(atomic layer deposition；ALD)、CVD、高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition；HDPCVD)、PVD或其類似者。然而，可利用任何合適的材料、製程以及厚度。
一旦已形成第一晶圓接合層109，即可在第一晶圓接合層109內形成接合開口以準備形成第一導電晶圓接合材料107。在一實施例中，接合開口可藉由首先在第一晶圓接合層109的頂部表面上方塗覆且圖案化光阻來形成。所述光阻隨後用於蝕刻第一晶圓接合層109以形成開口。可藉由乾式蝕刻(例如，反應性離子蝕刻(reactive ion etching；RIE)或中性束蝕刻(neutral beam etching；NBE))、濕式蝕刻或其類似者來蝕刻第一晶圓接合層109。根據本揭露的一些實施例，蝕刻在第一金屬化層105上終止，使得第一金屬化層105經由第一晶圓接合層109中的開口暴露。
一旦已暴露第一金屬化層105，即可與第一金屬化層105實體接觸且電接觸地形成第一導電晶圓接合材料107。在一實施例中，第一導電晶圓接合材料107可包括障壁層、晶種層、填充金屬或其組合(未單獨示出)。舉例而言，障壁層可毯覆式沉積於第一金屬化層105上方。障壁層可包括鈦、氮化鈦、鉭、氮化鉭或其類似者。晶種層可為諸如銅的導電材料，且可取決於所需材料使用諸如濺鍍、蒸鍍或電漿增強型化學氣相沉積(plasma-enhanced chemical vapor deposition；PECVD)或其類似者的製程而毯覆式沉積於障壁層上方。填充金屬可為諸如銅或銅合金的導體，且可經由諸如電鍍或無電鍍覆的鍍覆製程沉積於晶種層上方以填充或過量填充開口。一旦已沉積填充金屬，即可經由諸如化學機械研磨的平 坦化製程自開口外部移除填充金屬、晶種層以及障壁層的多餘材料。然而，雖然描述單一鑲嵌製程，但亦可利用諸如雙鑲嵌製程的任何合適方法。
然而，其中形成第一晶圓接合層109、對第一晶圓接合層109進行圖案化且在平坦化之前將第一導電晶圓接合材料107鍍覆至開口中的上述實施例意欲為說明性的且並不意欲限制實施例。實情為，可利用形成第一晶圓接合層109及第一導電晶圓接合材料107的任何合適方法。在其他實施例中，可首先使用例如微影圖案化及鍍覆製程來形成第一導電晶圓接合材料107，且隨後使用介電材料對第一導電晶圓接合材料107周圍的區域進行間隙填充，之後使用平坦化製程進行平坦化。任何此類製造製程全部意欲包含於實施例的範疇內。
另外，在製造製程中的任何所需時點，基底穿孔111可形成於第一基底103及(視需要)第一金屬化層105的一或多個層內，以提供自第一基底的103正面至第一基底103的背面的電連接。在一實施例中，可藉由首先形成至第一基底103及(視需要)上覆第一金屬化層105中之任一者(例如，在已形成所需第一金屬化層105之後，但在形成下一上覆第一金屬化層105之前)中的矽穿孔(through silicon via；TSV)開口而形成TSV 111。TSV開口可藉由塗覆及顯影合適光阻且移除暴露於所需深度的下層材料的部分而形成。TSV開口可經形成為以一深度延伸至第一基底103中，該深度大於第一基底103的最終所需高度。因此，雖然深度取決於總體設計，但深度可在約20微米與約200微米之間，諸如約50微米的深度。
一旦已在第一基底103及/或任何第一金屬化層105內形成TSV開口，即可用襯層給TSV開口加襯。襯層可為例如由正矽酸四乙酯(TEOS)或氮化矽形成的氧化物，但可使用任何合適的介電材料。襯層可使用電漿增強型化學氣相沉積(PECVD)製程形成，但可使用其他合適的製程，諸如物理氣相沉積或熱製程。此外，襯層可形成為約0.1微米與約5微米之間(諸如約1微米)的厚度。
一旦已沿TSV開口的側壁及底部形成襯層，即可形成障壁層且可用第一導電材料填充TSV開口的剩餘部分。第一導電材料可包括銅，但可利用其他合適的材料，諸如鋁、合金、摻雜多晶矽、其組合以及其類似者。第一導電材料可藉由將銅電鍍至晶種層上、填充以及過量填充TSV開口而形成。一旦已填充TSV開口，即可經由諸如化學機械研磨(chemical mechanical polishing；CMP)的平坦化製程來移除TSV開口外部的多餘襯層、障壁層、晶種層以及第一導電材料，但亦可使用任何合適的移除製程。
另外，在第一半導體元件101中的不同者之間形成切割區102。在一實施例中，切割區102可為一區，可經由所述區執行單體化以分離第一半導體元件101中的第一者與第一半導體元件101中的第二者。儘管切割區102可藉由簡單地不形成將在第一半導體元件101的操作期間利用的任何結構而形成，但諸如測試結構的一些結構可在切割區102內形成。
圖1另外示出第二半導體元件113及第三半導體元件115與第一導電晶圓接合材料107及第一晶圓接合層109的接合。在一實施例中，第二半導體元件113及第三半導體元件115中的每 一者可各自為既定與第一半導體元件101(例如，寬I/O DRAM元件)一起工作的系統晶片元件，諸如邏輯元件。然而，可利用任何合適的功能性，諸如邏輯晶粒、中央處理單元(CPU)晶粒、輸入/輸出晶粒、此等者的組合或其類似者。
在一實施例中，第二半導體元件113及第三半導體元件115可各自具有第二基底117、第二主動元件、第二金屬化層119、第二晶圓接合層121以及第二導電晶圓接合材料123。在一實施例中，第二基底117、第二主動元件、第二金屬化層119、第二晶圓接合層121以及第二導電晶圓接合材料123可與上文關於圖1所描述的第一基底103、第一主動元件、第一金屬化層105、第一晶圓接合層109以及第一導電晶圓接合材料107類似地形成。然而，在其他實施例中，可使用不同製程及不同材料形成此等結構。
一旦已製備第二半導體元件113及第三半導體元件115，即使用例如混合接合來將第二半導體元件113及第三半導體元件115接合至第一半導體元件101。在一實施例中，可首先活化第一半導體元件101(例如，第一晶圓接合層109及第一導電晶圓接合材料107)的表面以及第二半導體元件113及第三半導體元件115(例如，第二晶圓接合層121及第二導電晶圓接合材料123)的表面。活化第一半導體元件101、第二半導體元件113以及第三半導體元件115的頂部表面可包括例如乾式處理、濕式處理、電漿處理、暴露於惰性氣體電漿、暴露於H2、暴露於N2、暴露於O2或其組合。在使用濕式處理的實施例中，例如可使用RCA清潔。在另一實施例中，活化製程可包括其他類型的處理。活化製程輔助第一半導體元件101、第二半導體元件113以及第三半導體元件115 的混合接合。
在活化製程之後，可將第二半導體元件113及第三半導體元件115放置成與第一半導體元件101接觸。在利用混合接合的特定實施例中，將第一導電晶圓接合材料107放置成與第二導電晶圓接合材料123實體接觸，同時將第一晶圓接合層109放置成與第二晶圓接合層121實體接觸。在活化製程對表面進行化學改性的情況下，材料之間的接合製程在實體接觸後開始。
一旦實體接觸已使得接合製程開始，即可藉由使整體構件經受熱處理來加強接合。在一實施例中，第一半導體元件101、第二半導體元件113以及第三半導體元件115可經受約200℃與約400℃之間的溫度以加強第一晶圓接合層109與第二晶圓接合層121之間的接合。第一半導體元件101、第二半導體元件113以及第三半導體元件115隨後可經受處於或高於第一導電晶圓接合材料107及第二導電晶圓接合材料123的材料的共熔點的溫度。以此方式，第一半導體元件101、第二半導體元件113以及第三半導體元件115的熔融形成混合接合的元件。
另外，雖然已描述用以起始及加強第一半導體元件101、第二半導體元件113與第三半導體元件115之間的混合接合的具體製程，但此等描述意欲為說明性的且並不意欲限制實施例。實情為，可利用烘烤、退火、按壓或其他接合製程或製程組合的任何合適組合。所有此類製程全部意欲包含於實施例的範疇內。
再者，雖然將混合接合描述為將第一半導體元件101接合至第二半導體元件113及第三半導體元件115的一種方法，但此同樣僅意欲為說明性的且並不意欲限制實施例。實情為，亦可利 用任何合適的接合方法，諸如熔融接合、銅至銅接合或其類似者，或甚至使用例如球柵陣列封裝的焊料接合。可利用將第一半導體元件101接合至第二半導體元件113及第三半導體元件115的任何合適方法。
圖2示出第一開口201的形成，所述第一開口201預切割成位於第一半導體元件101之間的切割區102。第一開口201用於移除來自第一金屬化層105及在諸如鋸切製程(下文將進一步描述)的後續分離製程期間可能更易於分層的其他層的材料(例如，來自第一金屬化層105的極低k材料)。藉由在製程中此時以受控方式移除切割區102內的此等材料且使此等材料凹進，在隨後的單體化製程期間不會觸碰到此等材料，且可減少由分層造成的損壞。
在一實施例中，可使用雷射消熔製程(在圖2中藉由標記為203的虛線圓柱體表示)形成第一開口201。舉例而言，將雷射導向第一金屬化層105的需要移除的彼等部分。在雷射鑽孔製程期間，相對於第一金屬化層105的法線的鑽孔角度為約0度(垂直於第一金屬化層105)至約30度。然而，可利用用於雷射消熔製程203的任何合適參數。
藉由利用雷射消熔製程203，可將第一開口201形成為具有約11微米與約20微米之間(諸如約15微米)的第一深度D1。因而，第一開口201將以約3微米與約8微米之間(諸如約5微米)的第二深度D2延伸至第一基底103中。另外，第一開口201可形成為具有約50微米與約80微米之間(諸如約60微米)的第一寬度W1。然而，可利用任何合適的尺寸。
另外，藉由利用雷射消熔製程203，第一開口201的形狀將不規則。舉例而言，由雷射消熔製程203形成的第一開口201可具有大致的圓形形狀而非筆直的側壁。此外，雷射消熔製程203的引入將導致材料的不均勻移除，使得在第一基底103的材料內存在凹痕。
然而，雖然將雷射消熔製程203描述為用於形成第一開口201的一個可能實施例，但雷射消熔製程203的描述意欲為說明性的且並不意欲為限制性的。實情為，亦可利用可移除所需材料的任何合適製程，諸如可產生筆直側壁的微影遮蔽及蝕刻製程。所有此類製程全部意欲包含於實施例的範疇內。
圖3示出一旦已形成第一開口201，即可用第一包封體301來包封第二半導體元件113、第三半導體元件115以及第一半導體元件101。在一實施例中，包封可在模製元件中執行，所述模製元件可包括頂部模製部分及可與頂部模製部分分離的底部模製部分。在頂部模製部分下降至鄰近於底部模製部分時，可形成用於第一半導體元件101、第二半導體元件113以及第三半導體元件115的模製空腔。
在包封製程期間，可將頂部模製部分放置成鄰近於底部模製部分，從而將第一半導體元件101、第二半導體元件113以及第三半導體元件115圍封在模製空腔內。一旦圍封，頂部模製部分及底部模製部分即可形成氣密密封，以控制氣體自模製空腔的流入及流出。一旦密封，即可將第一包封體301放置於模製空腔內。
第一包封體301可為環氧樹脂或模製化合物樹脂，諸如 聚醯亞胺、聚苯硫醚(polyphenylene sulfide；PPS)、聚醚醚酮(polyetheretherketone；PEEK)、聚醚碸(poly ether sulphone；PES)、耐熱結晶性樹脂、此等者的組合或其類似者。第一包封體301可在對準頂部模製部分與底部模製部分之前放置於模製空腔內，或可使用壓縮模製、轉移模製或其類似者經由注入埠注入至模製空腔中。
一旦第一包封體301已放置於模製空腔中使得第一包封體301包封第一半導體元件101、第二半導體元件113以及第三半導體元件115，即可固化第一包封體301以使第一包封體301硬化以用於最佳保護。雖然確切的固化製程至少部分地取決於針對第一包封體301所選擇的特定材料，但在選擇模製化合物作為第一包封體301的一實施例中，固化可經由諸如將第一包封體301加熱至約100℃至約200℃(諸如約125℃)持續約60秒至約3000秒(諸如約600秒)的製程而發生。另外，起始劑及/或催化劑可包含於第一包封體301內以更好地控制固化製程。
然而，如所屬領域中具通常知識者將認識到，上文所描述的固化製程僅為例示性的製程，且不意謂限制當前實施例。亦可使用其他固化製程，諸如輻照或甚至允許第一包封體301在環境溫度下硬化。可使用任何合適的固化製程，且所有此類製程全部意欲包含於本文中所論述的實施例的範疇內。
圖3進一步示出對第一包封體301進行薄化以暴露第二半導體元件113及第三半導體元件115以供進一步處理。薄化可例如使用機械磨削、化學方法或化學機械研磨(CMP)製程來執行，由此利用化學蝕刻劑及研磨劑來反應且磨削掉第一包封體 301，從而使得第二半導體元件113及第三半導體元件115暴露，且第一包封體301具有約100微米與約150微米之間的厚度。因而，第二半導體元件113及第三半導體元件115可具有亦與第一包封體301共面的平面表面。在另一實施例中，可省略磨削。舉例而言，若在包封之後第二半導體元件113及第三半導體元件115已暴露，則可省略磨削。
此外，雖然上文所描述的CMP製程呈現為一個說明性實施例，但其不意欲限制所述實施例。任何其他適合的移除製程可用於薄化第一包封體301。舉例而言，可利用一系列化學蝕刻。此製程及任何其他合適的製程可用於使第一包封體301平坦化，且此類製程全部意欲包含於實施例的範疇內。
圖4示出放置第一載體基底401且薄化第一基底103的背面以暴露TSV 111。在一實施例中，第一載體基底401包括例如矽類材料(諸如玻璃或氧化矽)或其他材料(諸如氧化鋁)、此等材料中的任一者的組合或其類似者。第一載體基底401為平面的，以適於第二半導體元件113與第三半導體元件115的附接，所述附接可經由接合製程或經由使用黏著層(未單獨示出)進行。
一旦附接，即可薄化第一基底103的第二側以暴露TSV 111。在一實施例中，薄化第一基底103的第二側可使得TSV 111暴露。第一基底103的第二側的薄化可藉由諸如CMP或蝕刻的平坦化製程執行。然而，可利用薄化第一基底103的第二側的任何合適方法。
圖5示出重佈線結構501的形成，所述重佈線結構501具有位於第一基底103的第二側上方且與TSV 111連接的一或多 個層。在一實施例中，重佈線結構501可藉由首先形成位於TSV 111上方且與TSV 111電連接的第一重佈線層503而形成。在一實施例中，第一重佈線層503可藉由首先經由諸如CVD或濺鍍的合適形成製程來形成鈦銅合金的晶種層(未繪示)而形成。可隨後形成光阻(亦未繪示)以覆蓋晶種層，且可隨後對光阻進行圖案化以暴露晶種層位於需要安置第一重佈線層503的位置處的彼等部分。
一旦已形成且圖案化光阻，即可經由諸如鍍覆的沉積製程在晶種層上形成諸如銅的導電材料。導電材料可形成為具有約1微米與約10微米之間(諸如約4微米)的厚度。然而，雖然所論述的材料及方法適合於形成導電材料，但此等材料僅為例示性的。可使用任何其他適合的材料(諸如AlCu或Au)及任何其他適合的形成製程(諸如CVD或PVD)來形成第一重佈線層503。
一旦已形成導電材料，即可經由諸如化學剝離及/或灰化的合適移除製程來移除光阻。另外，在移除光阻之後，晶種層被光阻覆蓋的彼等部分可經由例如使用導電材料作為罩幕的合適蝕刻製程移除。
一旦已形成第一重佈線層503，即可形成重佈線鈍化層505。在一實施例中，儘管重佈線鈍化層505可為聚苯并噁唑(PBO)，但可替代地利用任何合適的材料，諸如聚醯亞胺或聚醯亞胺衍生物，諸如低溫固化的聚醯亞胺。儘管可使用例如旋轉塗佈製程將第一重佈線鈍化層505放置為約5微米與約17微米之間(諸如約7微米)的厚度，但可使用任何合適的方法及厚度。
一旦已形成重佈線鈍化層505，即可圖案化重佈線鈍化層505以允許與下層第一重佈線層503電接觸。在一實施例中，可使 用例如微影遮蔽及蝕刻製程來圖案化重佈線鈍化層505。然而，任何合適的製程可用於暴露下層第一重佈線層503。
另外，視需要可形成第一重佈線層503及重佈線鈍化層505的額外層以提供額外的互連選擇。特定言之，可使用本文所描述的製程及材料來形成任何合適數目個導電及介電層。所有此類層全部意欲包含於實施例的範疇內。
一旦已形成且圖案化重佈線鈍化層505，即可形成第一外部連接件507。在一實施例中，第一外部連接件507可為導電柱，諸如銅柱。在一實施例中，導電柱可藉由首先形成晶種層且隨後塗覆並圖案化光阻來形成，其中光阻的開口暴露需要安置導電柱的位置處的晶種層。可隨後使用諸如電鍍、無電鍍覆或其類似者的製程在光阻內形成諸如銅、鎢、其他導電金屬或其類似者的導電材料。一旦形成，即移除光阻且使用導電材料作為罩幕來圖案化晶種層。
視情況，可視需要用焊接材料(未單獨示出)覆蓋第一外部連接件507。在此類實施例中，焊料凸塊可藉由首先經由諸如蒸鍍、電鍍、印刷、焊料轉移的任何合適方法形成錫層而形成以放置覆蓋物的材料。一旦處於適當位置，即可執行回焊以使材料成形為所需的凸塊形狀。
一旦已形成第一外部連接件507，即形成第一鈍化層509以保護第一外部連接件507。在一實施例中，儘管第一鈍化層509可由諸如氧化矽、氮化矽或聚苯并噁唑(PBO)的一或多種合適的介電材料形成，但亦可由諸如聚醯亞胺或聚醯亞胺衍生物(諸如低溫固化的聚醯亞胺)、此等者的組合或其類似者的任何合適材料形 成。可使用諸如CVD、PVD、ALD、此等者的組合或其類似者的製程來形成第一鈍化層509。然而，可利用任何合適的材料及製程。
然而，其中形成第一外部連接件507、對第一外部連接件507進行圖案化且在平坦化之前放置第一鈍化層509的上述實施例意欲為說明性的且並不意欲限制實施例。實際上，可利用形成第一外部連接件507及第一鈍化層509的任何合適方法。在其他實施例中，可首先形成第一鈍化層509且隨後使用例如微影圖案化製程對第一鈍化層509進行圖案化，且隨後將第一外部連接件507鍍覆在第一鈍化層509內，之後使用平坦化製程進行平坦化。任何此類製造製程全部意欲包含於實施例的範疇內。
圖5亦示出在準備單體化製程時第一載體基底401的移除。在一實施例中，第一載體基底401可藉由如下方式移除：在黏著層處引入能量，從而減小其黏著力且允許移除黏著層及第一載體基底401兩者。
圖6示出一旦已移除第一載體基底401，即經由第一開口201(且因此經由位於第一開口201內的第一包封體301)將結構單體化以形成經單體化的半導體元件600，諸如積體電路上系統。在準備單體化製程時，將第一包封體301、第二半導體元件113以及第三半導體元件115放置於諸如膜框架601的支撐結構上。然而，可利用任何合適的支撐結構。
一旦在膜框架601上處於適當位置，即可藉由使用鋸刀(在圖6中藉由虛線框603表示)執行單體化以割開第一半導體元件101之間的第一包封體301，從而分離第一半導體元件101(其中第二半導體元件113及第三半導體元件115中的每一者與其接 合)中的一者與第一半導體元件101中的另一者。
然而，由於來自第一金屬化層105的一些材料已移除且自鋸刀603的路徑凹進，且剩餘的材料已經由放置第一包封體301而加強，因此在單體化製程期間出現更小損壞。舉例而言，當鋸刀603割開半導體晶圓100時出現的應力不會直接轉移至存在於第一金屬化層105內的易碎極低k材料，簡言之，這是因為鋸刀603不會觸碰到易碎極低k材料。此外，藉由在鋸刀603與易碎材料之間放置第一包封體301，第一包封體301可充當緩衝件以有助於保護材料。此全部有助於防止損壞在單體化製程期間發生諸如分層的損壞。
藉由形成第一開口201，用第一包封體301填充第一開口201，且隨後經由第一包封體301單體化，當第一包封體301進一步伸展至第一基底103中時，第一包封體301將具有減小的寬度。舉例而言，在單體化之後，第一包封體301具有約3微米與約10微米之間(諸如約5微米)的鄰近於第一金屬化層105的第二寬度W2，同時亦具有約2微米與約8微米之間(諸如約4微米)的鄰近於第一基底103的頂部表面的第三寬度W3。然而，可利用任何合適的尺寸。
圖7示出一旦已形成經單體化的半導體元件600，即可將經單體化的半導體元件600併入積體扇出製程中以整合經單體化的半導體元件600與其他元件。在一實施例中，積體扇出製程可利用第二載體基底(圖7中未示出)、第二黏著層(圖7中亦未示出)、聚合物層705、第二重佈線層706以及第二積體扇出型穿孔(through integrated fan out via；TIV)708。在一實施例中，第二載 體基底用作用於製造的初始底部，且包括例如矽類材料(諸如玻璃或氧化矽)、或其他材料(諸如氧化鋁)、此等材料中的任一者的組合或其類似者。第二載體基底為平面的，以適於諸如經單體化的半導體元件600的元件的附接。
第二黏著層可放置在第二載體基底上方以輔助上覆結構與第二載體基底的附接。在一實施例中，第二黏著層為晶粒貼合膜(die attached film；DAF)，諸如環氧樹脂、苯酚樹脂、丙烯酸橡膠、二氧化矽填充劑或其組合，且使用層壓技術塗覆。然而，可利用任何其他合適的材料及形成方法。
聚合物層705首先形成於第二黏著層上方。在一實施例中，聚合物層705可由一或多種合適的介電材料形成，所述介電材料諸如氧化矽、氮化矽、低k介電質(諸如摻碳氧化物)、極低k介電質(諸如多孔摻碳二氧化矽)、此等者的組合或其類似物。儘管聚合物層705可經由諸如化學氣相沉積(chemical vapor deposition；CVD)的製程形成，但可利用任何合適的製程，且聚合物層705可具有約0.5微米與約5微米之間的厚度。
一旦已形成聚合物層705，即可在聚合物層705上方形成凸塊下金屬化層及第二重佈線層706。在一實施例中，凸塊下金屬化層可包括三個導電材料層，諸如鈦層、銅層以及鎳層。然而，所屬領域中具通常知識者將認識到，存在適用於形成凸塊下金屬化層的許多合適的材料及層配置，諸如鉻/鉻銅合金/銅/金配置、鈦/鈦鎢/銅配置或銅/鎳/金配置。可用於凸塊下金屬化層的任何合適的材料或材料層全部意欲包含於實施例的範疇內。
在一實施例中，凸塊下金屬化層藉由在聚合物層705上 方形成每一層而產生。儘管可使用諸如電化學鍍覆的鍍覆製程來執行每一層的形成，但取決於所需材料，可替代地使用其他形成製程，諸如濺鍍、蒸鍍或PECVD製程。凸塊下金屬化層可形成為具有約0.7微米與約10微米之間(諸如約5微米)的厚度。
在一實施例中，第二重佈線層706包括嵌在一系列介電層內的一系列導電層。在一實施例中，所述系列介電層中的第一者形成於聚合物層705上方，且儘管所述系列介電層中的第一者可為諸如聚苯并噁唑(PBO)的材料，但可利用任何合適的材料，諸如聚醯亞胺或聚醯亞胺衍生物。儘管所述系列介電層中的第一者可使用例如旋轉塗佈製程放置，但可使用任何合適的方法。
在已形成所述系列介電層中的第一者之後，可藉由移除所述系列介電層中的第一者的部分而形成穿過所述系列介電層中的第一者的開口。儘管開口可使用合適的微影遮蔽及蝕刻製程形成，但任何合適的一或多個製程可用於圖案化所述系列介電層中的第一者。
一旦已形成且圖案化所述系列介電層中的第一者，即在所述系列介電層中的第一者上方且穿過形成於所述系列介電層中的第一者內的開口形成所述系列導電層中的第一者。在一實施例中，所述系列導電層中的第一者可藉由首先經由諸如CVD或濺鍍的合適形成製程形成鈦銅合金的晶種層(未繪示)而形成。可隨後形成光阻(亦未繪示)以覆蓋晶種層，且可隨後對光阻進行圖案化以暴露晶種層位於需要安置所述系列導電層中的第一者的位置處的彼等部分。
一旦已形成且圖案化光阻，即可經由諸如鍍覆的沉積製 程在晶種層上形成諸如銅的導電材料。導電材料可形成為具有約1微米與約10微米之間(諸如約5微米)的厚度。然而，雖然所論述的材料及方法適合於形成導電材料，但此等材料僅為例示性的。諸如AlCu或Au的任何其他合適材料及諸如CVD或PVD的任何其他合適形成製程可用於形成所述系列導電層中的第一者。一旦已形成導電材料，即可經由諸如灰化的合適移除製程來移除光阻。另外，在移除光阻之後，晶種層被光阻覆蓋的彼等部分可經由例如使用導電材料作為罩幕的合適蝕刻製程移除。
一旦已形成所述系列導電層中的第一者，即可藉由與所述系列介電層中的第一者及所述系列導電層中的第一者類似的重複步驟形成所述系列介電層中的第二者及所述系列導電層中的第二者。此等步驟可視需要重複以將所述系列導電層中的每一者電連接至所述系列導電層中的下層者，且可在每當需要時重複，直至已形成所述系列導電層中的最上層及所述系列介電層中的最上層。在一實施例中，儘管所述系列導電層及所述系列介電層的沉積及圖案化可繼續，直至第二重佈線層706具有所需數目個層，但可利用任何合適數目個個別層。
一旦已在第二載體基底上方形成第二重佈線層706，即形成與第二重佈線層706電連接的第二TIV 708。在一實施例中，第二TIV 708可藉由首先形成晶種層(未單獨示出)而形成。在一實施例中，晶種層為在後續處理步驟期間輔助形成較厚層的較薄導電材料層。晶種層可包括約1,000埃厚的鈦層及之後的約5,000埃厚的銅層。取決於所需材料，可使用諸如濺鍍、蒸鍍或PECVD製程的製程來產生晶種層。晶種層可形成為具有約0.3微米與約1微 米之間(諸如約0.5微米)的厚度。
一旦已形成晶種層，即將光阻(亦未示出)放置於晶種層上方。在一實施例中，可使用例如旋轉塗佈技術將光阻放置於晶種層上至約50微米與約250微米之間(諸如約120微米)的高度。一旦處於適當位置，即可隨後可藉由以下方式來圖案化光阻：將光阻暴露於經圖案化能量源(例如，經圖案化光源)以誘發化學反應，從而誘發光阻暴露於經圖案化光源的彼等部分的物理變化。隨後將顯影劑塗覆至經暴露的光阻以利用所述物理變化，且取決於所要圖案而選擇性地移除光阻的暴露部分或光阻的未暴露部分。在一實施例中，形成於光阻中的圖案為用於第二TIV 708的圖案。第二TIV 708以位於隨後附接元件的不同側的佈置形成。然而，可利用第二TIV 708的圖案的任何合適配置。
在一實施例中，第二TIV 708由一或多種導電材料形成於光阻內，所述一或多種導電材料諸如銅、鎢、其他導電金屬或其類似者，且第二TIV 708可例如藉由電鍍、無電鍍覆或其類似者形成。舉例而言，使用電鍍製程，其中將晶種層及光阻浸沒或浸入電鍍溶液中。將晶種層表面電連接至外部DC電源的負極側，使得晶種層在電鍍製程中充當陰極。諸如銅陽極的固體導電陽極亦浸入溶液中，且附接至電源的正極側。來自陽極的原子溶解於溶液中，例如晶種層的陰極自所述溶液獲取溶解的原子，從而鍍覆光阻的開口內的晶種層的經暴露導電區域。
一旦已使用光阻及晶種層形成第二TIV 708，即可使用合適的移除製程移除光阻。在一實施例中，電漿灰化製程可用於移除光阻，藉此光阻的溫度可升高，直至光阻經歷熱分解且可移除。然 而，可利用任何其他合適的製程，諸如濕式剝離。光阻的移除可暴露晶種層的下層部分。
一旦暴露，即可執行晶種層的經暴露部分的移除。在一實施例中，可藉由例如濕式或乾式蝕刻製程來移除晶種層的經暴露部分(例如，未被第二TIV 708覆蓋的彼等部分)。舉例而言，在乾式蝕刻製程中，可使用第二TIV 708作為罩幕將反應劑導向晶種層。在另一實施例中，蝕刻劑可經噴塗或以其他方式與晶種層接觸，以移除晶種層的經暴露部分。在已蝕刻掉晶種層的經暴露部分之後，在第二TIV 708之間暴露第二重佈線層706的一部分。
一旦已形成第二TIV 708，即可將經單體化的半導體元件600放置於第二重佈線層706上。在一實施例中，可使用例如取放製程來放置經單體化的半導體元件600。然而，可使用放置經單體化的半導體元件600的任何其他方法。
圖7另外示出一旦已放置經單體化的半導體元件600，即可用第二包封體712包封經單體化的半導體元件600及第二TIV 708。在一實施例中，可使用與如上文關於圖3所描述的第二半導體元件113及第三半導體元件115的包封類似的製程來包封經單體化的半導體元件600及第二TIV 708。一旦經包封，即可使經單體化的半導體元件600及第二TIV 708以及第二包封體712平坦化以暴露經單體化的半導體元件600及第二TIV 708。
圖7亦示出一旦包封經單體化的半導體元件600及第二TIV 708，即形成第三重佈線層701以將經單體化的半導體元件600與第二TIV 708互連。在一實施例中，可與形成第二重佈線層706(上文關於圖7所描述)類似地形成第三重佈線層701。舉例而言， 沉積一系列鈍化層及導電層且對其進行平坦化以形成一或多個導電佈線層。然而，可利用任何合適的方法及材料。
在一特定實施例中，可形成三個導電層。然而，三個導電層的使用意欲為說明性的且並不意欲為限制性的。實際上，可利用任何合適數目個導電層及鈍化層，且所有此類層數目全部意欲包含於實施例的範疇內。
圖7進一步示出形成第三外部連接件703以與第三重佈線層701進行電接觸。在一實施例中，第三外部連接件703可放置於第三重佈線層701上，且可為包括共熔材料(諸如焊料)的球柵陣列封裝(ball grid array；BGA)，但亦可使用任何合適的材料。視情況，可在第三外部連接件703與第三重佈線層701之間利用凸塊下金屬化。在第三外部連接件703為焊料凸塊的實施例中，第三外部連接件703可使用諸如直接落球製程的落球方法來形成。在另一實施例中，焊料凸塊可藉由以下方式形成：首先經由諸如蒸鍍、電鍍、印刷、焊料轉移的任何合適方法形成錫層，且隨後執行回焊以使材料成形為所需的凸塊形狀。一旦已形成第三外部連接件703，即可執行測試以確保結構適合於進一步處理。
在測試之後，可自經單體化的半導體元件600剝離第二載體基底。在一實施例中，可將第三外部連接件703且因此將包含經單體化的半導體元件600的結構附接至環結構(未在圖7中示出)。所述環結構可為意欲在剝離製程期間及之後為結構提供支撐及穩定性的金屬環。在一實施例中，儘管第三外部連接件703使用例如紫外線膠帶附接至環結構，但可使用任何其他合適的黏著劑或附接物。一旦附接，即可輻照第二黏著層，且可以物理方式移 除第二黏著層及第二載體基底。
一旦已移除第二載體基底且已暴露聚合物層705，即可使用例如雷射鑽孔方法來圖案化聚合物層705，藉由所述雷射鑽孔方法將雷射導向聚合物層705需要移除的彼等部分以暴露下方第二重佈線層706。在雷射鑽孔製程期間，鑽孔能量可在0.1毫焦至約60毫焦的範圍內，且相對於聚合物層705的法線的鑽孔角度為約0度(垂直於聚合物層705)至約85度。
圖7另外示出第四外部連接件707的放置。在一實施例中，第四外部連接件707可為諸如微凸塊或受控塌陷晶片連接(controlled collapse chip connection；C4)凸塊的接觸凸塊，且可包括諸如錫的材料或諸如焊料膏、銀或銅的其他合適材料。在第四外部連接件707為錫焊料凸塊的實施例中，第四外部連接件707可藉由首先經由諸如蒸鍍、電鍍、印刷、焊料轉移、植球等任何合適的方法形成錫層至例如約100微米的厚度而形成。一旦已在結構上形成錫層，即執行回焊以將材料成形為所要凸塊形狀。
圖7另外示出第四外部連接件707與第一封裝710的接合。在一實施例中，第一封裝710可包括第三基底709、第五半導體元件711、第六半導體元件713(接合至第五半導體元件711)、第三接觸焊墊715(用於電連接至第四外部連接件707)以及第三包封體717。在一實施例中，第三基底709可為例如封裝基底，所述封裝基底包括用以將第五半導體元件711及第六半導體元件713連接至第四外部連接件707的內部互連件(例如，基底穿孔)。
在另一實施例中，第三基底709可為用作中間基底以將第五半導體元件711及第六半導體元件713連接至第四外部連接 件707的插入件。在此實施例中，第三基底709可為例如經摻雜或未經摻雜的矽基底，或絕緣層上矽(SOI)基底的主動層。然而，第三基底709亦可為玻璃基底、陶瓷基底、聚合物基底或可提供合適保護及/或互連功能性的任何其他基底。此等及任何其他合適的材料可用於第三基底709。
第五半導體元件711可為經設計用於既定目的的半導體元件，諸如為邏輯晶粒、中央處理單元(CPU)晶粒、記憶體晶粒(例如，DRAM晶粒)、此等者的組合或其類似者。在一實施例中，第五半導體元件711在其中包括積體電路元件，諸如電晶體、電容器、電感器、電阻器、第一金屬化層(未繪示)以及其類似者，以視需要用於特定功能性。在一實施例中，第五半導體元件711經設計及製造以與經單體化的半導體元件600結合或並行地起作用。
第六半導體元件713可類似於第五半導體元件711。舉例而言，第六半導體元件713可為經設計用於既定目的(例如，DRAM晶粒)且包括用於所需功能性的積體電路元件的半導體元件。在一實施例中，第六半導體元件713經設計以與經單體化的半導體元件600及/或第五半導體元件711結合或並行地起作用。
可將第六半導體元件713接合至第五半導體元件711。在一實施例中，第六半導體元件713僅諸如藉由使用黏著劑而與第五半導體元件711實體接合。在此實施例中，可使用例如線接合件719將第六半導體元件713及第五半導體元件711電連接至第三基底709，但可利用任何合適的電接合。
在另一實施例中，可將第六半導體元件713實體接合且電接合至第五半導體元件711。在此實施例中，第六半導體元件713 可包括第四外部連接件(未單獨在圖7中示出)，所述第四外部連接件與第五半導體元件711上的第五外部連接件(亦未單獨在圖7中示出)連接，以將第六半導體元件713與第五半導體元件711互連。
第三接觸焊墊715可形成於第三基底709上以在第五半導體元件711與例如第四外部連接件707之間形成電連接。在一實施例中，第三接觸焊墊715可形成於第三基底709內的電佈線(諸如基底穿孔)上方且與所述電佈線電接觸。第三接觸焊墊715可包括鋁，但亦可使用其他材料，諸如銅。第三接觸焊墊715可使用諸如濺鍍的沉積製程形成以形成材料層(未繪示)，且材料層的部分可隨後經由合適的製程(諸如微影遮蔽及蝕刻)移除以形成第三接觸焊墊715。然而，任何其他合適的製程可用於形成第三接觸焊墊715。第三接觸焊墊715可形成為具有約0.5微米與約4微米之間(諸如約1.45微米)的厚度。
第三包封體717可用於包封及保護第五半導體元件711、第六半導體元件713以及第三基底709。在一實施例中，第三包封體717可為模製化合物且可使用模製元件(未在圖7中示出)來放置。舉例而言，可將第三基底709、第五半導體元件711以及第六半導體元件713放置於模製元件的空腔內，且可將空腔氣密密封。第三包封體717可在將空腔氣密密封之前放置於空腔內，或可經由注入埠注入空腔中。在一實施例中，第三包封體717可為模製化合物樹脂，諸如聚醯亞胺、PPS、PEEK、PES、耐熱結晶性樹脂、此等者的組合或其類似者。
一旦第三包封體717已放置於空腔中使得第三包封體717包封第三基底709、第五半導體元件711以及第六半導體元件 713周圍的區域，即可固化第三包封體717以使第三包封體717硬化以用於最佳保護。雖然確切的固化製程至少部分地取決於針對第三包封體717選擇的特定材料，但在選擇模製化合物作為第三包封體717的實施例中，固化可經由諸如將第三包封體717加熱至約100℃至約130℃(諸如約125℃)持續約60秒至約3000秒(諸如約600秒)的製程而發生。另外，起始劑及/或催化劑可包含於第三包封體717內以更好地控制固化製程。
然而，如所屬領域中具通常知識者將認識到，上文所描述的固化製程僅為例示性的製程，且不意謂限制當前實施例。可使用其他固化製程，諸如輻照或甚至允許第三包封體717在環境溫度下硬化。可使用任何合適的固化製程，且所有此類製程全部意欲包含於本文中所論述的實施例的範疇內。
一旦已形成第四外部連接件707，第四外部連接件707即與第三接觸焊墊715對準且經放置為與其實體接觸，且執行接合。舉例而言，在第四外部連接件707為焊料凸塊的實施例中，接合製程可包括回焊製程，藉此使第四外部連接件707的溫度升高至第四外部連接件707將液化且流動的點，從而一旦第四外部連接件707重新凝固，即將第一封裝710接合至第四外部連接件707。
圖7亦示出底填充材料721在第一封裝710與聚合物層705之間的放置。在一實施例中，底填充材料721為用於緩衝且支撐第一封裝710以免於操作及環境劣化(諸如由在操作期間的熱量的產生所導致的應力)的保護材料。底填充材料721可注入或以其他方式形成於第一封裝710與聚合物層705之間的空間中，且可例如包括施配在第一封裝710與聚合物層705之間且隨後經 固化以硬化的液體環氧樹脂。
圖7另外示出單體化。在一實施例中，單體化可藉由使用鋸刀(未單獨示出)割開底填充材料721及第二包封體712來執行。然而，如所屬領域中具通常知識者將認識到，利用鋸刀以用於單體化僅為一個說明性實施例且並不意欲為限制性的。可利用用於執行單體化的任何方法，諸如利用一或多個蝕刻。此等方法及任何其他合適的方法可用於將結構單體化。
藉由在單體化之前移除切割區102的一部分，可在損壞(諸如極低k介電材料的分層)的可能性降低的情況下製造經單體化的半導體元件600。藉由降低損壞的可能性，在製造製程期間可獲得較大良率，且可製造更可靠的半導體元件。
圖8示出在第一包封體301為諸如間隙填充材料801的較軟材料(而非諸如模製化合物的材料)的實施例中利用支撐結構803來幫助提供支撐的另一實施例。在一實施例中，間隙填充材料801可為使用任何合適的製程沉積在第一包封體301的位置上的非聚合物介電材料，諸如氧化矽、氮化矽、此等者的組合或其類似者。舉例而言，間隙填充材料可由CVD、PECVD或ALD沉積製程、FCVD或旋轉塗佈玻璃製程形成以填充及/或過量填充第二半導體元件113與第三半導體元件115之間的空間且亦填充第一開口201。一旦已沉積間隙填充材料801，即可用第二半導體元件113及第三半導體元件115將間隙填充材料801平坦化至約20微米與約50微米之間的厚度。
然而，在利用較軟材料的實施例中，支撐結構803可用於提供額外支撐以支持間隙填充材料801。因而，圖8亦示出支撐 結構803的放置以幫助支撐元件且補償間隙填充材料801中的不同材料。在一實施例中，支撐結構803可為諸如矽的半導體材料(例如，矽晶圓)。然而，亦可使用諸如玻璃支撐結構或甚至金屬支撐結構的合適支撐材料。
可使用例如接合製程(諸如熔融接合製程)將支撐結構803附接至間隙填充材料801。在其他實施例中，可利用黏著劑或任何其他合適的用於附接支撐結構803與間隙填充材料801的材料或方法來附接支撐結構803。所有此類材料及製程全部意欲包含於實施例的範疇內。
一旦已附接支撐結構803，即可遵循上文關於圖4所描述的製程的其餘步驟。舉例而言，可附接第一載體基底401(在此實施例中附接至支撐結構803)且可薄化第一基底103以暴露TSV 111。然而，可利用任何合適的製程。
圖9示出在支撐結構803仍附接的情況下重佈線結構501、第一外部連接件507以及第一鈍化層509的形成。在一實施例中，可如上文關於圖5所描述形成重佈線結構501、第一外部連接件507以及第一鈍化層509。然而，可利用任何合適的製程及材料。
圖10示出結構及支撐結構803的單體化。在一實施例中，可如上文關於圖6所描述執行單體化。舉例而言，可利用鋸刀切開半導體晶圓100以及間隙填充材料801及支撐結構803，以形成仍與支撐結構803附接的經單體化的半導體元件600。然而，可利用將元件單體化以形成經單體化的半導體元件600的任何合適方法。
另外，在一些實施例中，可使用剝離製程、薄化製程或用於移除支撐結構803的任何其他合適製程來移除支撐結構803。然而，在其他實施例中，支撐結構803可作為經單體化的半導體元件600的部分而留在原位，其中支撐結構803不僅可提供結構性支撐，且亦可用作散熱片以移除在第二半導體元件113及第三半導體元件115的操作期間所產生的熱量。
藉由利用支撐結構803，可利用更寬泛的材料組合來包封第二半導體元件113及第三半導體元件115，以幫助減少在單體化期間由於分層造成的損壞。另外，可藉由使用支撐結構803作為積體散熱片而避免散熱片的後續附接。此情形及來自單體化的損壞的減少有助於增加製造良率且減少操作問題。
圖11示出利用第二開口1101以及第一開口201(參見圖2)來幫助保護結構免於後續單體化製程期間的分層損壞的另一實施例。在此實施例中，如上文關於圖1至圖5所描述形成結構。然而，一旦已形成重佈線結構501、第一外部連接件507以及第一鈍化層509，即在重佈線結構501、第一外部連接件507、第一鈍化層509以及第一基底103內形成第二開口1101，以提供單體化製程(例如，鋸刀)可通過的額外空間。
在一實施例中，可使用第二雷射消熔製程(在圖11中藉由標記為1103的虛線圓柱體表示)來形成第二開口1101。舉例而言，在一些實施例中，將雷射導向第一鈍化層509需要移除的彼等部分。在第二雷射消熔製程1103期間，相對於第一鈍化層509的法線的鑽孔角度為約0度(垂直於第一金屬化層105)至約30度。然而，可利用用於第二雷射消熔製程1103的任何合適參數。
藉由利用第二雷射消熔製程1103，可將第二開口1101形成為具有約20微米與約30微米之間(諸如約25微米)的第三深度D3。因而，第二開口1101將以約3微米與約8微米之間(諸如約5微米)的第四深度D4延伸至第一基底103中。另外，第二開口1101可經形成為具有約50微米與約80微米之間(諸如約60微米)的第四寬度W4。然而，可利用任何合適的尺寸。
另外，藉由利用第二雷射消熔製程1103，第二開口1101的形狀將不規則。舉例而言，由第二雷射消熔製程1103形成的第二開口1101可具有大致圓形的彎曲形狀而非筆直的側壁。此外，第二雷射消熔製程1103的引入將導致材料的不均勻移除，使得在第一基底103的材料內存在凹痕。
然而，雖然將雷射鑽孔製程描述為用於形成第二開口1101的一個可能實施例，但雷射鑽孔製程的描述意欲為說明性的且並不意欲為限制性的。實際上，亦可利用可移除所需材料的任何合適製程，諸如可產生筆直側壁的微影遮蔽及蝕刻製程。所有此類製程全部意欲包含於實施例的範疇內。
圖12示出一旦已形成第二開口1101，即可經由第一開口201及第二開口1101兩者將半導體晶圓100單體化。在一實施例中，可如上文關於圖6所描述執行單體化。舉例而言，可使用鋸刀603經由第二開口1101及第一開口201兩者切開半導體晶圓100。然而，可利用任何合適的單體化製程。
圖13示出第二開口1101亦經填充而非僅形成以在單體化製程期間提供額外結構性支撐的又一實施例。在一實施例中，可用第四包封體1301填充第二開口1101。此外，第四包封體1301 可為與上文關於圖3所描述的第一包封體301或上文關於圖8所描述的間隙填充材料801類似的材料且使用與其類似的方法形成。舉例而言，第四包封體1301可為模製化合物材料或間隙填充材料，且可使用模製製程或沉積製程塗覆以填充及/或過量填充第二開口1101。一旦處於適當位置，即可視需要使用諸如化學機械研磨的製程對第四包封體1301進行平坦化以將第四包封體1301嵌入第二開口1101中。
圖13亦示出一旦已塗覆第四包封體1301，即可經由第一開口201、第二開口1101以及第四包封體1301將結構單體化。在一實施例中，可如上文關於圖6所描述執行單體化。舉例而言，可使用鋸刀603經由第二開口1101及第四包封體1301切開半導體晶圓100。然而，可利用任何合適的單體化製程。
藉由在單體化之前移除切割區102鄰近半導體晶圓100兩側的一部分，可在損壞(諸如第一金屬化層105及重佈線結構501中的介電材料的分層)的可能性降低的情況下製造經單體化的半導體元件600。藉由降低損壞的可能性，在製造製程期間可獲得較大良率，且可製造更可靠的半導體元件。
根據一實施例，一種半導體元件包含：連接半導體基底上的主動元件的金屬化層；連接至所述金屬化層的第一半導體元件；連接至所述金屬化層的第二半導體元件；以及包封所述第一半導體元件及所述第二半導體元件的包封體，所述包封體與所述金屬化層及所述半導體基底實體接觸。在一實施例中，所述包封體包括模製化合物。在一實施例中，所述包封體包括氧化矽。在一實施例中，支撐結構附接至所述氧化矽。在一實施例中，隨著所述包封體 延伸至所述半導體基底中，所述包封體的寬度減小。在一實施例中，所述半導體元件更包含：延伸穿過所述半導體基底的基底穿孔；連接至所述基底穿孔的重佈線層；以及鄰近所述重佈線層的鈍化層。在一實施例中，所述鈍化層具有彎曲側壁。
根據另一實施例，一種半導體元件包含：接合至半導體基底上方的金屬化層的第一半導體晶粒；接合至所述金屬化層的第二半導體晶粒；在所述第一半導體晶粒與所述第二半導體晶粒之間延伸的包封體，所述包封體亦延伸穿過所述金屬化層以與所述半導體基底實體接觸。在一實施例中，所述包封體鄰近所述金屬化層具有第一寬度且鄰近所述半導體基底具有小於所述第一寬度的第二寬度。在一實施例中，所述包封體具有第一表面，第一表面與所述半導體基底的第二表面共面。在一實施例中，所述包封體為氧化物材料。在一實施例中，所述半導體元件更包含附接至所述氧化物材料的支撐結構。在一實施例中，所述半導體元件更包含：延伸穿過所述半導體基底的基底穿孔；連接至所述基底穿孔的重佈線層；以及鄰近所述重佈線層的鈍化層。在一實施例中，所述半導體元件更包含延伸穿過所述重佈線層以與所述半導體基底實體接觸的第二包封體。
在又一實施例中，一種製造半導體元件的方法，所述方法包含：將第一半導體晶粒接合至元件，所述元件包括半導體基底；將第二半導體晶粒接合至所述元件；在所述半導體基底中形成開口；用填充材料填充所述開口；以及經由所述開口內的所述填充材料單體化所述半導體基底。在一實施例中，所述方法更包含：薄化所述半導體基底以暴露基底穿孔；形成與所述基底穿孔電連接的 重佈線層；以及在所述重佈線層上方塗覆鈍化層。在一實施例中，所述方法更包含在所述單體化所述半導體基底之前，形成延伸穿過所述鈍化層且延伸至所述半導體基底中的第二開口。在一實施例中，所述填充所述開口用氧化物材料來填充所述開口。在一實施例中，所述方法更包含將支撐結構附接至所述氧化物材料。在一實施例中，所述填充所述開口用模製化合物來填充所述開口。
前文概述若干實施例的特徵，使得所屬領域中具通常知識者可更佳地理解本揭露的態樣。所屬領域中具通常知識者應瞭解，其可易於使用本揭露作為設計或修改用於實施本文中所引入的實施例的相同目的及/或實現相同優點的其他製程及結構的基礎。所屬領域中具通常知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且所屬領域中具通常知識者可在不脫離本揭露的精神及範疇的情況下在本文中作出各種改變、替代以及更改。
100:半導體晶圓
101:第一半導體元件
102:切割區
103:第一基底
105:第一金屬化層
107:第一導電晶圓接合材料
109:第一晶圓接合層
111:基底穿孔
113:第二半導體元件
115:第三半導體元件
117:第二基底
119:第二金屬化層
121:第二晶圓接合層
123:第二導電晶圓接合材料

Claims (9)

  1. 一種半導體元件，包括：連接半導體基底上的主動元件的金屬化層；連接至所述金屬化層的第一半導體元件；連接至所述金屬化層的第二半導體元件；以及包封所述第一半導體元件及所述第二半導體元件的包封體，其中所述包封體具有第一表面，所述第一表面與所述金屬化層及所述半導體基底實體接觸，所述第一表面具有伸入所述金屬化層與所述半導體基底中的多個凹痕。
  2. 如請求項1之半導體元件，其中所述包封體包括模製化合物。
  3. 如請求項1之半導體元件，其中所述包封體包括氧化矽。
  4. 如請求項1之半導體元件，其中隨著所述包封體延伸至所述半導體基底中，所述包封體的寬度減小。
  5. 如請求項1之半導體元件，更包括：延伸穿過所述半導體基底的基底穿孔；連接至所述基底穿孔的重佈線層；以及鄰近所述重佈線層的鈍化層。
  6. 一種半導體元件，包括：接合至半導體基底上方的金屬化層的第一半導體晶粒；接合至所述金屬化層的第二半導體晶粒；在所述第一半導體晶粒與所述第二半導體晶粒之間延伸的包封體，所述包封體亦延伸穿過所述金屬化層以與所述半導體基底 實體接觸，其中所述包封體鄰近所述金屬化層具有第一寬度且鄰近所述半導體基底具有小於所述第一寬度的第二寬度。
  7. 如請求項6之半導體元件，其中所述包封體具有第一表面，所述第一表面與所述半導體基底的第二表面共面。
  8. 一種製造半導體元件的方法，所述方法包括：將第一半導體晶粒接合至元件，所述元件包括半導體基底；將第二半導體晶粒接合至所述元件；在所述半導體基底中形成開口，其中隨著所述開口延伸至所述半導體基底中，所述開口的寬度減小；用填充材料填充所述開口；以及經由所述開口內的所述填充材料單體化所述半導體基底。
  9. 如請求項8之製造半導體元件的方法，更包括：薄化所述半導體基底以暴露基底穿孔；形成與所述基底穿孔電連接的重佈線層；以及在所述重佈線層上方塗覆鈍化層。
TW110110734A 2020-06-30 2021-03-24 半導體元件及製造方法 TWI773216B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/917,388 2020-06-30
US16/917,388 US11424191B2 (en) 2020-06-30 2020-06-30 Semiconductor devices and methods of manufacture

Publications (2)

Publication Number Publication Date
TW202203404A TW202203404A (zh) 2022-01-16
TWI773216B true TWI773216B (zh) 2022-08-01

Family

ID=78124282

Family Applications (1)

Application Number Title Priority Date Filing Date
TW110110734A TWI773216B (zh) 2020-06-30 2021-03-24 半導體元件及製造方法

Country Status (5)

Country Link
US (2) US11424191B2 (zh)
KR (1) KR102480685B1 (zh)
CN (1) CN113539980B (zh)
DE (1) DE102020119295B4 (zh)
TW (1) TWI773216B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220006931A (ko) * 2020-07-09 2022-01-18 삼성전자주식회사 인터포저 및 이를 포함하는 반도체 패키지
KR20220042705A (ko) * 2020-09-28 2022-04-05 삼성전자주식회사 반도체 패키지 및 반도체 패키지의 제조 방법
US12021064B2 (en) * 2021-05-03 2024-06-25 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture
US20230187299A1 (en) * 2021-12-09 2023-06-15 Nxp B.V. Dielectric sidewall protection and sealing for semiconductor devices in a in wafer level packaging process
US20230299049A1 (en) * 2022-03-18 2023-09-21 Intel Corporation Microelectronic structure including active base substrate with through vias between a top die and a bottom die supported on an interposer
CN114927500B (zh) * 2022-07-19 2022-10-04 武汉大学 基于分布式的双扇出型异构集成三维封装结构及工艺

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201246482A (en) * 2010-09-24 2012-11-16 Stats Chippac Ltd Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
TW201322406A (zh) * 2011-11-30 2013-06-01 Taiwan Semiconductor Mfg 半導體裝置及其形成方法
TW201946233A (zh) * 2018-04-30 2019-12-01 台灣積體電路製造股份有限公司 封裝及其形成方法

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3233535B2 (ja) * 1994-08-15 2001-11-26 株式会社東芝 半導体装置及びその製造方法
US5910687A (en) 1997-01-24 1999-06-08 Chipscale, Inc. Wafer fabrication of die-bottom contacts for electronic devices
JPWO2009118950A1 (ja) * 2008-03-27 2011-07-21 イビデン株式会社 多層プリント配線板の製造方法
US8580657B2 (en) 2008-09-23 2013-11-12 Taiwan Semiconductor Manufacturing Company, Ltd. Protecting sidewalls of semiconductor chips using insulation films
US8338945B2 (en) * 2010-10-26 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Molded chip interposer structure and methods
US8557684B2 (en) 2011-08-23 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional integrated circuit (3DIC) formation process
TWI492350B (zh) * 2012-11-20 2015-07-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9425121B2 (en) * 2013-09-11 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out structure with guiding trenches in buffer layer
US9412662B2 (en) 2014-01-28 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and approach to prevent thin wafer crack
US10090241B2 (en) * 2015-05-29 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Device, package structure and method of forming the same
US10797038B2 (en) * 2016-02-25 2020-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and rework process for the same
US10510634B2 (en) * 2017-11-30 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method
US10510650B2 (en) 2018-02-02 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor device packaging structure having through interposer vias and through substrate vias
US10854552B2 (en) 2018-06-29 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
WO2020010136A1 (en) * 2018-07-06 2020-01-09 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US10665572B2 (en) * 2018-08-15 2020-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing method thereof
TWI770440B (zh) 2018-12-07 2022-07-11 美商艾馬克科技公司 半導體封裝和其製造方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201246482A (en) * 2010-09-24 2012-11-16 Stats Chippac Ltd Semiconductor device and method of forming TSV interposer with semiconductor die and build-up interconnect structure on opposing surfaces of the interposer
TW201322406A (zh) * 2011-11-30 2013-06-01 Taiwan Semiconductor Mfg 半導體裝置及其形成方法
TW201946233A (zh) * 2018-04-30 2019-12-01 台灣積體電路製造股份有限公司 封裝及其形成方法

Also Published As

Publication number Publication date
DE102020119295A1 (de) 2021-12-30
TW202203404A (zh) 2022-01-16
US20220367375A1 (en) 2022-11-17
DE102020119295B4 (de) 2024-08-29
US20210407920A1 (en) 2021-12-30
KR20220002040A (ko) 2022-01-06
KR102480685B1 (ko) 2022-12-22
CN113539980B (zh) 2024-02-02
CN113539980A (zh) 2021-10-22
US11424191B2 (en) 2022-08-23

Similar Documents

Publication Publication Date Title
US11456240B2 (en) Semiconductor device and method of manufacture
US11056471B2 (en) Semiconductor device and method of manufacture
US10090284B2 (en) Semiconductor device and method of manufacture
US11393783B2 (en) Dummy structure of stacked and bonded semiconductor device
TWI773216B (zh) 半導體元件及製造方法
KR101753454B1 (ko) 칩 온 패키지 구조 및 방법
US20240290755A1 (en) Semiconductor devices and methods of manufacture
US20220367466A1 (en) Semiconductor Devices with System on Chip Devices
US11856800B2 (en) Semiconductor devices with system on chip devices
CN220873580U (zh) 封装件