TW201946233A - 封裝及其形成方法 - Google Patents

封裝及其形成方法 Download PDF

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Publication number
TW201946233A
TW201946233A TW107127228A TW107127228A TW201946233A TW 201946233 A TW201946233 A TW 201946233A TW 107127228 A TW107127228 A TW 107127228A TW 107127228 A TW107127228 A TW 107127228A TW 201946233 A TW201946233 A TW 201946233A
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Taiwan
Prior art keywords
package
forming
encapsulating material
element die
die
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TW107127228A
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English (en)
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TWI669791B (zh
Inventor
陳明發
余振華
陳憲偉
胡致嘉
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台灣積體電路製造股份有限公司
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Publication of TWI669791B publication Critical patent/TWI669791B/zh
Publication of TW201946233A publication Critical patent/TW201946233A/zh

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Abstract

本揭露提供一種封裝及其形成方法。封裝的形成方法包含形成中介結構，所述中介結構包含半導體基底及半導體基底上方的互連結構。所述方法更包含將元件晶粒接合至中介結構，使得中介結構中的第一金屬墊接合至元件晶粒中的第二金屬墊，且中介結構中的第一表面介電層接合至元件晶粒中的第二表面介電層。所述方法更包含以包封材料包封元件晶粒；在元件晶粒上方形成導電特徵且使其電耦合至所述元件晶粒；以及移除半導體基底。中介結構的一部分、元件晶粒以及導電特徵的一部分共同地形成封裝。

Description

封裝及其形成方法
積體電路的封裝變得越來越複雜，以將更多元件晶粒（device die）整合於同一封裝中而取得更多的功能。舉例而言，系統整合晶片（System on Integrate Chip，SoIC）已被開發成在同一封裝中包含諸如處理器及記憶體塊的多個元件晶粒。SoIC可接合使用不同技術形成的元件晶粒且對同一元件晶粒帶來不同的功能，因此形成系統。此可節省製造成本並最佳化元件效能。
以下揭露內容提供用於實施本揭露之不同特徵的許多不同實施例或實例。在下文描述構件及配置的特定實例以簡化本揭露。當然，此等構件及配置僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵在第二特徵上方或第二特徵上的形成可包含第一特徵及第二特徵直接接觸地形成的實施例，且亦可包含額外特徵可在第一特徵與第二特徵之間形成使得第一特徵與第二特徵可不直接接觸的實施例。另外，本揭露可在各種實例中重複參考編號及/或字母。此重複是出於簡單性及清楚的目的，且自身並不規定所論述的各種實施例及/或組態之間的關係。
另外，諸如「在……之下」、「在……下方」、「下部」、「上覆」、「上部」及其類似者的空間相對術語可在本文中為了易於描述而使用，從而描述如圖中所說明的一個元件或特徵與另一或多個元件或特徵的關係。除圖中所描繪的定向以外，空間相對術語意欲亦涵蓋元件在使用或操作中的不同定向。設備可以其他方式定向（旋轉90度或處於其他定向）且本文中所使用的空間相對描述詞可同樣相應地進行解譯。
根據各種實施例提供封裝及其形成方法。根據一些實施例說明形成封裝的中間階段。論述一些實施例的一些變化。在各個圖式及說明性實施例中，類似的參考編號用以指定類似元件。應瞭解，儘管以水平系統整合晶片（SoIC-H）封裝的形成作為實例來解釋本揭露實施例的概念，但本揭露的實施例可輕易地應用至其他封裝。
圖1說明在形成晶圓2之過程中的初始結構的橫截面圖。根據本揭露的一些實施例，晶圓2為中介晶圓（interposer wafer），其不含諸如電晶體及/或二極體的主動元件。中介晶圓2可不含諸如電容器、電感器、電阻器或其類似者的被動元件，或可包含被動元件。中介晶圓2中可包含多個晶片4，其中說明晶片4中的一者的一些細節。晶片4在下文中被替代地稱作晶粒。
根據本揭露的一些實施例，晶圓2包含半導體基底20及形成於半導體基底20上方的特徵。半導體基底20可由結晶矽、結晶鍺、結晶矽鍺及/或III-V族化合物半導體形成，所述III-V族化合物半導體諸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP以及其類似者。基底20亦可由其他剛性材料，諸如玻璃、氧化矽、碳化矽或其類似者形成。當基底20由半導體形成時，基底20亦可為塊狀矽基底。
於半導體基底20上方形成介電層24。根據本揭露的一些實施例，介電層24是由氧化矽、氮化矽、碳化矽、氮氧化矽、碳氧化矽或其類似者形成。根據一些實施例，介電層24是由氧化矽形成，可對基底20執行熱氧化以形成氧化物層24。
在介電層24上方設置互連結構30，所述互連結構30包含介電層32及金屬線34/通孔36。圖1示意性地說明金屬線34及通孔36，且圖14根據一些實施例說明介電層32、金屬線34以及通孔36的一些細節。如圖14所示，互連結構30包含金屬線34及通孔36，所述金屬線及通孔皆形成於介電層32中。介電層32在下文中被替代地稱作金屬間介電（Inter-Metal Dielectric，IMD）層32。根據本揭露的一些實施例，至少較低層的介電層32是由可具有低於約3.0的介電常數（k值）的低k介電材料形成。介電層32可由黑金剛石（應用材料公司的註冊商標）、含碳低k介電材料、三氧化矽烷（Hydrogen SilsesQuioxane，HSQ）、甲基矽倍半氧烷（MethylSilsesQuioxane，MSQ）或其類似者形成。根據本揭露的替代實施例，介電層32中的一些或全部層由非低k介電材料形成，所述材料例如是氧化矽、碳化矽（SiC）、碳氮化矽（SiCN）、碳氧氮化矽（SiOCN）或其類似者。根據本揭露的一些實施例，介電層32的形成包含沈積含成孔劑（porogen）的介電材料，且接著執行固化製程以將成孔劑向外驅趕，且因此剩餘介電層32為多孔性的。可由碳化矽、氮化矽或其類似者形成的蝕刻終止層（未繪示）形成於IMD層32的相鄰兩層之間，且為簡潔起見並未被展示。
處在同一層級的金屬線34在下文中被集體地稱作金屬層。根據本揭露的一些實施例，互連結構30包含藉由通孔36互連的多個金屬層。金屬線34及通孔36可由銅或銅合金形成，且其亦可由其他金屬形成。形成製程可包含單金屬鑲嵌製程及雙金屬鑲嵌製程。在單金屬鑲嵌製程的實例中，首先在介電層32中的一者中形成溝渠，繼而用導電材料填充溝渠。接著執行諸如化學機械研磨（Chemical Mechanical Polish，CMP）製程的平坦化製程，以移除高於IMD層的頂部表面的導電材料的過量部分，從而在溝渠中留下金屬線。在雙金屬鑲嵌製程中，在IMD層中形成溝渠及通孔開口兩者，其中通孔開口在溝渠之下且連接至溝渠。接著將導電材料填充至溝渠及通孔開口中，以分別形成金屬線及通孔。金屬線34及通孔36中的一者在圖14中予以詳細地展示，且擴散障壁層35A以及上覆的導電材料35B被說明為導電材料的實例。擴散障壁層35A可包括鈦、氮化鈦、鉭、氮化鉭或其類似者。導電材料35B可由銅或銅合金形成。
返回參看圖1，晶粒4/晶圓2包含形成於其頂部表面處的表面介電層38。表面介電層38是由諸如氧化矽的非低k介電材料形成。表面介電層38被替代地稱作鈍化層，此是由於其具有將下伏低k介電層（若存在）隔離以使其免受濕氣及有害化學製品不利影響的功能。表面介電層38亦可具有包含多於一個層的複合結構，其可由氧化矽、氮化矽、未經摻雜的矽酸鹽玻璃（Undoped Silicate Glass，USG）或其類似者形成。晶粒4亦可包含金屬墊，諸如鋁墊或鋁銅墊、後鈍化互連件（Post-Passivation Interconnect，PPI）或其類似者，為簡潔起見不對其進行繪示。
於表面介電層38中形成接合墊40。根據本揭露的一些實施例，經由單金屬鑲嵌製程而形成接合墊40，且亦可包含形成障壁層及形成於各個障壁層上方的含銅材料。根據本揭露的替代實施例，經由雙金屬鑲嵌製程而形成接合墊40。頂部表面介電層38及接合墊40經平坦化使得其頂部表面共面，此可為在形成接合墊40的過程中的CMP所致。
接下來，如圖2中所展示，將元件晶粒42A及元件晶粒42B接合至晶圓2。對應製程被說明為如圖17中所展示的製程流程200中的製程202。根據本揭露的一些實施例，元件晶粒42A及元件晶粒42B中的每一者可為中央處理單元（Central Processing Unit，CPU）晶粒、微控制單元（Micro Control Unit，MCU）晶粒、輸入/輸出（input-output，IO）晶粒、基頻（BaseBand，BB）晶粒、應用程式處理器（Application processor，AP）晶粒或其類似者。元件晶粒42A及元件晶粒42B亦可包含記憶體晶粒。另外，元件晶粒42A及元件晶粒42B可為選自上文所列類型的不同類型的晶粒。可使用諸如45 nm技術、28 nm技術、20 nm技術或其類似者的不同技術來形成元件晶粒42A及元件晶粒42B。又，元件晶粒42A及元件晶粒42B中的一者可為數位電路晶粒，而另一者可為類比電路晶粒。晶粒4、晶粒42A以及晶粒42B的組合能作為系統。將系統的功能及電路分成諸如晶粒42A及晶粒42B的不同晶粒可最佳化此等晶粒的形成，且可降低製造成本。
元件晶粒42A及元件晶粒42B分別包含半導體基底44A及半導體基底44B，所述半導體基底可為矽基底。積體電路元件46A及積體電路元件46B形成於元件晶粒42A及元件晶粒42B中，所述積體電路元件可包含諸如電晶體及/或二極體的主動元件及諸如電容器、電阻器或其類似者的被動元件。又，元件晶粒42A及元件晶粒42B分別包含互連結構53A及互連結構53B，所述互連結構用於連接至元件晶粒42A及元件晶粒42B中的主動元件及被動元件。互連結構53A及互連結構53B包括金屬線及通孔（未繪示）。
晶粒42A包含接合墊50A及介電層52A，接合墊50A與介電層52A位於晶粒42A的底部表面處。接合墊50A的底部表面與介電層52A的底部表面共面。晶粒42B包含接合墊50B及介電層52B，接合墊50B與介電層52B位於晶粒42B的底部表面處。接合墊50B的底部表面與介電層52B的底部表面共面。根據本揭露的一些實施例，諸如晶粒42A及晶粒42B的所有元件晶粒皆不含諸如聚合物的有機介電材料。
可藉由混合式接合（hybrid bonding）來進行接合。舉例而言，藉由金屬對金屬（metal-to-metal）直接接合以將接合墊50A及接合墊50B接合至接合墊40。根據本揭露的一些實施例，金屬對金屬直接接合包含銅對銅直接接合。此外，藉由熔接接合（fusion bonding）而將介電層52A及介電層52B接合至表面介電層38。
為達成混合式接合，首先藉由將元件晶粒42A及元件晶粒42B抵靠晶粒4且輕微按壓元件晶粒42A及元件晶粒42B，以將元件晶粒42A及元件晶粒42B預接合至介電層38及接合墊40。儘管只說明兩個元件晶粒42A及42B的預接合方法，但可在晶圓層級下執行混合式接合，且將相同於所說明晶粒群組（其包含元件晶粒42A及元件晶粒42B）的多個元件晶粒群組預接合，且配置為若干列及若干行。
在預接合所有元件晶粒42A及元件晶粒42B之後，執行退火以使得接合墊40以及對應的上覆接合墊50A及上覆接合墊50B中的金屬發生相互擴散。根據一些實施例，退火溫度可在約200℃與約400℃之間的範圍內，且可在約300℃與約400℃之間的範圍內。根據一些實施例，退火時間可在約1.5小時與約3.0小時之間的範圍內，且可在約1.5小時與約2.5小時之間的範圍內。藉由混合式接合，由金屬相互擴散造成的直接金屬接合（direct metal bonding）能將接合墊50A及接合墊50B接合至對應接合墊40。
介電層38亦接合至介電層52A及介電層52B，其中在介電層38與介電層52A之間及介電層38與介電層52B之間形成鍵結。舉例而言，介電層38以及介電層52A/52B中的一者中的原子（諸如氧原子）與介電層38以及介電層52A/52B中的另一者中的原子（諸如矽原子）形成化學鍵結或共價鍵結。介電層38與介電層52A/52B之間的所得鍵結為介電質對介電質（dielectric-to-dielectric）鍵結。接合墊50A及接合墊50B的大小可大於、等於或小於各別接合墊40的大小。
接下來，參看圖3，在將元件晶粒42A及元件晶粒42B接合至晶粒4之後，以包封材料（包封體）54包封元件晶粒42A及元件晶粒42B。對應的製程被說明為如圖17中所展示的製程流程200中的製程204。包封材料54可為模製化合物、模製底部填充料、環氧樹脂及/或樹脂。包封材料54的頂部表面高於基底44A及基底44B的頂部表面。圖15示意性地說明包封材料54的一些細節。包封材料54可包含可為聚合物、樹脂、環氧樹脂或其類似者的基質材料54A，以及基質材料54A中的填料粒子54B。基質材料可為碳基聚合物。填料粒子可為諸如SiO2 、Al2 O3 、矽石、鐵（Fe）化合物、鈉（Na）化合物或其類似者的介電材料粒子，且可具有球形形狀。又，根據一些實例，如圖15中所繪示，球形填料粒子54B可具有相同直徑或不同直徑。
在後續步驟中，亦如圖3中所展示，執行諸如化學機械研磨（Chemical Mechanical Polish，CMP）製程或機械研磨製程的平坦化製程以使元件晶粒42A及元件晶粒42B以及包封材料54的頂部表面平坦化，直至曝露基底44A及基底44B為止。歸因於平坦化製程，模製的包封材料54的頂部表面處（圖3中）的一些填料粒子54B被部分研磨，從而使得填料粒子中的一些的頂部部分被移除，且保留底部部分。所得部分的填料粒子因此將具有平坦的頂部表面，所述平坦的頂部表面分別與基質材料54A以及元件晶粒42A的基底44A及元件晶粒42B的基底44B的頂部表面共面。
根據本揭露的一些實施例，在以包封材料54包封元件晶粒42A及元件晶粒42B之前，不對元件晶粒42A及元件晶粒42B進行薄化。又，在施予包封材料54之後執行的平坦化製程期間，不對包封材料54過度地執行平坦化。根據本揭露的一些實施例，一旦曝露基底44A及基底44B兩者時就終止平坦化。因此，保留元件晶粒42A及元件晶粒42B的厚度，且元件晶粒42A及元件晶粒42B以及包封材料54具有足夠的厚度，使得在隨後移除基底20時作為支撐結構。
根據本揭露的一些實施例，如圖4中所展示，元件晶粒42A及元件晶粒42B以及包封材料54並不具有足夠的厚度。將支撐基底56附接至元件晶粒42A及元件晶粒42B，且亦可能附接至包封材料54。對應的製程被說明為如圖17中所展示的製程流程200中的製程206。支撐基底56可為由諸如矽的均質材料形成的空白基底（blank substrate），且無元件形成於基底56上/中。可藉由熔接接合使支撐基底56與基底44A/44B接合。在所附實例中，例如藉由熱氧化以於基底56的表面上形成氧化矽層58。接著，使基底56經由氧化矽層58接合至基底44A及基底44B，其中在氧化物層58與基底44A/44B之間形成Si-O-Si鍵結。由於包封材料54並非由氧化物或矽形成，故氧化物層58可實體接觸包封材料54但並不鍵結至包封材料54。根據替代實施例，對基底56、基底44A及基底44B執行處理以形成Si-OH鍵結，且因此可藉由熔接接合使基底56直接接合至基底44A及基底44B。
根據替代實施例，經由諸如熱介面材料（Thermal Interface Material，TIM）的黏著膜將支撐基底56附接至基底44A/44B。根據替代實施例，省略圖4中所展示的製程（亦即不附接支撐基底），且執行如圖5中所展示的製程。相應地，基底56及氧化矽層58在後續圖中被繪示為虛線，從而指示其可能存在或可能不存在。
接下來，將圖4（或圖3，若省略圖4中的步驟）中所示的結構上下顛倒地翻轉。接著例如在CMP製程或機械研磨製程中移除基底20。對應的製程被說明為如圖17中所示的製程流程200中的製程208。圖5中展示所得的結構。根據本揭露的一些實施例，使用介電層24作為研磨（CMP）終止層來執行平坦化。因此，在移除基底20之後，就曝露介電層24。根據替代實施例，亦移除介電層24，且曝露金屬線/金屬墊34。接著，可形成介電層來覆蓋金屬線/金屬墊34。
參看圖6，形成導電特徵60及介電層62。對應的製程被說明為如圖17中所展示的製程流程200中的製程210。介電層62可由諸如矽、氮化矽或其類似者的無機材料，或由可為聚苯并噁唑（polybenzoxazole，PBO）、聚醯亞胺或其類似者的有機材料（諸如聚合物）形成。導電特徵60可為金屬墊、凸塊下金屬層（Under-Bump-Metallurgy，UBM）、金屬柱或其類似者，且可由銅、鈦、鎳、鋁、其合金以及其所組成的多層結構形成。可執行單體化（singulation），使得晶圓2及形成於其上之結構被鋸切成彼此相同的多個封裝64。若支撐基底56附接至元件晶粒42A及元件晶粒42B，則支撐基底56亦被鋸切於若干封裝64中。對應的製程被說明為如圖17中所展示的製程流程200中的製程212。封裝64亦被稱作元件封裝或SoIC-H封裝，此係由於晶粒42A及晶粒42B被水平地分配於同一層級中。封裝64中的晶粒4的剩餘部分與介電層62及導電特徵60在下文中被合併地稱作中介結構（interposer）4。
圖7至圖12說明根據本揭露的一些實施例的SoIC-H封裝的形成的中間階段的橫截面圖。對應的製程被說明為如圖17中所展示的製程流程200中的製程214。除非另外指定，否則在此等實施例中的構件的材料及形成方法基本上等同於上述對應的構件，所述構件由圖1至圖6中所示實施例中的類似參考編號表示。關於圖7至圖12中所示構件的形成製程及材料的細節可因此在對應於圖1至圖6中所示實施例的論述中找到。
圖7至圖12中所示的實施例相似於圖1至圖6中所示的實施例，惟額外形成基底穿孔（Through-Substrate-Vias，TSV）66。參看圖7，形成晶圓2，其中TSV 66形成為延伸至基底20中。TSV 66電連接至互連結構30中的金屬線34及通孔36。圖7中所示的其他構件可與參看圖1所論述的構件相似，且因此不對其再次進行論述。
參看圖8，藉由混合式接合將元件晶粒42A及元件晶粒42B接合至晶粒4。此處不在贅述元件晶粒42A、元件晶粒42B以及接合製程的細節。接下來，參看圖9，以包封材料54包封元件晶粒42A及元件晶粒42B，接著進行平坦化製程來移除包封材料54的過量部分。因此，曝露出基底44A及基底44B，所述基底44A及基底44B的頂部表面與包封材料54的頂部表面共面。再次，一旦曝露基底44A及基底44B時就可終止平坦化。
參看圖10，根據本揭露的一些實施例，將可由矽形成的支撐基底56經由層58而附接至元件晶粒42A、元件晶粒42B以及包封材料54。根據本揭露的一些實施例，支撐基底56為矽基底，且層58為氧化物層且藉由熔接接合而接合至基底44A及基底44B，其中在氧化矽層58與基底44A/44B之間形成Si-O-Si鍵結。根據本揭露的替代實施例，層58為諸如TIM的黏著層。根據又一些替代實施例，支撐基底56為矽基底，且藉由熔接接合而直接接合至基底44A及基底44B。
接著，將圖10中所示的結構上下顛倒地翻轉，且薄化基底20直至曝露出TSV 66為止。圖11中展示所得結構。TSV 66也可略高於剩餘基底20的頂部表面而突出。接下來，參看圖12，形成介電層68及介電層70，且於介電層68及介電層70中形成重佈線（redistribution line，RDL）72，以使重佈線72電耦合至TSV 66。介電層68及介電層70可由諸如矽、氮化矽或其類似者的無機材料形成，或由可為聚苯并噁唑（polybenzoxazole，PBO）、聚醯亞胺或其類似者的有機材料（諸如聚合物）形成。介電層62及傳導特徵60亦經形成以電性連接至RDL 72。
可執行單體化，使得晶圓2及形成於其上之結構被鋸切成彼此相同的多個SoIC-H封裝64。晶粒4的剩餘部分以及上覆結構在下文共同地被稱作中介結構4。若支撐基底56附接至元件晶粒42A及元件晶粒42B，則支撐基底56亦被鋸切於若干SoIC-H封裝64中。
圖13A、圖13B、圖13C、圖13D、圖13E、圖13F以及圖13G根據本揭露的一些實施例說明以基於SoIC-H封裝64形成的一些封裝的橫截面圖。SoIC-H封裝64內建於積體扇出型（Integrated Fan-out，InFO）封裝中。SoIC-H封裝64在圖13A、圖13B、圖13C、圖13D、圖13E、圖13F以及圖13G中被示意性地說明，且SoIC-H封裝64的細節可參看圖6及圖12的相關說明。圖13A、圖13B、圖13C、圖13D、圖13E、圖13F以及圖13G中的SoIC-H封裝64中的每一者可具有圖6及圖12中的任一者中所示的結構。在後續論述中，說明為了形成圖13A中所示封裝的簡要製程，且相同製程亦可適用於形成圖13B、圖13C、圖13D、圖13E、圖13F以及圖13G中所示的結構。
在圖13A中所示結構的形成製程中，首先於離型薄膜（未繪示）上形成介電緩衝層76，其中所述離型薄膜塗布在載體（未繪示）上。載體為可由玻璃形成的透明載體。離型薄膜可為光-熱轉換（Light-To-Heat-Conversion，LTHC）塗層，其在諸如雷射光束的輻射熱下分解，且因此用以將形成於其上的結構與載體分離。介電緩衝層76可由諸如PBO或聚醯亞胺的有機材料（例如聚合物）形成，或由諸如氧化矽、氮化矽或其類似者的無機材料形成。
根據本揭露的一些實施例，將SoIC-H封裝64經由作為黏著膜的晶粒貼合膜（Die-Attach Film，DAF）78而附接至介電緩衝層76。DAF 78的邊緣可與SoIC-H封裝64的對應邊緣齊平。可在晶圓層級下執行封裝製程，其中多個SoIC-H封裝64被置放於介電緩衝層76上。在置放SoIC-H封裝64之後，分配且固化包封材料74，接著進行諸如CMP製程或機械研磨製程的平坦化製程。藉由平坦化製程，SoIC-H封裝64的頂部表面與包封材料74的頂部表面共面。
圖16示意性地說明如圖13A中所展示的區75中的包封材料74的頂部部分。如圖16中所展示，包封材料74可包含可為聚合物、樹脂、環氧樹脂或其類似者的基質材料74A，及基質材料74A中的填料粒子74B。聚合物可為碳基聚合物。填料粒子74B可為諸如SiO2 、Al2 O3 、矽石、鐵（Fe）化合物、鈉（Na）化合物或其類似者的介電材料粒子，且可具有球形形狀。又，如圖16中所說明，根據一些實例，球形填料粒子74B可具有相同直徑或不同直徑。
圖15說明如圖13A中所展示的區77中的包封材料54的底部部分。比較圖15與圖16，應瞭解，在圖15中，部分填料粒子54B在底部，其可接觸DAF 78，而在圖16中，部分填料粒子74B在頂部，其可接觸介電層80。
包封材料54與包封材料74可彼此相同或不同。舉例而言，包封材料54是在中介結構4下方，且因此其熱膨脹係數（coefficient of thermal expansion，CTE）顯著影響所得封裝的翹曲，此尤其是當中介結構4中包含矽基底時（參考圖13B）。另一方面，包封材料74完全環繞中介結構4及元件晶粒42A、元件晶粒42B以及元件晶粒42C，且因此其CTE相比於包封材料54有較小的影響（在造成翹曲方面）。因此，對包封材料54的選擇更具限定性，且可將其選擇為具有小CTE。可根據諸如較低成本的其他準則來選擇包封材料74。因此，包封材料74的CTE可大於包封材料54的CTE。
在包封及平坦化之後，形成介電層80，其可由諸如PBO或聚醯亞胺的有機材料（例如聚合物）形成，或由諸如氧化矽、氮化矽或其類似者的無機材料形成。於介電層80中形成RDL 82，且RDL 82經形成以電耦合至SoIC-H封裝64中的導電特徵60。接著，形成UBM 84及電連接件86（諸如焊料區）。在後續製程中，例如藉由投射雷射光束來分解下伏的離型薄膜（未繪示）而將圖13A中所展示的結構自所述離型薄膜及載體（未繪示）剝離。接著，執行單體化以形成多個相同的封裝，每一封裝包含SoIC-H封裝64中的一者。所得封裝被稱作封裝90A。在單體化中，鋸切緩衝介電層76、包封材料74以及介電層80。
圖13B說明根據本揭露的一些實施例而形成的封裝90B，其中封裝90B嵌入有SoIC-H封裝64。此等實施例相似於圖13A中所展示的實施例，不同之處在於：中介結構4包含半導體基底20，且穿孔66貫穿半導體基底20。可參考圖6至圖12中的實施例的論述來找到基底20及穿孔66的細節。
圖13C說明根據本揭露的一些實施例而形成的封裝90C，其中封裝90C嵌入有SoIC-H封裝64。此等實施例相似於圖13A中所展示的實施例，不同之處在於：SoIC-H封裝64包含支撐基底56，且支撐基底56與DAF 78接觸。可參考圖1至圖12中的實施例的論述來找到支撐基底56的細節。
圖13D說明根據本揭露的一些實施例而形成的封裝90D，其中封裝90D嵌入有SoIC-H封裝64。此等實施例相似於圖13A中所展示的實施例，不同之處在於：中介結構4包含半導體基底20，且穿孔66貫穿半導體基底20。此外，支撐基底56設置於SoIC-H封裝64中，且與DAF 78接觸。可參考圖12的論述來找到基底20、穿孔66以及支撐基底56的細節。
圖13E說明根據本揭露的一些實施例而形成的封裝90E，其中封裝90E嵌入有SoIC-H封裝64。此等實施例相似於圖13A中所展示的實施例，不同之處在於：額外的InFO封裝91接合至封裝90E-1。儘管在一實例中封裝90E-1具有封裝90A的結構，但亦可具有封裝90B（圖13B）、封裝90C（圖13C）或封裝90D（圖13D）的任何其他結構。InFO封裝91可包含包封材料74'，及貫穿包封材料74'的穿孔96。底部填料92安置於封裝91與封裝90E-1之間。
圖13F說明根據本揭露的一些實施例而形成的封裝90F，其中封裝90F嵌入有SoIC-H封裝64。此等實施例相似於圖13A中所展示的實施例，不同之處在於：額外的InFO封裝90F-2接合至封裝90F-1，所述封裝各自具有SoIC-H封裝64（被標記為64-1及64-2以便進行區分）。SoIC-H封裝90F-1及SoIC-H封裝90-F2中的每一者可具有選自封裝90A（圖13A）、封裝90B（圖13B）、封裝90C（圖13C）或封裝90D（圖13D）的結構。InFO封裝90F-2可包含包封材料74'，及包封材料74'中的穿孔96。底部填料92安置於封裝90F-1與封裝90F-2之間。
圖13G說明根據本揭露的一些實施例而形成的封裝90G，其中封裝90G嵌入有SoIC-H封裝64。此等實施例相似於圖13A中所展示的實施例，不同之處在於：穿孔96形成於封裝90G-1中且貫穿包封材料74。額外封裝93接合至封裝90G-1。封裝93可包含記憶體晶粒94，所述記憶體晶粒可為動態隨機存取記憶體（Dynamic Random Access Memory，DRAM）晶粒。
在上文所說明的例示性實施例中，根據本揭露的一些實施例論述一些例示性製程及特徵。亦可包含其他特徵及製程。舉例而言，可包含測試結構以幫助對3D封裝或3DIC元件的驗證測試。測試結構可包含例如形成於重佈層中或基底上的測試墊，其允許測試3D封裝或3DIC、使用探測器及/或探測卡及其類似者。可對中間結構以及最終結構執行驗證測試。另外，本文中所揭露的結構及方法可結合併有對已知良好晶粒的中間驗證的測試方法使用，以提高產率且降低成本。
本揭露的實施例具有一些有利特徵。形成SoIC-H封裝並將SoIC-H封裝整合至其他封裝中，從而改良所得封裝的積集度。此外，平坦化製程通常需要高成本。然而，在如在圖3及圖9中的間隙填充製程中，若元件晶粒在平坦化過程中並未被薄化，則難以填充氧化物，此是因為氧化物通常無法用以填充深於約30微米的間隙。根據本揭露的一些實施例，模製化合物可用以填充深的間隙，從而避免了用於薄化元件晶粒的平坦化製程。
根據本揭露的一些實施例，一種封裝的形成方法包含形成中介結構，所述中介結構包含半導體基底及所述半導體基底上方的互連結構。所述方法更包含將元件晶粒接合至所述中介結構，使得所述中介結構中的第一金屬墊接合至所述元件晶粒中的第二金屬墊，且所述中介結構中的第一表面介電層接合至所述元件晶粒中的第二表面介電層。所述方法更包含以第一包封材料包封所述元件晶粒；在所述元件晶粒上方形成導電特徵且使其電耦合至所述元件晶粒；以及移除所述半導體基底。所述中介結構的一部分、所述元件晶粒以及所述導電特徵的一部分共同地形成封裝。在一實施例中，所述方法更包括將支撐基底附接至所述元件晶粒，其中所述支撐基底形成所述封裝的一部分。在一實施例中，所述支撐基底為空白半導體基底。在一實施例中，所述方法更包括將所述中介結構及所述第一包封材料鋸切為彼此分離的多個封裝，其中所述封裝為所述多個封裝中的一者，其中在所述鋸切中，所述支撐基底被鋸開。在一實施例中，所述方法更包括以第二包封材料包封所述封裝；及在所述封裝上方形成重佈線且使其電耦合至所述封裝。在一實施例中，所述第一包封材料及所述第二包封材料具有不同的CTE。在一實施例中，所述方法更包括執行晶粒鋸切來鋸切所述第二包封材料。在一實施例中，在以第一包封材料進行包封之前，並不對所述元件晶粒執行薄化。
根據本揭露的一些實施例，一種封裝的形成方法包括：形成中介晶圓，所述中介結構晶圓包括：半導體基底；及所述半導體基底上方的互連結構；將多個元件晶粒接合至所述中介晶圓，其中將所述中介晶圓中的第一金屬墊接合至所述元件晶粒中的第二金屬墊，且將所述中介晶圓中的第一表面介電層接合至所述元件晶粒中的第二表面介電層；以第一包封材料包封所述元件晶粒；在所述元件晶粒上方形成導電特徵且使其電耦合至所述元件晶粒；鋸切所述中介晶圓及所述第一包封材料以形成多個封裝；以第二包封材料包封所述多個封裝中的一者；形成與所述第二包封材料以及所述多個封裝中的所述一者重疊的重佈線，以形成InFO封裝；以及鋸切所述第二包封材料以形成多個額外封裝。在一實施例中，所述方法更包括將支撐基底附接至所述元件晶粒，其中當所述中介晶圓被鋸切時，所述支撐基底被鋸切於所述多個封裝中。在一實施例中，所述支撐基底包括矽基底，且經由混合式接合將所述矽基底接合至所述多個元件晶粒的基底。在一實施例中，所述第一包封材料及所述第二包封材料具有不同的CTE。在一實施例中，在以第一包封材料進行包封之前，並不對所述元件晶粒執行薄化。在一實施例中，所述方法更包括在所述鋸切之前移除所述中介晶圓的所述半導體基底。在一實施例中，所述中介晶圓包括所述半導體基底中的穿孔，且所述方法更包括：在形成所述重佈線之前，研磨所述半導體基底以暴露出所述穿孔，其中所述重佈線電耦合至所述穿孔。
根據本揭露的一些實施例，一種封裝包括：SoIC-H封裝（元件封裝），所述SoIC-H封裝包括：中介結構；元件晶粒，位於所述中介結構下方且接合至所述中介結構；以及第一包封材料，包封所述元件晶粒，其中所述第一包封材料與所述中介結構的一部分重疊。封裝更包括：第二包封材料，包封所述SoIC-H封裝；與所述第二包封材料及所述SoIC-H封裝重疊的至少一介電層；以及位於所述至少一介電層中的導電特徵，其中所述導電特徵經由所述中介結構電耦合至所述元件晶粒。在一實施例中，所述中介結構中的第一金屬墊經由金屬對金屬直接接合而接合至所述元件晶粒中的第二金屬墊，且所述中介結構中的第一表面介電層經由熔接接合而接合至所述元件晶粒中的第二表面介電層。在一實施例中，所述封裝更包括在所述元件晶粒的半導體基底下方且接合至所述元件晶粒的所述半導體基底的支撐基底。在一實施例中，所述封裝更包括在所述第二包封材料下方且接觸所述第二包封材料的介電緩衝層。在一實施例中，所述封裝更包括在所述介電緩衝層上方且接觸所述介電緩衝層的黏著膜，其中所述黏著膜的邊緣與所述SoIC-H封裝的邊緣齊平。
前文概述若干實施例的特徵，從而使得在本領域具有知識者可較好地理解本揭露的態樣。在本領域具有知識者應瞭解，其可易於使用本揭露作為設計或修改用於進行本文中所引入實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。在本領域具有知識者亦應認識到，此類等效構造並不脫離本揭露的精神及範疇，且其可在不脫離本揭露的精神及範疇的情況下在本文中進行各種改變、替代以及更改。
2‧‧‧中介晶圓
4‧‧‧晶片/晶粒/中介結構
20、44A、44B‧‧‧半導體基底
24、52A、52B、62、68、70、80‧‧‧介電層
30、53A、53B‧‧‧互連結構
32‧‧‧介電層
34‧‧‧金屬線/金屬墊
35A‧‧‧擴散障壁層
35B‧‧‧導電材料
36‧‧‧通孔
38‧‧‧頂部表面介電層
40、50A、50B‧‧‧接合墊
42A、42B、42C‧‧‧元件晶粒
46A、46B‧‧‧積體電路元件
54、74、74'‧‧‧包封材料
54A、74A‧‧‧基質材料
54B‧‧‧部分填料粒子
56‧‧‧基底
58‧‧‧層
60‧‧‧導電特徵
64、64-1、64-2‧‧‧水平系統整合晶片（SoIC-H）封裝
66‧‧‧基底穿孔（TSV）
72、82‧‧‧重佈線（RDL）
74B‧‧‧部分填料粒子
75、77‧‧‧區
76‧‧‧介電緩衝層
78‧‧‧晶粒貼合膜（DAF）
84‧‧‧凸塊下金屬層（UBM）
86‧‧‧電連接件
90A、90B、90C、90D、90E、90E-1、90F、90F-1、90F-2、90G、90G-1、91、93‧‧‧封裝
92‧‧‧底部填料
94‧‧‧記憶體晶粒
96‧‧‧穿孔
200‧‧‧製程流程
202、204、206、208、210、212、214‧‧‧製程
當結合附圖閱讀時，自以下詳細描述最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。實際上，為論述清楚起見，可任意增加或減小各種特徵的尺寸。 圖1至圖6為根據一些實施例的水平系統整合晶片（System-on-Integrated-Chip-Horizontal，SoIC-H）封裝之形成的中間階段的橫截面圖。 圖7至圖12為根據一些實施例的SoIC-H封裝的形成的中間階段的橫截面圖。 圖13A、圖13B、圖13C、圖13D、圖13E、圖13F以及圖13G說明根據一些實施例的包含內建式SoIC-H封裝的封裝的橫截面圖。 圖17說明用於形成根據一些實施例的封裝的製程流程。

Claims (20)

  1. 一種封裝的形成方法，包括： 形成中介結構，所述中介結構包括： 半導體基底；以及 互連結構，位於所述半導體基底上方； 將元件晶粒接合至所述中介結構，其中所述中介結構中的第一金屬墊接合至所述元件晶粒中的第二金屬墊，且所述中介結構中的第一表面介電層接合至所述元件晶粒中的第二表面介電層； 以第一包封材料包封所述元件晶粒； 在所述元件晶粒上方形成導電特徵且使所述導電特徵電耦合至所述元件晶粒；以及 移除所述半導體基底，其中所述中介結構的一部分、所述元件晶粒以及所述導電特徵的一部分共同地形成封裝。
  2. 如申請專利範圍第1項所述的封裝的形成方法，更包括： 將支撐基底附接至所述元件晶粒，其中所述支撐基底形成所述封裝的一部分。
  3. 如申請專利範圍第2項所述的封裝的形成方法，其中所述支撐基底為空白半導體基底。
  4. 如申請專利範圍第2項所述的封裝的形成方法，更包括將所述中介結構及所述第一包封材料鋸切為彼此分離的多個封裝，其中所述封裝為所述多個封裝中的一者，其中在所述鋸切中，所述支撐基底被鋸開。
  5. 如申請專利範圍第1項所述的封裝的形成方法，更包括： 以第二包封材料包封所述封裝；以及 在所述封裝上方形成重佈線且使所述重佈線電耦合至所述封裝。
  6. 如申請專利範圍第5項所述的封裝的形成方法，其中所述第一包封材料及所述第二包封材料具有不同的熱膨脹係數。
  7. 如申請專利範圍第5項所述的封裝的形成方法，更包括執行晶粒鋸切來鋸切所述第二包封材料。
  8. 如申請專利範圍第1項所述的封裝的形成方法，其中在以所述第一包封材料進行包封之前，並不對所述元件晶粒執行薄化。
  9. 一種封裝的形成方法，包括： 提供中介晶圓，所述中介晶圓包括： 半導體基底；以及 互連結構，位於所述半導體基底上方； 將多個元件晶粒接合至所述中介晶圓，其中將所述中介晶圓中的第一金屬墊接合至所述元件晶粒中的第二金屬墊，且將所述中介晶圓中的第一表面介電層接合至所述元件晶粒中的第二表面介電層； 以第一包封材料包封所述元件晶粒； 在所述元件晶粒上方形成導電特徵且使所述導電特徵電耦合至所述元件晶粒； 鋸切所述中介晶圓及所述第一包封材料以形成多個封裝； 以第二包封材料包封所述多個封裝中的一者； 形成與所述第二包封材料以及所述多個封裝中的所述一者重疊的重佈線；以及 鋸切所述第二包封材料以形成多個額外封裝。
  10. 如申請專利範圍第9項所述的封裝的形成方法，更包括： 將支撐基底附接至所述元件晶粒，其中當所述中介晶圓被鋸切時，所述支撐基底被鋸切於所述多個封裝中。
  11. 如申請專利範圍第10項所述的封裝的形成方法，其中所述支撐基底包括矽基底，且經由混合式接合將所述矽基底接合至所述多個元件晶粒的基底。
  12. 如申請專利範圍第9項所述的封裝的形成方法，其中所述第一包封材料及所述第二包封材料具有不同的熱膨脹係數。
  13. 如申請專利範圍第9項所述的封裝的形成方法，其中在以所述第一包封材料進行包封之前，並不對所述元件晶粒執行薄化。
  14. 如申請專利範圍第9項所述的封裝的形成方法，更包括在所述鋸切之前移除所述中介晶圓的所述半導體基底。
  15. 如申請專利範圍第9項所述的封裝的形成方法，其中所述中介晶圓包括穿孔，所述穿孔位於所述半導體基底中，且所述封裝的形成方法更包括： 在形成所述重佈線之前，研磨所述半導體基底以暴露出所述穿孔，其中所述重佈線電耦合至所述穿孔。
  16. 一種封裝，包括： 元件封裝，所述元件封裝包括： 中介結構； 元件晶粒，位於所述中介結構下方且接合至所述中介結構；以及 第一包封材料，包封所述元件晶粒，其中所述第一包封材料與所述中介結構的一部分重疊； 第二包封材料，包封所述元件封裝； 至少一介電層，重疊於所述第二包封材料及所述元件封裝；以及 導電特徵，位於所述至少一介電層中，其中所述導電特徵經由所述中介結構電耦合至所述元件晶粒。
  17. 如申請專利範圍第16項所述的封裝，其中所述中介結構中的第一金屬墊接合至所述元件晶粒中的第二金屬墊，且所述中介結構中的第一表面介電層接合至所述元件晶粒中的第二表面介電層。
  18. 如申請專利範圍第16項所述的封裝，更包括支撐基底，位於所述元件晶粒的半導體基底下方。
  19. 如申請專利範圍第16項所述的封裝，更包括介電緩衝層，位於所述第二包封材料下方且接觸所述第二包封材料。
  20. 如申請專利範圍第19項所述的封裝，更包括黏著膜，位於所述介電緩衝層上方且接觸所述介電緩衝層，其中所述黏著膜的邊緣與所述元件封裝的邊緣齊平。
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