CN113078148B - 半导体封装结构、方法、器件和电子产品 - Google Patents
半导体封装结构、方法、器件和电子产品 Download PDFInfo
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- CN113078148B CN113078148B CN202110269375.8A CN202110269375A CN113078148B CN 113078148 B CN113078148 B CN 113078148B CN 202110269375 A CN202110269375 A CN 202110269375A CN 113078148 B CN113078148 B CN 113078148B
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Abstract
本申请提供一种半导体封装结构、方法、器件和电子产品。该半导体封装结构中,被封装元件一一对应地固定在衬底上的凹槽内;被封装元件的有源表面背向衬底,被封装元件与其所处凹槽之间由绝缘材料隔开,各被封装元件均具有位于其有源表面上的第一焊盘,第一焊盘的上表面平齐;重布线层内导体之间由绝缘材料隔开,钝化层位于重布线层背向衬底一侧;衬底由半导体材料或绝缘材料形成,衬底与被封装元件内的半导体材料的热膨胀系数相同或相近,重布线层由晶圆制造工艺形成。该半导体封装结构翘曲程度小、可靠性高、工艺成熟、互连密度高,面积小。
Description
技术领域
本申请属于半导体制造技术领域,具体涉及一种半导体封装结构、方法、器件和电子产品。
背景技术
现有半导体封装制造工艺中,需要对被封装元件(例如是裸芯,也称die)进行封装,进而得到半导体器件。通常的工艺是将被封装元件固定在基板(substrate)、框架(leadframe)或转接板(interposer)上,然后再用互联和塑封等一系列工艺实现对被封装元件的包裹,从而得到封装好的半导体器件。
发明内容
本申请的目的在于提供一种半导体封装结构、方法、器件和电子产品。
为解决上述技术问题,本申请采用如下技术方案:一种半导体封装结构,包括:衬底、至少一个被封装元件、重布线层和钝化层,所述衬底上开设有至少一个凹槽,所述被封装元件一一对应地固定在所述凹槽内;
所述被封装元件的有源表面背向所述衬底,所述被封装元件与其所处凹槽之间由绝缘材料隔开,各所述被封装元件均具有位于其有源表面上的第一焊盘,全部所述第一焊盘的背向所述衬底的表面平齐;
所述重布线层位于所述被封装元件背向所述衬底一侧,所述重布线层的第一面上形成有多个第二焊盘,所述重布线层的与所述第一面相对的第二面上形成有多个第三焊盘,所述第二焊盘与所述第一焊盘一一对应地电接触,所述重布线层内的导体与导体之间由绝缘材料隔开,所述重布线层还具有电连接第二焊盘和第三焊盘的走线;
所述钝化层位于所述重布线层背向所述衬底一侧;
其中,所述衬底由半导体材料或绝缘材料形成,所述衬底与所述被封装元件内的半导体材料的热膨胀系数相同或相近,所述重布线层由晶圆制造工艺形成。
为解决上述技术问题,本申请采用如下技术方案:一种半导体封装方法,包括:
在衬底上形成至少一个凹槽;
将至少一个被封装元件一一对应地固定在所述凹槽内,其中,所述被封装元件的有源表面背向所述衬底,所述被封装元件与其所处凹槽之间由绝缘材料隔开,各所述被封装元件均具有位于其有源表面上的第一焊盘,全部所述第一焊盘的背向所述衬底的表面平齐;
形成暴露所述第一焊盘的平整表面;
采用晶圆制造工艺形成重布线层,所述重布线层的第一面上形成有多个第二焊盘,所述重布线层的与所述第一面相对的第二面上形成有多个第三焊盘,所述第二焊盘与所述第一焊盘一一对应地电接触,所述重布线层内的导体与导体之间由绝缘材料隔开,所述重布线层还具有电连接第二焊盘和第三焊盘的走线;
形成钝化层;
其中,所述衬底由半导体材料或绝缘材料形成,所述衬底与所述被封装元件内的半导体材料的热膨胀系数相同或相近。
为解决上述技术问题,本申请采用如下技术方案:一种半导体器件,包括:前述的半导体封装结构。
为解决上述技术问题,本申请采用如下技术方案:一种电子产品,包括:前述的半导体器件。
与现有技术相比,本申请的有益效果为:
由于被封装元件内的半导体材料和衬底的热膨胀系数相等或接近(例如二者由相同的半导体材料构成),所述重布线层内至少一种绝缘材料与所述被封装元件内的绝缘材料的热膨胀系数相同或相近,封装完成之后,半导体封装结构随温度变化而产生的翘曲度相对更小,有利于提高半导体器件的良率以及电学和机械上的可靠性。同时,在一些实施例中,半导体衬底比传统封装形式的模塑材料散热性好。
进一步,由于重布线层通过现有的半导体制造工艺(FAB工艺、晶圆制造工艺)形成重布线层,不仅制造工艺成熟,而且重布线层内的线宽更细且线距更小,从而使得互连密度更高,半导体封装结构面积更小。
附图说明
图1a和图1b是根据本申请实施例的两种半导体封装结构的结构示意图。
图2是根据本申请实施例的半导体封装方法的流程示意图。
图3a至图3g是图1a所示半导体封装结构在封装的不同阶段的产品状态示意图。
图4a至图4g是图1b所示半导体封装结构在封装的不同阶段的产品状态示意图。
其中,1、衬底;10、凹槽;111、112、绝缘材料;21、22、被封装元件;211、221、第一焊盘;3、重布线层;31、第二焊盘;32、第三焊盘;33、走线;4、钝化层;5、电极结构。
具体实施方式
在本申请中,应理解,诸如“包括”或“具有”等术语旨在指示本说明书中存在所公开的特征、数字、步骤、行为、部件、部分或其组合的存在,但是并不排除存在一个或多个其他特征、数字、步骤、行为、部件、部分或其组合存在的可能性。
另外还需要说明的是,在不冲突的情况下,本申请中的实施例及实施例中的特征可以相互组合。下面将参考附图并结合实施例来详细说明本申请。
下面结合附图所示的实施例对本申请作进一步说明。
本申请的实施例提供一种半导体封装结构,包括:衬底、至少一个被封装元件、重布线层和钝化层,衬底上开设有至少一个凹槽,被封装元件一一对应地固定在凹槽内;被封装元件的有源表面背向衬底,被封装元件与其所处凹槽之间由绝缘材料隔开,各被封装元件均具有位于其有源表面上的第一焊盘,全部第一焊盘的背向衬底的表面平齐;重布线层位于被封装元件背向衬底一侧,重布线层的第一面上形成有多个第二焊盘,重布线层的与第一面相对的第二面上形成有多个第三焊盘,第二焊盘与第一焊盘一一对应地电接触,所述重布线层内的导体与导体之间由绝缘材料隔开,重布线层还具有电连接第二焊盘和第三焊盘的走线;钝化层位于重布线层背向衬底一侧;其中,所述衬底由半导体材料或绝缘材料形成,所述衬底与所述被封装元件内的半导体材料的热膨胀系数相同或相近,所述重布线层由晶圆制造工艺形成。
这些实施例中,被封装元件是放置在衬底上形成的凹槽内的,被封装元件上方是被重布线层所覆盖的。衬底、被封装元件内的基础材料都是热膨胀系数相同或相近的半导体材料或者绝缘材料。
本申请中“相同的半导体材料”指的是它们的化学成分是相同的,例如都是硅材料形成的,或者都是由砷化镓材料形成的。但并不限定这些半导体材料的纯度或者密度或者结晶状态等完全一致。
例如,所述衬底内的半导体材料与所述被封装元件内的半导体材料相同。
又例如,所述被封装元件内的半导体材料为硅或砷化镓,并且所述衬底的材料为工程耐热玻璃。它们的热膨胀系数为同一数量级。
本申请中,两种材料的热膨胀系数相近,指的是二者的差与二者中绝对值较小一者的比值的绝对值小于9。
重布线层内包含至少一层金属走线、以及包含连接不同层金属走线(如果有多层金属走线)、连接金属走线与第二焊盘的过孔、连接金属走线与第三焊盘的过孔。重布线层内的走线可以实现第二焊盘与第三焊盘的互连,第二焊盘与第二焊盘的互连、第三焊盘与第三焊盘的互连。
由于被封装元件和衬底的热膨胀系数相同或者相近,封装完成之后,半导体器件随温度变化而产生的翘曲度相对更小,有利于提高半导体封装结构的良率以及电学和机械上的可靠性。同时,半导体衬底比传统封装形式的模塑材料散热性好。
进一步,由于重布线层能够通过现有的半导体制造工艺(FAB工艺、晶圆制造工艺)形成重布线层。不仅制造工艺成熟,而且重布线层内的线宽更细且线距更小,从而使得互连密度更高,半导体封装结构面积更小。
具体地,重布线层内的走线以及第二焊盘、第三焊盘可由沉积、光刻、刻蚀的工艺形成。重布线层内的绝缘材料可通过沉积的工艺形成。通常,重布线层内的绝缘材料为无机绝缘材料。重布线层内的绝缘材料选取能够用于制造晶圆(例如能够用于制造裸芯)的绝缘材料。
在一些实施例中,所述被封装元件内的绝缘材料以及所述重布线层内的绝缘材料的热膨胀系数相同或相近。
例如,所述重布线层内的绝缘材料和所述被封装元件内的绝缘材料均包含二氧化硅或均包含氮化硅。
重布线层与被封装元件的热膨胀特性更为接近,这进一步有利于防止半导体封装结构的翘曲。
当重布线层与被封装元件均包含相同的绝缘材料,形成被封装元件的工艺场所也可以用于形成重布线层。这进一步降低制作工艺的复杂度。
在一些实施例中,被封装元件呈裸芯的状态。
在一些实施例中,单个半导体封装结构中包含一个被封装元件。重布线层的作用仅是将被封装元件上的第一焊盘引出。
在一些实施例中,单个半导体封装结构中包含多个被封装元件。此时,重布线层内的线路可以起到多个被封装元件的第一焊盘之间信号互连的作用。
在一些实施例中,被封装元件的数量为多个且厚度相等,各凹槽的深度相等。
参考图1a和图3a,被封装元件21和被封装元件22的厚度相等,二者所处凹槽10的深度相等。
当然,被封装元件21和被封装元件22可以是相同的元件,也可以是不同的元件。由于被封装元件21和被封装元件22的厚度相等,各凹槽10可采用相同的开槽(比如刻蚀)工艺形成。
如这些被封装元件最初的厚度是不一致的,可以通过减薄的工艺使得它们的厚度相等。
当然,即使这些被封装元件21、22的最初的厚度是相等的,也可通过减薄的工艺使得它们的厚度减小并相等。如此,可以减少在衬底1中开设凹槽10的槽深。
在一些实施例中,被封装元件的数量为多个,且至少两个被封装元件的厚度不相等,其中,至少两个凹槽的深度不同,以使各被封装元件的第一焊盘的上表面平齐。
参考图1b和图4a,被封装元件21和被封装元件22的厚度不相等,二者所处凹槽10的深度也不相等。被封装元件21更厚,相应地,其所处的凹槽10的深度更深。
可以通过控制开槽工艺(比如分步刻蚀或二次刻蚀)形成不同深度的凹槽10。
在一些实施例中,钝化层覆盖重布线层上方的第三焊盘后,该半导体封装结构即可作为独立出售的产品。
在一些实施例中,参考图1a和图1b,半导体封装结构还包括位于钝化层4背向衬底1一侧的电极结构5,钝化层4上与第三焊盘32相对的区域开设有过孔,电极结构5与第三焊盘32一一对应,电极结构5通过过孔与对应第三焊盘32电连接。
具体地,电极结构5例如包含覆盖第三焊盘的凸点下金属(UBM),以及位于凸点下金属上方的焊锡球。当然,电极结构也可以是形成在第三焊盘上方的焊盘(Pad)。
在一些实施例中,被封装元件与所处凹槽的槽底之间由绝缘粘胶层隔开。即由绝缘粘胶层固定被封装元件,并实现被封装元件与凹槽槽底之间的绝缘。
在一些实施例中,被封装元件与所处凹槽的侧面之间由固化的树脂材料(例如是环氧树脂)或无机绝缘材料隔开。即可向被封装元件与所处凹槽之间的间隙填充并固化树脂材料,或者向该间隙沉积无机绝缘材料(例如是二氧化硅)。
参考图2,本申请的实施例还提供一种半导体封装方法。该封装方法能够制造得到前述实施例所提供的半导体封装结构。该制造方法包括以下步骤。
步骤1000、在衬底上形成至少一个凹槽;
步骤1001、将至少一个被封装元件一一对应地固定在凹槽内,其中,被封装元件的有源表面背向衬底,被封装元件与其所处凹槽之间由绝缘材料隔开,各被封装元件均具有位于其有源表面上的第一焊盘,全部第一焊盘的背向衬底的表面平齐;
步骤1002、形成暴露第一焊盘的平整表面;
步骤1003、采用晶圆制造工艺形成重布线层,重布线层的第一面上形成有多个第二焊盘,重布线层的与第一面相对的第二面上形成有多个第三焊盘,第二焊盘与第一焊盘一一对应地电接触,所述重布线层内的导体与导体之间由绝缘材料隔开,所述重布线层还具有电连接第二焊盘和第三焊盘的走线;
步骤1004、形成钝化层;
其中,衬底由半导体材料或者绝缘材料形成,衬底材料是与被封装元件内的半导体材料为热膨胀系数相同或者相近的材料。
由于被封装元件和衬底由热膨胀系数相同或者相近材料构成,封装完成之后,半导体器件随温度变化而产生的翘曲度相对更小,有利于提高半导体器件的良率以及电学和机械上的可靠性。
进一步,由于重布线层通过半导体制造工艺(FAB工艺)形成。例如可采用沉积、光刻、刻蚀等工艺形成重布线层内的走线和电极,以及通过沉积的工艺形成绝缘材料层。这不仅制造工艺成熟,而且重布线层内的线宽更细且线距更小,从而使得互连密度更高,半导体封装结构面积更小。
在一些实施例中,所述衬底内的半导体材料与所述被封装元件内的半导体材料相同。
在一些实施例中,所述被封装元件内的半导体材料为硅或砷化镓,并且所述衬底的材料为工程耐热玻璃。
在一些实施例中,所述被封装元件内的绝缘材料以及所述重布线层内的绝缘材料的热膨胀系数相同或相近。
例如,所述重布线层内的绝缘材料和所述被封装元件内的绝缘材料均包含二氧化硅或均包含多晶硅。
由于重布线层与被封装元件均包含热膨胀系数相同或者相近的绝缘材料,重布线层与被封装元件的热膨胀特性也更为接近,这进一步有利于防止半导体封装结构的翘曲。
在一些实施例中,该封装方法还包括:
步骤1005、在钝化层上形成至少一个过孔,过孔与第三焊盘一一对应,过孔暴露对应的第三焊盘;
步骤1006、在第三焊盘上形成与其电接触的电极结构。
在一些实施例中,被封装元件的数量为多个,其所处凹槽的深度相同,该封装方法还包括:对至少部分被封装元件进行减薄,以使各被封装元件的厚度相等。
在一些实施例中,被封装元件的数量为多个,且至少两个被封装元件的厚度不相等,在衬底上形成凹槽时,至少两个凹槽的深度是不等的,以使各被封装元件的第一焊盘的上表面平齐。
在一些实施例中,将至少一个被封装元件一一对应地固定在凹槽内,包括:
在凹槽的槽底所形成绝缘粘胶层;
将被封装元件粘贴在绝缘粘胶上,其中,被封装元件与所处凹槽的侧面之间留有空隙;
向被封装元件与对应的凹槽的侧面之间填充绝缘材料。
在一些实施例中,向被封装元件与对应的凹槽侧面之间填充绝缘材料,包括:
向被封装元件与对应的凹槽侧面之间填充并固化树脂材料,或向被封装元件与对应的凹槽侧面之间的空隙沉积无机氧化物绝缘材料。
在一些实施例中,形成暴露第一焊盘的平整表面,包括:通过磨削工艺去除高出第一焊盘的绝缘材料以及衬底材料,随后进行表面处理。
在一些实施例中,衬底的面积较大,其实可以形成大量的凹槽。该制造还包括:通过切割工艺得到多个半导体封装结构,其中,每个半导体封装结构至少包含:一个被封装元件、所含被封装元件所处的凹槽、与所含被封装元件电连接的重布线层、以及所含重布线层上方的钝化层。
在一些实施例中,被封装元件呈裸芯的状态。
在一些实施例中,参考图3a至图3g以及图1a,半导体器件的封装方法的具体实现过程如下。
第一步,参考图3a,采用刻蚀的工艺在衬底1上形成多个凹槽10,多个凹槽10的深度相等。
第二步,参考图3b,在凹槽10的槽底形成绝缘粘胶层111。
第三步,参考图3c,将被封装元件21和被封装元件22分别放在一个凹槽10内,并粘贴在绝缘粘胶111上,其中,被封装元件21的第一焊盘211和被封装元件22的第一焊盘221朝上,被封装元件21和被封装元件22的厚度相等。被封装元件21和22二者均与所处凹槽10的侧壁之间留有间距。
第四步,参考图3d,向凹槽10内填充并固化绝缘材料112。例如是将液态状的环氧树脂滴入凹槽10与被封装元件21、22之间的缝隙,并通过加热固化环氧树脂。或者向凹槽10与被封装元件21、22的缝隙沉积无机绝缘材料(例如是二氧化硅)。
第五步,参考图3e,磨削去除高出第一焊盘211、221的绝缘材料112以及高出第一焊盘211、221的衬底材料,在进行诸如化学清洗、抛光等的表面处理工艺,得到暴露第一焊盘211、221的平整表面。
第六步,参考图3f,在这个平整表面上形成重布线层3,重布线层3的第二焊盘31分别与第一焊盘211、221实现电接触,重布线层3的第三焊盘32与第二焊盘31进行互连。
具体地,可通过溅射或电镀、以及光刻、刻蚀、清洗等的图形化工艺形成第二焊盘31的图案,然后通过沉积等FAB工艺形成绝缘材料层(例如是二氧化硅层),再在绝缘材料层形成暴露第二焊盘31的过孔,然后通过溅射或电镀、图形化的工艺形成连接第二焊盘31的走线33,之后再沉积形成另一侧绝缘材料层;再次形成一层走线33和一层绝缘材料层;随后在最新得到绝缘材料层中形成暴露下层走线33的过孔,最后再经溅射、电镀和图形化的工艺得到第三焊盘32的图案。
当然,也可以首先采用构图工艺形成第二焊盘31的图案,然后形成绝缘材料层,再在绝缘材料层中形成暴露第二焊盘31的过孔,然后形成第一层走线33的图案。
本领域技术人员可以依据现有技术制备重布线层。
以上方式中,制作重布线层的工艺与制作裸芯的工艺是相同的。该重布线层中有多层走线33。
第七步,参考图3g,在重布线层3上形成钝化层4。钝化层4的材料例如可以是硅的氮化物或者聚酰亚胺(polyimide)等材料。钝化层4起到保护其下方元件的作用。
第八步,参考图1a,在钝化层4上刻蚀出过孔,从而暴露各个第三焊盘32,在第三焊盘32上形成电极结构5。电极结构5例如包括第三焊盘32上方的凸点下金属(UBM)以及凸点下金属上方的焊锡球,当然,电极结构5也可以是焊盘(Pad)的形态。
在一些实施例中,参考图4a至图4g以及图1b,半导体器件的封装方法的具体实现过程如下。
第一步,参考图4a,控制开槽工艺(比如分步刻蚀或二次刻蚀)在衬底1上形成多个凹槽10,多个凹槽10的深度不等。
第二步,参考图4b,在凹槽10的槽底形成绝缘粘胶层111。
第三步,参考图4c,将被封装元件21和被封装元件22分别放在一个凹槽10内,并粘贴在绝缘粘胶111上,其中,被封装元件21的第一焊盘211和被封装元件22的第一焊盘221朝上且平齐,被封装元件21和被封装元件22的厚度不相等。
第四步,参考图4d,向凹槽10内填充并固化绝缘材料112。例如是将液态状的环氧树脂滴入凹槽10与被封装元件21、22之间的缝隙,并通过加热固化环氧树脂;或者向凹槽10与被封装元件21、22的缝隙沉积无机绝缘材料(例如是二氧化硅)。
第五步,参考图4e,磨削去除高出第一焊盘211、221的绝缘材料以及高出第一焊盘211、221的衬底材料,在进行诸如化学清洗、抛光等的表面处理工艺,得到暴露第一焊盘211、221的平整表面。
第六步,参考图4f,在这个平整表面上形成重布线层3,重布线层3的第二焊盘31分别与第一焊盘211、221实现电接触,重布线层3的第三焊盘32与第二焊盘31进行互连。
具体地,可通过溅射或电镀、以及光刻、刻蚀、清洗等的图形化工艺形成第二焊盘31的图案,然后通过沉积等FAB工艺形成绝缘材料层(例如是二氧化硅层),再在绝缘材料层形成暴露第二焊盘31的过孔,然后通过溅射或电镀、以及图形化的工艺形成连接第二焊盘31的走线33,之后再沉积形成另一侧绝缘材料层;随后在最新得到绝缘材料层中形成暴露下层走线33的过孔,最后再经溅射或电镀、以及图形化的工艺得到第三焊盘32的图案。
以上方式中,制作重布线层的工艺与制作裸芯的工艺是相同的。该重布线层中包含至少一层走线33。
第七步,参考图4g,在重布线层3上形成钝化层4。钝化层4的材料例如可以是硅的氮化物或者聚酰亚胺(polyimide)等材料。钝化层4起到保护其下方元件的作用。
第八步,参考图4a,在钝化层4上刻蚀出过孔,从而暴露各个第三焊盘32,在第三焊盘32上形成电极结构5。电极结构5例如包括第三焊盘32上方的凸点下金属(UBM)以及凸点下金属上方的焊锡球,电极结构5也可以是焊盘(Bonding Pad)。
本申请的实施例还提供一种半导体器件,包括前述的半导体封装结构。即可以对前述的半导体封装结构进行进一步加工,例如是和其他的半导体封装结构组合成组件或模组。
本申请的实施例还提供一种电子产品,包括:前述的半导体器件。电子产品例如是手机、电脑、服务器、智能手表等各种类型的电子产品。
得益于上述半导体封装结构的稳定性的提升,这些半导体器件、电子产品的稳定性也相应得到提升。
本申请中的各个实施例均采用递进的方式描述,各个实施例之间相同相似的部分互相参见即可,每个实施例重点说明的都是与其他实施例的不同之处。
本申请的保护范围不限于上述的实施例,显然,本领域的技术人员可以对本申请进行各种改动和变形而不脱离本申请的范围和精神。倘若这些改动和变形属于本申请权利要求及其等同技术的范围,则本申请的意图也包含这些改动和变形在内。
Claims (27)
1.一种半导体封装结构,其特征在于,包括:衬底、至少一个被封装元件、重布线层和钝化层,所述衬底上开设有至少一个凹槽,所述被封装元件一一对应地固定在所述凹槽内;
所述被封装元件的有源表面背向所述衬底,所述被封装元件与其所处凹槽之间由绝缘材料隔开,各所述被封装元件均具有位于其有源表面上的第一焊盘,全部所述第一焊盘的背向所述衬底的表面平齐;
所述重布线层位于所述被封装元件背向所述衬底一侧,所述重布线层的第一面上形成有多个第二焊盘,所述重布线层的与所述第一面相对的第二面上形成有多个第三焊盘,所述第二焊盘与所述第一焊盘一一对应地电接触,所述重布线层内的导体与导体之间由绝缘材料隔开,所述重布线层还具有电连接第二焊盘和第三焊盘的走线;
所述钝化层位于所述重布线层背向所述衬底一侧;
其中,所述衬底由半导体材料或绝缘材料形成,所述衬底与所述被封装元件内的半导体材料的热膨胀系数相同或相近,所述重布线层由晶圆制造工艺形成。
2.根据权利要求1所述的半导体封装结构,其特征在于,所述衬底内的半导体材料与所述被封装元件内的半导体材料相同。
3.根据权利要求1所述的半导体封装结构,其特征在于,所述被封装元件内的半导体材料为硅或砷化镓,并且所述衬底的材料为工程耐热玻璃。
4.根据权利要求1所述的半导体封装结构,其特征在于,所述被封装元件内的绝缘材料以及所述重布线层内的绝缘材料的热膨胀系数相同或相近。
5.根据权利要求4所述的半导体封装结构,其特征在于,所述重布线层内的绝缘材料和所述被封装元件内的绝缘材料均包含二氧化硅或均包含多晶硅。
6.根据权利要求1所述的半导体封装结构,其特征在于,所述被封装元件的数量为多个且厚度相等,各所述凹槽的深度相等。
7.根据权利要求1所述的半导体封装结构,其特征在于,所述被封装元件的数量为多个,且至少两个被封装元件的厚度不相等,其中,至少两个凹槽的深度不同,以使各所述被封装元件的第一焊盘的上表面平齐。
8.根据权利要求1所述的半导体封装结构,其特征在于,还包括位于所述钝化层背向所述衬底一侧的电极结构,所述钝化层上与所述第三焊盘相对的区域开设有过孔,所述电极结构与所述第三焊盘一一对应,所述电极结构通过所述过孔与对应第三焊盘电连接。
9.根据权利要求1所述的半导体封装结构,其特征在于,所述被封装元件呈裸芯的状态。
10.根据权利要求1所述的半导体封装结构,其特征在于,所述被封装元件与所处凹槽的槽底之间由绝缘粘胶层隔开。
11.根据权利要求1所述的半导体封装结构,其特征在于,所述被封装元件与所处凹槽的侧面之间由固化的树脂材料或无机绝缘材料隔开。
12.一种半导体封装方法,其特征在于,包括:
在衬底上形成至少一个凹槽;
将至少一个被封装元件一一对应地固定在所述凹槽内,其中,所述被封装元件的有源表面背向所述衬底,所述被封装元件与其所处凹槽之间由绝缘材料隔开,各所述被封装元件均具有位于其有源表面上的第一焊盘,全部所述第一焊盘的背向所述衬底的表面平齐;
形成暴露所述第一焊盘的平整表面;
采用晶圆制造工艺形成重布线层,所述重布线层的第一面上形成有多个第二焊盘,所述重布线层的与所述第一面相对的第二面上形成有多个第三焊盘,所述第二焊盘与所述第一焊盘一一对应地电接触,所述重布线层内的导体与导体之间由绝缘材料隔开,所述重布线层还具有电连接第二焊盘和第三焊盘的走线;
形成钝化层;
其中,所述衬底由半导体材料或绝缘材料形成,所述衬底与所述被封装元件内的半导体材料的热膨胀系数相同或相近。
13.根据权利要求12所述的方法,其特征在于,所述衬底内的半导体材料与所述被封装元件内的半导体材料相同。
14.根据权利要求12所述的方法,其特征在于,所述被封装元件内的半导体材料为硅或砷化镓,并且所述衬底的材料为工程耐热玻璃。
15.根据权利要求12所述的方法,其特征在于,所述被封装元件内的绝缘材料以及所述重布线层内的绝缘材料的热膨胀系数相同或相近。
16.根据权利要求15所述的方法,其特征在于,所述重布线层内的绝缘材料和所述被封装元件内的绝缘材料均包含二氧化硅或均包含多晶硅。
17.根据权利要求12所述的方法,其特征在于,形成重布线层的步骤中,采用沉积工艺形成其内的无机绝缘材料。
18.根据权利要求12所述的方法,其特征在于,所述被封装元件的数量为多个,其所处凹槽的深度相同,所述方法还包括:对至少部分被封装元件进行减薄,以使各被封装元件的厚度相等。
19.根据权利要求12所述的方法,其特征在于,所述被封装元件的数量为多个,且至少两个被封装元件的厚度不相等,在所述衬底上形成凹槽时,至少两个凹槽的深度是不等的,以使各所述被封装元件的第一焊盘的上表面平齐。
20.根据权利要求12所述的方法,其特征在于,将至少一个被封装元件一一对应地固定在所述凹槽内,包括:
在所述凹槽的槽底所形成绝缘粘胶层;
将所述被封装元件粘贴在所述绝缘粘胶上,其中,所述被封装元件与所处凹槽的侧面之间留有空隙;
向所述被封装元件与对应的凹槽的侧面之间填充绝缘材料。
21.根据权利要求20所述的方法,其特征在于,向所述被封装元件与对应的凹槽侧面之间填充绝缘材料,包括:
向所述被封装元件与对应的凹槽侧面之间填充并固化树脂材料,或向所述被封装元件与对应的凹槽侧面之间的空隙沉积无机氧化物绝缘材料。
22.根据权利要求12所述的方法,其特征在于,形成暴露所述第一焊盘的平整表面,包括:
通过磨削工艺去除高出所述第一焊盘的绝缘材料以及衬底材料,随后进行表面处理。
23.根据权利要求12所述的方法,其特征在于,还包括:
在所述钝化层上形成至少一个过孔,所述过孔与所述第三焊盘一一对应,所述过孔暴露对应的第三焊盘;
在所述第三焊盘上形成与其电接触的电极结构。
24.根据权利要求12或23所述的方法,其特征在于,还包括:
通过切割工艺得到多个半导体封装结构,其中,每个半导体封装结构至少包含:一个所述被封装元件、所含被封装元件所处的凹槽、与所含被封装元件电连接的重布线层、以及所含重布线层上方的钝化层。
25.根据权利要求12所述的方法,其特征在于,所述被封装元件呈裸芯的状态。
26.一种半导体器件,其特征在于,包括:根据权利要求1至11任意一项所述的半导体封装结构。
27.一种电子产品,其特征在于,包括:根据权利要求26所述的半导体器件。
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CN202110269375.8A CN113078148B (zh) | 2021-03-12 | 2021-03-12 | 半导体封装结构、方法、器件和电子产品 |
TW111104270A TWI821894B (zh) | 2021-03-12 | 2022-02-07 | 半導體封裝結構、方法、器件和電子產品 |
KR1020220030520A KR102647093B1 (ko) | 2021-03-12 | 2022-03-11 | 반도체 패키지 구조, 방법, 소자 및 전자 제품 |
US17/693,357 US20220293504A1 (en) | 2021-03-12 | 2022-03-12 | Semiconductor packaging structure, method, device and electronic product |
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TW202236574A (zh) | 2022-09-16 |
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