TWI821894B - 半導體封裝結構、方法、器件和電子產品 - Google Patents
半導體封裝結構、方法、器件和電子產品 Download PDFInfo
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- TWI821894B TWI821894B TW111104270A TW111104270A TWI821894B TW I821894 B TWI821894 B TW I821894B TW 111104270 A TW111104270 A TW 111104270A TW 111104270 A TW111104270 A TW 111104270A TW I821894 B TWI821894 B TW I821894B
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- insulating material
- semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 102
- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 60
- 239000011810 insulating material Substances 0.000 claims abstract description 77
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- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 4
- 239000000853 adhesive Substances 0.000 claims description 4
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Abstract
本申請提供一種半導體封裝結構、方法、器件和電子產品。該半導體封裝結構中,被封裝元件一一對應地固定在襯底上的凹槽內;被封裝元件的有源表面背向襯底,被封裝元件與其所處凹槽之間由絕緣材料隔開,各被封裝元件均具有位於其有源表面上的第一焊盤,第一焊盤的上表面平齊;重佈線層內導體之間由絕緣材料隔開,鈍化層位於重佈線層背向襯底一側;襯底由半導體材料或絕緣材料形成,襯底與被封裝元件內的半導體材料的熱膨脹係數相同或相近,重佈線層由晶圓製造工藝形成。該半導體封裝結構翹曲程度小、可靠性高、工藝成熟、互連密度高,面積小。
Description
本申請屬於半導體製造技術領域,具體涉及一種半導體封裝結構、方法、器件和電子產品。
現有半導體封裝製造工藝中,需要對被封裝元件(例如是裸芯,也稱die)進行封裝,進而得到半導體器件。通常的工藝是將被封裝元件固定在基板(substrate)、框架(leadframe)或轉接板(interposer)上,然後再用互聯和塑封等一系列工藝實現對被封裝元件的包裹,從而得到封裝好的半導體器件。
本申請的目的在於提供一種半導體封裝結構、方法、器件和電子產品。
為解決上述技術問題,本申請採用如下技術方案:一種半導體封裝結構,包括:襯底、至少一個被封裝元件、重佈線層和鈍化層,所述襯底上開設有至少一個凹槽,所述被封裝元件一一對應地固定在所述凹槽內;
所述被封裝元件的有源表面背向所述襯底,所述被封裝元件與其所處凹槽之間由絕緣材料隔開,各所述被封裝元件均具有位於其有源表面上的第一焊盤,全部所述第一焊盤的背向所述襯底的表面平齊;
所述重佈線層位於所述被封裝元件背向所述襯底一側,所述重佈線層的第一面上形成有多個第二焊盤,所述重佈線層的與所述第一面相對的第二面上形成有多個第三焊盤,所述第二焊盤與所述第一焊盤一一對應地電接觸,所述重佈線層內的導體與導體之間由絕緣材料隔開,所述重佈線層還具有電連接第二焊盤和第三焊盤的走線;
所述鈍化層位於所述重佈線層背向所述襯底一側;
其中,所述襯底由半導體材料或絕緣材料形成,所述襯底與所述被封裝元件內的半導體材料的熱膨脹係數相同或相近,所述重佈線層由晶圓製造工藝形成。
為解決上述技術問題,本申請採用如下技術方案:一種半導體封裝方法,包括:
在襯底上形成至少一個凹槽;
將至少一個被封裝元件一一對應地固定在所述凹槽內,其中,所述被封裝元件的有源表面背向所述襯底,所述被封裝元件與其所處凹槽之間由絕緣材料隔開,各所述被封裝元件均具有位於其有源表面上的第一焊盤,全部所述第一焊盤的背向所述襯底的表面平齊;
形成曝露所述第一焊盤的平整表面;
採用晶圓製造工藝形成重佈線層,所述重佈線層的第一面上形成有多個第二焊盤,所述重佈線層的與所述第一面相對的第二面上形成有多個第三焊盤,所述第二焊盤與所述第一焊盤一一對應地電接觸,所述重佈線層內的導體與導體之間由絕緣材料隔開,所述重佈線層還具有電連接第二焊盤和第三焊盤的走線;
形成鈍化層;
其中,所述襯底由半導體材料或絕緣材料形成,所述襯底與所述被封裝元件內的半導體材料的熱膨脹係數相同或相近。
為解決上述技術問題,本申請採用如下技術方案:一種半導體器件,包括:前述的半導體封裝結構。
為解決上述技術問題,本申請採用如下技術方案:一種電子產品,包括:前述的半導體器件。
與現有技術相比,本申請的有益效果為:
由於被封裝元件內的半導體材料和襯底的熱膨脹係數相等或接近(例如二者由相同的半導體材料構成),所述重佈線層內至少一種絕緣材料與所述被封裝元件內的絕緣材料的熱膨脹係數相同或相近,封裝完成之後,半導體封裝結構隨溫度變化而產生的翹曲度相對更小,有利於提高半導體器件的良率以及電學和機械上的可靠性。同時,在一些實施例中,半導體襯底比傳統封裝形式的模塑材料散熱性好。
進一步,由於重佈線層通過現有的半導體製造工藝(FAB工藝、晶圓製造工藝)形成重佈線層,不僅製造工藝成熟,而且重佈線層內的線寬更細且線距更小,從而使得互連密度更高,半導體封裝結構面積更小。
在本申請中,應理解,諸如“包括”或“具有”等術語旨在指示本說明書中存在所公開的特徵、數位、步驟、行為、部件、部分或其組合的存在,但是並不排除存在一個或多個其他特徵、數位、步驟、行為、部件、部分或其組合存在的可能性。
另外還需要說明的是,在不衝突的情況下,本申請中的實施例及實施例中的特徵可以相互組合。下面將參考附圖並結合實施例來詳細說明本申請。
下面結合附圖所示的實施例對本申請作進一步說明。
本申請的實施例提供一種半導體封裝結構,包括:襯底、至少一個被封裝元件、重佈線層和鈍化層,襯底上開設有至少一個凹槽,被封裝元件一一對應地固定在凹槽內;被封裝元件的有源表面背向襯底,被封裝元件與其所處凹槽之間由絕緣材料隔開,各被封裝元件均具有位於其有源表面上的第一焊盤,全部第一焊盤的背向襯底的表面平齊;重佈線層位於被封裝元件背向襯底一側,重佈線層的第一面上形成有多個第二焊盤,重佈線層的與第一面相對的第二面上形成有多個第三焊盤,第二焊盤與第一焊盤一一對應地電接觸,所述重佈線層內的導體與導體之間由絕緣材料隔開,重佈線層還具有電連接第二焊盤和第三焊盤的走線;鈍化層位於重佈線層背向襯底一側;其中,所述襯底由半導體材料或絕緣材料形成,所述襯底與所述被封裝元件內的半導體材料的熱膨脹係數相同或相近,所述重佈線層由晶圓製造工藝形成。
這些實施例中,被封裝元件是放置在襯底上形成的凹槽內的,被封裝元件上方是被重佈線層所覆蓋的。襯底、被封裝元件內的基礎材料都是熱膨脹係數相同或相近的半導體材料或者絕緣材料。
本申請中“相同的半導體材料”指的是它們的化學成分是相同的,例如都是矽材料形成的,或者都是由砷化鎵材料形成的。但並不限定這些半導體材料的純度或者密度或者結晶狀態等完全一致。
例如,所述襯底內的半導體材料與所述被封裝元件內的半導體材料相同。
又例如,所述被封裝元件內的半導體材料為矽或砷化鎵,並且所述襯底的材料為工程耐熱玻璃。它們的熱膨脹係數為同一數量級。
本申請中,兩種材料的熱膨脹係數相近,指的是二者的差與二者中絕對值較小一者的比值的絕對值小於9。
重佈線層內包含至少一層金屬走線、以及包含連接不同層金屬走線(如果有多層金屬走線)、連接金屬走線與第二焊盤的過孔、連接金屬走線與第三焊盤的過孔。重佈線層內的走線可以實現第二焊盤與第三焊盤的互連,第二焊盤與第二焊盤的互連、第三焊盤與第三焊盤的互連。
由於被封裝元件和襯底的熱膨脹係數相同或者相近,封裝完成之後,半導體器件隨溫度變化而產生的翹曲度相對更小,有利於提高半導體封裝結構的良率以及電學和機械上的可靠性。同時,半導體襯底比傳統封裝形式的模塑材料散熱性好。
進一步,由於重佈線層能夠通過現有的半導體製造工藝(FAB工藝、晶圓製造工藝)形成重佈線層。不僅製造工藝成熟,而且重佈線層內的線寬更細且線距更小,從而使得互連密度更高,半導體封裝結構面積更小。
具體地,重佈線層內的走線以及第二焊盤、第三焊盤可由沉積、光刻、刻蝕的工藝形成。重佈線層內的絕緣材料可通過沉積的工藝形成。通常,重佈線層內的絕緣材料為無機絕緣材料。重佈線層內的絕緣材料選取能夠用於製造晶圓(例如能夠用於製造裸芯)的絕緣材料。
在一些實施例中,所述被封裝元件內的絕緣材料以及所述重佈線層內的絕緣材料的熱膨脹係數相同或相近。
例如,所述重佈線層內的絕緣材料和所述被封裝元件內的絕緣材料均包含二氧化矽或均包含氮化矽。
重佈線層與被封裝元件的熱膨脹特性更為接近,這進一步有利於防止半導體封裝結構的翹曲。
當重佈線層與被封裝元件均包含相同的絕緣材料,形成被封裝元件的工藝場所也可以用於形成重佈線層。這進一步降低製作工藝的複雜度。
在一些實施例中,被封裝元件呈裸芯的狀態。
在一些實施例中,單個半導體封裝結構中包含一個被封裝元件。重佈線層的作用僅是將被封裝元件上的第一焊盤引出。
在一些實施例中,單個半導體封裝結構中包含多個被封裝元件。此時,重佈線層內的線路可以起到多個被封裝元件的第一焊盤之間信號互連的作用。
在一些實施例中,被封裝元件的數量為多個且厚度相等,各凹槽的深度相等。
參考圖1a和圖3a,被封裝元件21和被封裝元件22的厚度相等,二者所處凹槽10的深度相等。
當然,被封裝元件21和被封裝元件22可以是相同的元件,也可以是不同的元件。由於被封裝元件21和被封裝元件22的厚度相等,各凹槽10可採用相同的開槽(比如刻蝕)工藝形成。
如這些被封裝元件最初的厚度是不一致的,可以通過減薄的工藝使得它們的厚度相等。
當然,即使這些被封裝元件21、22的最初的厚度是相等的,也可通過減薄的工藝使得它們的厚度減小並相等。如此,可以減少在襯底1中開設凹槽10的槽深。
在一些實施例中,被封裝元件的數量為多個,且至少兩個被封裝元件的厚度不相等,其中,至少兩個凹槽的深度不同,以使各被封裝元件的第一焊盤的上表面平齊。
參考圖1b和圖4a,被封裝元件21和被封裝元件22的厚度不相等,二者所處凹槽10的深度也不相等。被封裝元件21更厚,相應地,其所處的凹槽10的深度更深。
可以通過控制開槽工藝(比如分步刻蝕或二次刻蝕)形成不同深度的凹槽10。
在一些實施例中,鈍化層覆蓋重佈線層上方的第三焊盤後,該半導體封裝結構即可作為獨立出售的產品。
在一些實施例中,參考圖1a和圖1b,半導體封裝結構還包括位於鈍化層4背向襯底1一側的電極結構5,鈍化層4上與第三焊盤32相對的區域開設有過孔,電極結構5與第三焊盤32一一對應,電極結構5通過過孔與對應第三焊盤32電連接。
具體地,電極結構5例如包含覆蓋第三焊盤的凸點下金屬(UBM),以及位於凸點下金屬上方的焊錫球。當然,電極結構也可以是形成在第三焊盤上方的焊盤(Pad)。
在一些實施例中,被封裝元件與所處凹槽的槽底之間由絕緣黏膠層隔開。即由絕緣黏膠層固定被封裝元件,並實現被封裝元件與凹槽槽底之間的絕緣。
在一些實施例中,被封裝元件與所處凹槽的側面之間由固化的樹脂材料(例如是環氧樹脂)或無機絕緣材料隔開。即可向被封裝元件與所處凹槽之間的間隙填充並固化樹脂材料,或者向該間隙沉積無機絕緣材料(例如是二氧化矽)。
參考圖2,本申請的實施例還提供一種半導體封裝方法。該封裝方法能夠製造得到前述實施例所提供的半導體封裝結構。該製造方法包括以下步驟。
步驟1000、在襯底上形成至少一個凹槽;
步驟1001、將至少一個被封裝元件一一對應地固定在凹槽內,其中,被封裝元件的有源表面背向襯底,被封裝元件與其所處凹槽之間由絕緣材料隔開,各被封裝元件均具有位於其有源表面上的第一焊盤,全部第一焊盤的背向襯底的表面平齊;
步驟1002、形成曝露第一焊盤的平整表面;
步驟1003、採用晶圓製造工藝形成重佈線層,重佈線層的第一面上形成有多個第二焊盤,重佈線層的與第一面相對的第二面上形成有多個第三焊盤,第二焊盤與第一焊盤一一對應地電接觸,所述重佈線層內的導體與導體之間由絕緣材料隔開,所述重佈線層還具有電連接第二焊盤和第三焊盤的走線;
步驟1004、形成鈍化層;
其中,襯底由半導體材料或者絕緣材料形成,襯底材料是與被封裝元件內的半導體材料為熱膨脹係數相同或者相近的材料。
由於被封裝元件和襯底由熱膨脹係數相同或者相近材料構成,封裝完成之後,半導體器件隨溫度變化而產生的翹曲度相對更小,有利於提高半導體器件的良率以及電學和機械上的可靠性。
進一步,由於重佈線層通過半導體製造工藝(FAB工藝)形成。例如可採用沉積、光刻、刻蝕等工藝形成重佈線層內的走線和電極,以及通過沉積的工藝形成絕緣材料層。這不僅製造工藝成熟,而且重佈線層內的線寬更細且線距更小,從而使得互連密度更高,半導體封裝結構面積更小。
在一些實施例中,所述襯底內的半導體材料與所述被封裝元件內的半導體材料相同。
在一些實施例中,所述被封裝元件內的半導體材料為矽或砷化鎵,並且所述襯底的材料為工程耐熱玻璃。
在一些實施例中,所述被封裝元件內的絕緣材料以及所述重佈線層內的絕緣材料的熱膨脹係數相同或相近。
例如,所述重佈線層內的絕緣材料和所述被封裝元件內的絕緣材料均包含二氧化矽或均包含多晶矽。
由於重佈線層與被封裝元件均包含熱膨脹係數相同或者相近的絕緣材料,重佈線層與被封裝元件的熱膨脹特性也更為接近,這進一步有利於防止半導體封裝結構的翹曲。
在一些實施例中,該封裝方法還包括:
步驟1005、在鈍化層上形成至少一個過孔,過孔與第三焊盤一一對應,過孔曝露對應的第三焊盤;
步驟1006、在第三焊盤上形成與其電接觸的電極結構。
在一些實施例中,被封裝元件的數量為多個,其所處凹槽的深度相同,該封裝方法還包括:對至少部分被封裝元件進行減薄,以使各被封裝元件的厚度相等。
在一些實施例中,被封裝元件的數量為多個,且至少兩個被封裝元件的厚度不相等,在襯底上形成凹槽時,至少兩個凹槽的深度是不等的,以使各被封裝元件的第一焊盤的上表面平齊。
在一些實施例中,將至少一個被封裝元件一一對應地固定在凹槽內,包括:
在凹槽的槽底所形成絕緣黏膠層;
將被封裝元件黏貼在絕緣黏膠上,其中,被封裝元件與所處凹槽的側面之間留有空隙;
向被封裝元件與對應的凹槽的側面之間填充絕緣材料。
在一些實施例中,向被封裝元件與對應的凹槽側面之間填充絕緣材料,包括:
向被封裝元件與對應的凹槽側面之間填充並固化樹脂材料,或向被封裝元件與對應的凹槽側面之間的空隙沉積無機氧化物絕緣材料。
在一些實施例中,形成曝露第一焊盤的平整表面,包括:通過磨削工藝去除高出第一焊盤的絕緣材料以及襯底材料,隨後進行表面處理。
在一些實施例中,襯底的面積較大,其實可以形成大量的凹槽。該製造還包括:通過切割工藝得到多個半導體封裝結構,其中,每個半導體封裝結構至少包含:一個被封裝元件、所含被封裝元件所處的凹槽、與所含被封裝元件電連接的重佈線層、以及所含重佈線層上方的鈍化層。
在一些實施例中,被封裝元件呈裸芯的狀態。
在一些實施例中,參考圖3a至圖3g以及圖1a,半導體器件的封裝方法的具體實現過程如下。
第一步,參考圖3a,採用刻蝕的工藝在襯底1上形成多個凹槽10,多個凹槽10的深度相等。
第二步,參考圖3b,在凹槽10的槽底形成絕緣黏膠層111。
第三步,參考圖3c,將被封裝元件21和被封裝元件22分別放在一個凹槽10內,並黏貼在絕緣黏膠111上,其中,被封裝元件21的第一焊盤211和被封裝元件22的第一焊盤221朝上,被封裝元件21和被封裝元件22的厚度相等。被封裝元件21和22二者均與所處凹槽10的側壁之間留有間距。
第四步,參考圖3d,向凹槽10內填充並固化絕緣材料112。例如是將液態狀的環氧樹脂滴入凹槽10與被封裝元件21、22之間的縫隙,並通過加熱固化環氧樹脂。或者向凹槽10與被封裝元件21、22的縫隙沉積無機絕緣材料(例如是二氧化矽)。
第五步,參考圖3e,磨削去除高出第一焊盤211、221的絕緣材料112以及高出第一焊盤211、221的襯底材料,在進行諸如化學清洗、拋光等的表面處理工藝,得到曝露第一焊盤211、221的平整表面。
第六步,參考圖3f,在這個平整表面上形成重佈線層3,重佈線層3的第二電極31分別與第一焊盤211、221實現電接觸,重佈線層3的第三電極32與第二電極31進行互連。
具體地,可通過濺射或電鍍、以及光刻、刻蝕、清洗等的圖形化工藝形成第二電極31的圖案,然後通過沉積等FAB工藝形成絕緣材料層(例如是二氧化矽層),再在絕緣材料層形成曝露第二電極31的過孔,然後通過濺射或電鍍、圖形化的工藝形成連接第二電極31的走線33,之後再沉積形成另一側絕緣材料層;再次形成一層走線33和一層絕緣材料層;隨後在最新得到絕緣材料層中形成曝露下層走線33的過孔,最後再經濺射、電鍍和圖形化的工藝得到第三電極32的圖案。
當然,也可以首先採用構圖工藝形成第二焊盤31的圖案,然後形成絕緣材料層,再在絕緣材料層中形成曝露第二焊盤31的過孔,然後形成第一層走線33的圖案。
本領域技術人員可以依據現有技術製備重佈線層。
以上方式中,製作重佈線層的工藝與製作裸芯的工藝是相同的。該重佈線層中有多層走線33。
第七步,參考圖3g,在重佈線層3上形成鈍化層4。鈍化層4的材料例如可以是矽的氮化物或者聚醯亞胺(polyimide)等材料。鈍化層4起到保護其下方元件的作用。
第八步,參考圖1a,在鈍化層4上刻蝕出過孔,從而曝露各個第三電極32,在第三電極32上形成電極結構5。電極結構5例如包括第三電極32上方的凸點下金屬(UBM)以及凸點下金屬上方的焊錫球,當然,電極結構5也可以是焊盤(Pad)的形態。
在一些實施例中,參考圖4a至圖4g以及圖1b,半導體器件的封裝方法的具體實現過程如下。
第一步,參考圖4a,控制開槽工藝(比如分步刻蝕或二次刻蝕)在襯底1上形成多個凹槽10,多個凹槽10的深度不等。
第二步,參考圖4b,在凹槽10的槽底形成絕緣黏膠層111。
第三步,參考圖4c,將被封裝元件21和被封裝元件22分別放在一個凹槽10內,並黏貼在絕緣黏膠111上,其中,被封裝元件21的第一焊盤211和被封裝元件22的第一焊盤221朝上且平齊,被封裝元件21和被封裝元件22的厚度不相等。
第四步,參考圖4d,向凹槽10內填充並固化絕緣材料112。例如是將液態狀的環氧樹脂滴入凹槽10與被封裝元件21、22之間的縫隙,並通過加熱固化環氧樹脂;或者向凹槽10與被封裝元件21、22的縫隙沉積無機絕緣材料(例如是二氧化矽)。
第五步,參考圖4e,磨削去除高出第一焊盤211、221的絕緣材料以及高出第一焊盤211、221的襯底材料,在進行諸如化學清洗、拋光等的表面處理工藝,得到曝露第一焊盤211、221的平整表面。
第六步,參考圖4f,在這個平整表面上形成重佈線層3,重佈線層3的第二電極31分別與第一焊盤211、221實現電接觸,重佈線層3的第三電極32與第二電極31進行互連。
具體地,可通過濺射或電鍍、以及光刻、刻蝕、清洗等的圖形化工藝形成第二電極31的圖案,然後通過沉積等FAB工藝形成絕緣材料層(例如是二氧化矽層),再在絕緣材料層形成曝露第二電極31的過孔,然後通過濺射或電鍍、以及圖形化的工藝形成連接第二電極31的走線33,之後再沉積形成另一側絕緣材料層;隨後在最新得到絕緣材料層中形成曝露下層走線33的過孔,最後再經濺射或電鍍、以及圖形化的工藝得到第三電極32的圖案。
以上方式中,製作重佈線層的工藝與製作裸芯的工藝是相同的。該重佈線層中包含至少一層走線33。
第七步,參考圖4g,在重佈線層3上形成鈍化層4。鈍化層4的材料例如可以是矽的氮化物或者聚醯亞胺(polyimide)等材料。鈍化層4起到保護其下方元件的作用。
第八步,參考圖4a,在鈍化層4上刻蝕出過孔,從而曝露各個第三電極32,在第三電極32上形成電極結構5。電極結構5例如包括第三電極32上方的凸點下金屬(UBM)以及凸點下金屬上方的焊錫球,電極結構5也可以是焊盤(Bonding Pad)。
本申請的實施例還提供一種半導體器件,包括前述的半導體封裝結構。即可以對前述的半導體封裝結構進行進一步加工,例如是和其他的半導體封裝結構組合成元件或模組。
本申請的實施例還提供一種電子產品,包括:前述的半導體器件。電子產品例如是手機、電腦、伺服器、智慧手錶等各種類型的電子產品。
得益於上述半導體封裝結構的穩定性的提升,這些半導體器件、電子產品的穩定性也相應得到提升。
本申請中的各個實施例均採用遞進的方式描述,各個實施例之間相同相似的部分互相參見即可,每個實施例重點說明的都是與其他實施例的不同之處。
本申請的保護範圍不限於上述的實施例,顯然,本領域的技術人員可以對本申請進行各種改動和變形而不脫離本申請的範圍和精神。倘若這些改動和變形屬於本申請請求項及其等同技術的範圍,則本申請的意圖也包含這些改動和變形在內。
1:襯底
10:凹槽
111、112:絕緣材料
21、22:被封裝元件
211、221:第一焊盤
3:重佈線層
31:第二焊盤
32:第三焊盤
33:走線
4:鈍化層
5:電極結構
[圖1a和圖1b]是根據本申請實施例的兩種半導體封裝結構的結構示意圖。
[圖2]是根據本申請實施例的半導體封裝方法的流程示意圖。
[圖3a至圖3g]是圖1a所示半導體封裝結構在封裝的不同階段的產品狀態示意圖。
[圖4a至圖4g]是圖1b所示半導體封裝結構在封裝的不同階段的產品狀態示意圖。
1:襯底
111、112:絕緣材料
21、22:被封裝元件
211、221:第一焊盤
3:重佈線層
31:第二焊盤
32:第三焊盤
33:走線
4:鈍化層
5:電極結構
Claims (25)
- 一種半導體封裝結構,其特徵在於,包括:襯底、至少一個被封裝元件、重佈線層和鈍化層,所述襯底上開設有至少一個凹槽,所述被封裝元件一一對應地固定在所述凹槽內;所述被封裝元件的有源表面背向所述襯底,所述被封裝元件與其所處凹槽之間由絕緣材料隔開,各所述被封裝元件均具有位於其有源表面上的第一焊盤,全部所述第一焊盤的背向所述襯底的表面平齊;所述重佈線層位於所述被封裝元件背向所述襯底一側,所述重佈線層的第一面上形成有多個第二焊盤,所述重佈線層的與所述第一面相對的第二面上形成有多個第三焊盤,所述第二焊盤與所述第一焊盤一一對應地電接觸,所述重佈線層內的導體與導體之間由絕緣材料隔開,所述重佈線層還具有電連接第二焊盤和第三焊盤的走線;所述鈍化層位於所述重佈線層背向所述襯底一側;其中,所述襯底由半導體材料或絕緣材料形成,所述襯底與所述被封裝元件內的半導體材料的熱膨脹係數相同或相近,所述重佈線層由晶圓製造工藝形成;其中,所述被封裝元件的數量為多個,且至少兩個被封裝元件的厚度不相等,其中,至少兩個凹槽的深度不同,以使各所述被封裝元件的第一焊盤的上表面平齊。
- 如請求項1所述的半導體封裝結構,其中,所述襯底內的半導體材料與所述被封裝元件內的半導體材料相同。
- 如請求項1所述的半導體封裝結構,其中,所述被封裝元件內的半導體材料為矽或砷化鎵,並且所述襯底的材料為工程耐熱玻璃。
- 如請求項1所述的半導體封裝結構,其中,所述被封裝元件內的絕緣材料以及所述重佈線層內的絕緣材料的熱膨脹係數相同或相近。
- 如請求項4所述的半導體封裝結構,其中,所述重佈線層內的絕緣材料和所述被封裝元件內的絕緣材料均包含二氧化矽或均包含多晶矽。
- 如請求項1所述的半導體封裝結構,其中,所述被封裝元件的數量為多個且厚度相等,各所述凹槽的深度相等。
- 如請求項1所述的半導體封裝結構,其中,還包括位於所述鈍化層背向所述襯底一側的電極結構,所述鈍化層上與所述第三焊盤相對的區域開設有過孔,所述電極結構與所述第三焊盤一一對應,所述電極結構通過所述過孔與對應第三焊盤電連接。
- 如請求項1所述的半導體封裝結構,其中,所述被封裝元件呈裸芯的狀態。
- 如請求項1所述的半導體封裝結構,其中,所述被封裝元件與所處凹槽的槽底之間由絕緣黏膠層隔開。
- 如請求項1所述的半導體封裝結構,其中,所述被封裝元件與所處凹槽的側面之間由固化的樹脂材料或無機絕緣材料隔開。
- 一種半導體封裝方法,其特徵在於,包括:在襯底上形成至少一個凹槽;將至少一個被封裝元件一一對應地固定在所述凹槽內,其中,所述被封裝元件的有源表面背向所述襯底,所述被封裝元件與其所處凹槽之間由絕緣材料 隔開,各所述被封裝元件均具有位於其有源表面上的第一焊盤,全部所述第一焊盤的背向所述襯底的表面平齊;形成曝露所述第一焊盤的平整表面;採用晶圓製造工藝形成重佈線層,所述重佈線層的第一面上形成有多個第二焊盤,所述重佈線層的與所述第一面相對的第二面上形成有多個第三焊盤,所述第二焊盤與所述第一焊盤一一對應地電接觸,所述重佈線層內的導體與導體之間由絕緣材料隔開,所述重佈線層還具有電連接第二焊盤和第三焊盤的走線;形成鈍化層;其中,所述襯底由半導體材料或絕緣材料形成,所述襯底與所述被封裝元件內的半導體材料的熱膨脹係數相同或相近;其中,所述襯底內的半導體材料與所述被封裝元件內的半導體材料相同。
- 如請求項11所述的方法,其中,所述被封裝元件內的半導體材料為矽或砷化錄,並且所述襯底的材料為工程耐熱玻璃。
- 如請求項11所述的方法,其中,所述被封裝元件內的絕緣材料以及所述重佈線層內的絕緣材料的熱膨脹係數相同或相近。
- 如請求項13所述的方法,其中,所述重佈線層內的絕緣材料和所述被封裝元件內的絕緣材料均包含二氧化矽或均包含多晶矽。
- 如請求項11所述的方法,其中,形成重佈線層的步驟中,採用沉積工藝形成其內的無機絕緣材料。
- 如請求項11所述的方法,其中,所述被封裝元件的數量為多個,其所處凹槽的深度相同,所述方法還包括:對至少部分被封裝元件進行減薄,以使各被封裝元件的厚度相等。
- 如請求項11所述的方法,其中,所述被封裝元件的數量為多個,且至少兩個被封裝元件的厚度不相等,在所述襯底上形成凹槽時,至少兩個凹槽的深度是不等的,以使各所述被封裝元件的第一焊盤的上表面平齊。
- 如請求項11所述的方法,其中,將至少一個被封裝元件一一對應地固定在所述凹槽內,包括:在所述凹槽的槽底所形成絕緣黏膠層;將所述被封裝元件黏貼在所述絕緣黏膠上,其中,所述被封裝元件與所處凹槽的側面之間留有空隙;向所述被封裝元件與對應的凹槽的側面之間填充絕緣材料。
- 如請求項18所述的方法,其中,向所述被封裝元件與對應的凹槽側面之間填充絕緣材料,包括:向所述被封裝元件與對應的凹槽側面之間填充並固化樹脂材料,或向所述被封裝元件與對應的凹槽側面之間的空隙沉積無機氧化物絕緣材料。
- 如請求項11所述的方法,其中,形成曝露所述第一焊盤的平整表面,包括:通過磨削工藝去除高出所述第一焊盤的絕緣材料以及襯底材料,隨後進行表面處理,其中,所述表面處理包括以下工藝中的至少一項:化學清洗工藝和拋光工藝。
- 如請求項11所述的方法,其中,還包括: 在所述鈍化層上形成至少一個過孔,所述過孔與所述第三焊盤一一對應,所述過孔曝露對應的第三焊盤;在所述第三焊盤上形成與其電接觸的電極結構。
- 如請求項11或21所述的方法,其中,還包括:通過切割工藝得到多個半導體封裝結構,其中,每個半導體封裝結構至少包含:一個所述被封裝元件、所含被封裝元件所處的凹槽、與所含被封裝元件電連接的重佈線層、以及所含重佈線層上方的鈍化層。
- 如請求項11所述的方法,其中,所述被封裝元件呈裸芯的狀態。
- 一種半導體器件,其中,包括:如請求項1至10中任一項所述的半導體封裝結構。
- 一種電子產品,其中,包括:如請求項24所述的半導體器件。
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