TWI237352B - Warpage-preventing substrate - Google Patents

Abstract

A warpage-preventing substrate is provided. The substrate includes a core layer having a first surface and an opposed second surface. A first trace layer is formed on the first surface of the core layer. A second trace layer is formed on the second surface of the core layer. An insulating material layer is applied over the surfaces and the trace layers. Wherein, the thickness of the first and second trace layers are made to be in inverse proportion to the trace density of the same, and the thickness of the first trace layer is made to be in proportion to the thickness of the second trace layer. Thereby, to allow the shrinking stress generated in the first trace layer and that in the second trace layer, under a temperature variation, balance with each other. Moreover, the insulating material layer on the first surface of the core layer may have similar deformation to the insulating material layer on the second surface of the core layer, thereby assuring flatness of the substrate without being warped.

Description

1237352

1237352 V. Description of the invention (2) The thermal expansion coefficient (CTE) of the conductive trace and the solder resist is very different. This kind of substrate structure is liable to cause many problems under the temperature change in the manufacturing process. One of them is important This is the warpage of the substrate. Figures 1 A and 1 B show a substrate 1 that produces a surface curvature. The substrate 1 includes a core layer 10;-a metal layer 11 composed of most copper conductive traces formed on the core layer 10 Surface 12; —The lower metal layer 13 is composed of most copper conductive traces and is formed on the surface 1 4 below the core layer 10; an upper solder resist layer 15 is laid on the upper metal layer 11 to cover the conductivity Traces; and a solder resist layer 16 is laid down to the lower metal layer 13 to cover the conductive traces. As shown in Figure 1A, when the conductive trace density of the upper metal layer 11 is higher than that of the lower metal layer 13, the temperature changes during the manufacturing process, such as substrate baking, curing, (Curing), In the subsequent thermal cycle (Thermal Cyc 1 e) operation and other environments, when cooling, the upper metal layer 11 will generate a larger shrinkage force, so that the deformation of the lower solder resist layer 16 is larger than that of the upper solder resist layer 15 Then, the substrate 1 is slightly bent. Conversely, as shown in FIG. 1B, when the conductive trace density of the upper metal layer 11 is lower than that of the lower metal layer 13 and the substrate 1 is subjected to temperature changes, the lower metal layer 13 will have a larger amount of shrinkage. , Causing the substrate 1 to bend downward to deform and cause warpage. In order to solve the disadvantages caused by the difference in thermal expansion coefficients in the substrate structure, U.S. Patent No. 5, 4 7 3, 1 19 discloses a substrate with a stress absorption mechanism. As shown in Figure 2, the substrate 2 is based on a single floor (S υ ρ ρ 〇 r t Layer) or core layer 20, a stress-relieving layer (Stress-Relieving

] 7568 Fragments · ptd Page 7 1237352

1237352 V. Description of the invention (4) 3 4 to increase the strength of the substrate 3 1 supporting the wafer 35. In addition, when the wafer 35 is placed on the substrate 31, the copper mesh layer 34 is buried under the edge 36 of the wafer 35, and is stuck in the process of molding (m ο 1 ding). Prevent chip damage. However, the technical means of increasing the rigidity of the substrate by laying a copper mesh layer in the substrate will increase the restrictions and difficulties of the line layout (routabi 1 ty), which is not conducive to the development of the product. In summary, how to provide a simple process and also prevent the substrate from being subjected to the stress shrinkage effect caused by the difference in thermal expansion coefficients of the upper and lower layers of the substrate in the process environment of temperature rise and fall, thereby causing cracks in the solder bumps (crack). The substrate structure has become an urgent problem. [Summary of the Invention] In order to solve the shortcomings of the above-mentioned conventional technology, the main object of the present invention is to provide a substrate that prevents deformation. By forming copper layers with different thicknesses corresponding to the conductive trace density of the upper and lower layers of the substrate, this can be effectively avoided The substrate is warped to keep the substrate flat. Another object of the present invention is to provide a substrate that prevents deformation. By forming copper layers with different thicknesses corresponding to the conductive trace density of the upper and lower layers of the substrate, the substrate can be raised before increasing the thickness of the substrate, the production cost, and the difficulty of circuit layout , To effectively avoid warping the substrate to maintain the flatness of the substrate. To achieve the above and other objectives, the substrate for preventing deformation of the present invention includes: a core layer having a first surface and an opposite second surface; and a first circuit formed on the first surface of the core layer Layer; one formed in the

] 7568 石 夕 品 .ptd Page 9 1237352 5. Description of the invention (5) The second circuit layer on the second surface of the core layer; and an insulation property for covering the surfaces and the circuit layers respectively Material layer. Wherein, the thickness of the first circuit layer and the thickness of the second circuit layer are inversely proportional to the density of its wiring layout, and the thickness of the first circuit layer and the thickness of the second circuit layer form a proportional relationship. When the substrate is in a semiconductor packaging process environment such as substrate baking, encapsulation gel curing, and subsequent thermal cycling operations, the thickness of the first circuit layer and the second circuit layer are inversely proportional to the density of the circuit layout. The circuit layer generates shrinkage stresses that counter each other under temperature changes, and the deformation of the insulating material layer used to cover the surfaces and the conductive traces is equivalent, so it can effectively prevent the substrate from Deformation during the temperature change process to keep the substrate flat. Compared with the conventional substrate structure, the deformation-preventing substrate of the present invention can be raised without increasing the thickness of the substrate, the production cost, and the difficulty of circuit layout, so as to effectively avoid warping of the substrate and maintain the substrate flatness. [Embodiment] The following describes the embodiment of the present invention through specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention may also be implemented or applied by other different specific embodiments, and various details in this specification may also be based on different viewpoints and applications, and various modifications and changes may be made without departing from the spirit of the present invention. Please refer to FIG. 4. As shown in the figure, the substrate 40 of the present invention is mainly a package.

17568 硅 品 .ptd Page 10 1237552 V. Description of the invention (6) It includes an angry layer 41, a first circuit layer 42, a second circuit layer 43, and the first circuit layer 42 and the The insulating material layers 44 and 45 of the two circuit layers 43 are the core layer 41 having a first surface 41a and an opposite second surface 41b. The core layer 41 is made of epoxy resin (Epoxy Resin), polyimide resin (Polyimide), BT (Bismaleimide Trazine) resin, FR4 resin and other resin materials. Since the structure and manufacturing method of the core layer 41 are conventional technologies, they will not be repeated here. The first circuit layer 42 is at least one copper layer laminated on the first surface 41 a of the core layer 41. The first circuit layer 42 is exposed through conventional exposure (Exposing) and development (Development). And # etch (E t ch i ng) and other technologies pattern the first circuit layer 42, and a plurality of first conductive traces are formed at predetermined locations on the first surface 4 1 a of the core layer 41. 4 6. Each of the first conductive traces 4 6 has a terminal (welding finger) 4 6 a. The second circuit layer 4 3 is at least a copper layer laminated on the second surface 4 1 b of the core layer 41, and the second circuit layer 4 3 is also exposed through conventional exposure (Exposing), developing (Developing) ), Etching (Etching), etc. pattern the second circuit layer 43 (P a 11 erning), and a plurality of second conductive traces are formed at predetermined locations on the second surface 4 1 b of the core layer 41. Each of the second conductive traces 4 7 has a terminal (welding finger) 4 7 a. Compared with the conventional method of using a metal mesh to increase the rigidity of the substrate, the present invention is characterized in that the thickness of the first circuit layer 42 is the same as the density of the first conductive trace 46 formed on the first circuit layer 4 2. Inversely proportional; and the thickness of the second circuit layer 43 is dense with the second conductive trace 47 formed on the second circuit layer 43

] 7568 石 夕 品 .ptd Page 11 1237352-" " " " " ^^ V. Description of Invention (7) " --- Degrees are inversely proportional. At the same time, the thicknesses of the first circuit layer 42 and the second circuit layer 43 are in a proportional relationship. That is, 'the denser the distribution density of the first conductive trace 46 is, the thinner the thickness of the first line $ layer 4 2 is; The thicker the first wiring layer 42 is. Similarly, the denser the distribution density of the second conductive trace 47 is, the thinner the thickness of the second circuit layer 43 is. The relative is the denser the distribution density of the second conductive trace 47 is. The thickness of the second circuit layer 43 is thicker. In this embodiment, it is assumed that the first conductive trace 46 of the first circuit layer 42 is compared with the second conductive trace 47 of the second circuit layer 43.卩 is a bifurcation, the thickness of the first wiring layer 42 is thinner than that of the second wiring layer 43. Through such a technical means for controlling the thickness of the metal layer, the substrate 40 can be formed with the first circuit layer 42 and the second circuit layer of the first conductive trace 46 and the second conductive trace 47, respectively. The thermal stress of 43 is equivalent. In other words, 'in the process environment of increasing or decreasing temperature, the substrate 40 and the deformation phenomenon such as no warpage will occur, so as to achieve the purpose of maintaining product yield. It is not necessary to increase the rigidity of the substrate through the laying of the metal mesh layer, so it can reduce the restrictions and difficulties of the circuit layout (r o u t a b i 1 i t y). The insulating material layers 4 4 and 4 5 are respectively laid on the first surfaces 4 1 a and 4 1 b to the required layer 4 1, and 俾 covers the first conductive trace 46 and the first conductive trace. Trace 4 7 and expose the terminals 4 6 a and 4 7 a to the insulating material layers 4 4 and 4 5 respectively. In this embodiment, the insulating material layers 4 4 and 4 5 may be a solder mask layer. Through the covering of the insulating and destructive layer, it is possible to avoid external water vapor or pollutants on these metals. Invasion

17568 守 品 .ptd Page] 2 丄 237352 V. Description of the invention (8), and to prevent the short circuit caused by the exposed conductive trace in the subsequent process, which affects the electrical quality. Please refer to FIG. 5, which shows a semiconductor package 5 using a substrate 40 of the present invention. In this embodiment, the semiconductor package 5 is a Bal 1 Grid Array (BGA) type semiconductor package. It should be noted that the substrate 40 of the present invention can also be applied to other types of semiconductor packages such as a flip-chip (F 1 ip Ch ip) structure, and can also be used as a circuit board to carry the package. First, the substrate 40 is prepared, wherein the first surface 4 1 a is a crystal plane for receiving a wafer; and the second surface 41 b is a plant for soldering balls or bumps. Sphere. Second, a die bonding operation is performed to place at least one wafer 51 on the first surface 41 a of the substrate 40, and a majority of bonding wires 52 are formed through a wire bonding operation. In this embodiment, 'both ends of the bonding wire 5 2 are respectively soldered to the wafer 5 1 and the welding finger 4 6 a,' and the wafer 51 is electrically connected to the first surface 41 of the substrate 40. a on. Furthermore, a molding operation is performed to form an encapsulating gel 5 3 like epoxy resin on the first surface 4 1 a, so as to cover the wafer 40 and the bonding wire 5 2 to prevent isolation from the outside world. Damaged by external water vapor and / or pollutants. Then, a post molding curing (PMC) process is performed to cure the encapsulant 53. After the measurement, a Ball Implantation operation is performed to implant a large number of solder balls 5 4 on the terminal 4 7 a of the second surface 4 1 b of the substrate 40, 俾

1237352 V. Description of the invention (9) The chip 51 is electrically connected to an external device (not shown). In summary, the substrate for preventing deformation of the present invention can be raised before increasing the thickness of the substrate, the production cost and the layout of the circuit, so as to effectively prevent the substrate from warping and keep the substrate flat. The above-mentioned embodiments are merely illustrative for explaining the principle of the present invention and its effects, and are not intended to limit the present invention. Anyone skilled in the art can modify and change the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the rights of the present invention should be listed in the scope of patent application mentioned later.

] 7568δ 夕 品 .pid Page] 41237352 Brief Description of Drawings [Simplified Description of Drawings] Figures 1 A and 1 B are cross-sectional views of a conventional substrate structure that deforms under a temperature-varying environment; A cross-sectional view of the substrate disclosed in No. 5, 4 7 3, 11 9; FIG. 3 is a top view of the substrate structure in the semiconductor package disclosed in No. 6, 20, 4, 5 59; The drawing is a cross-sectional view of the substrate of the present invention, and FIG. 5 is a semiconductor package using the substrate of the present invention. 1 substrate 2 substrate 5 semiconductor package 10 core layer 11 upper metal layer 12 upper surface 13 lower metal layer 14 lower surface 15 upper solder resist layer 16 lower solder resist layer 20 support layer (core layer) 21 stress relief layer 22 conductive layer 23 Semiconductor wafer 24 Solder bump 31 Substrate 32 Blind hole 33 Conductive trace 34 Copper mesh layer 35 Wafer 36 Edge 40 Substrate 41 Core layer 41a First surface 41b First __ — surface

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Brief description of the drawing 42 First circuit layer 43 Second circuit layer 44 ~ 45 Insulating material layer 46 First conductive trace 46a Terminal 47 First — Conductive trace 47a Terminal 51 Chip 52 Welding wire 53 Encapsulant 54 Welding ball Π568 stone Xipin.ptd page] 6

Claims (1)

1237352 6. Scope of patent application 1. A substrate for preventing deformation, comprising: a core layer including a first surface and an opposite second surface; a first circuit layer formed on the first of the core layer On the surface; a second circuit layer formed on the second surface of the core layer; and an insulating material layer used to cover the surfaces and the circuit layers respectively; wherein, the The thickness of the first circuit layer and the second circuit layer are inversely proportional to the density of its circuit layout, and the thickness of the first circuit layer and the thickness of the second circuit layer form a proportional relationship. The second circuit layer generates shrinkage stresses that are in opposition to each other under temperature changes. 2. For the substrate according to item 1 of the patent application scope, wherein the core layer is made of one of epoxy resin, polyurethane resin, BT resin and FR4 resin. 3. For the substrate of the scope of application for item 1, wherein the first circuit layer and the second circuit layer are respectively formed with a first conductive trace and a second conductive trace. 4. The substrate of claim 3, wherein the first conductive trace and the second conductive trace are made of copper. 5. The substrate according to item 3 of the patent application, wherein the first conductive trace and the second conductive trace have a terminal exposed outside the insulating material layer. 17568¾ 夕 品 .ptd Page 17 1237352 6. Application for Patent Scope 6. For the substrate with the scope of patent application No. 5, in which the terminals of the first conductive trace and the second conductive trace are used for planting solder bumps. . 7. The substrate of claim 5 in which the terminals of the first conductive trace and the second conductive trace are used to implant solder balls. 8. For the substrate of the scope of the patent application No. 5, wherein the terminal of the first conductive trace is used for bonding wire, and the terminal of the second conductive trace is used for planting fresh balls. 9. The substrate according to item 1 of the scope of patent application, wherein the insulating material layer is a freshness preventive layer. 10. The substrate according to item 3 of the scope of patent application, wherein when the first conductive trace layout density is higher than the second conductive trace layout density, the thickness of the first circuit layer is thin. The thickness of the second circuit layer. 1 1. According to the substrate of claim 3 in the scope of patent application, when the first conductive trace layout density is lower than the second conductive trace layout density of the second circuit layer, the thickness of the first circuit layer is thick. The thickness of the second circuit layer. 1 2. The substrate according to item 10 or 11 of the scope of patent application, wherein the proportional relationship between the thickness of the first circuit layer and the thickness of the second circuit layer is based on the temperature of the first surface and the second surface. The deformations formed in the changing environment are fairly benchmark. 17568¾ Xipin.ptd Page 18