JP6621951B1 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6621951B1 JP6621951B1 JP2019022031A JP2019022031A JP6621951B1 JP 6621951 B1 JP6621951 B1 JP 6621951B1 JP 2019022031 A JP2019022031 A JP 2019022031A JP 2019022031 A JP2019022031 A JP 2019022031A JP 6621951 B1 JP6621951 B1 JP 6621951B1
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Engineering & Computer Science (AREA)
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- Computer Hardware Design (AREA)
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Details Of Aerials (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Aerials With Secondary Devices (AREA)
Abstract
Description
表面及び裏面に設けられた再配線層40を構成する金属材料が露出させる。これにより,基板10の両面に回路素子20が配置された集積度の高い半導体装置を得ることができる。
11…凹部 11a…底面
11b…側面 11c…段差部
12…貫通孔 13…バリ
14…穴部 15…貫通孔用凹部
20…回路素子 21…電極パッド
30…絶縁層 31…接着剤
32…感光性樹脂膜 40…再配線層
41…はんだボール 50…貫通ビア
60…導体材料 70…絶縁膜
71…開口部 100…半導体装置
210…上金型 211…突起部
212…注入口 220…下金型
221…窪み部 300…マスクシート
400…プレート部材 410…金属層
411…外枠部 412…凸部
413…囲繞領域 420…樹脂層
Claims (1)
- 熱硬化性樹脂を一又は複数の凹部を持つ形状に成型した後に熱硬化させて基板を形成する工程と,
前記基板の凹部内に回路素子を配置する工程と,
前記凹部の開口側において前記回路素子に再配線層を接続する工程とを含む
半導体装置の製造方法であって,
前記基板を形成する工程は,導電性の凸部を有するプレート部材の表面に熱硬化性樹脂を圧接させ,当該凸部の周囲を熱硬化性樹脂が取り囲んだ状態で熱硬化させ,当該プレート部材の凸部を除く部分を除去することで,当該凸部を当該熱硬化性樹脂からなる基板を厚み方向に貫通する貫通ビアとして機能させる
半導体装置の製造方法。
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Cited By (2)
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CN111640677A (zh) * | 2020-03-02 | 2020-09-08 | 浙江集迈科微电子有限公司 | 一种凹槽内芯片放置方法 |
CN113257786A (zh) * | 2021-06-17 | 2021-08-13 | 浙江集迈科微电子有限公司 | 用于射频传输的多层布线转接板及其制备方法 |
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FR3118293A1 (fr) | 2020-12-22 | 2022-06-24 | Commissariat à l'Energie Atomique et aux Energies Alternatives | Procédé de mise en courbure collective de composants microélectroniques comportant un report des composants microélectroniques alors assemblés à une poignée temporaire |
FR3118295B1 (fr) | 2020-12-22 | 2023-10-06 | Commissariat Energie Atomique | Procédé de mise en courbure collective de composants microélectroniques |
CN113078148B (zh) * | 2021-03-12 | 2024-03-26 | 上海易卜半导体有限公司 | 半导体封装结构、方法、器件和电子产品 |
CN113078149B (zh) * | 2021-03-12 | 2023-11-10 | 上海易卜半导体有限公司 | 半导体封装结构、方法、器件和电子产品 |
CN113097201B (zh) * | 2021-04-01 | 2023-10-27 | 上海易卜半导体有限公司 | 半导体封装结构、方法、器件和电子产品 |
CN115084046B (zh) * | 2022-07-20 | 2022-11-08 | 威海市泓淋电力技术股份有限公司 | 一种混合集成半导体封装及其制造方法 |
US20240113075A1 (en) * | 2022-09-29 | 2024-04-04 | Intel Corporation | Multichip ic devices with die embedded in glass substrate & a redistribution layer interconnect bridge |
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Publication number | Priority date | Publication date | Assignee | Title |
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CN111640677A (zh) * | 2020-03-02 | 2020-09-08 | 浙江集迈科微电子有限公司 | 一种凹槽内芯片放置方法 |
CN111640677B (zh) * | 2020-03-02 | 2022-04-26 | 浙江集迈科微电子有限公司 | 一种凹槽内芯片放置方法 |
CN113257786A (zh) * | 2021-06-17 | 2021-08-13 | 浙江集迈科微电子有限公司 | 用于射频传输的多层布线转接板及其制备方法 |
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KR20210110302A (ko) | 2021-09-07 |
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US20220102310A1 (en) | 2022-03-31 |
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JP2020109818A (ja) | 2020-07-16 |
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