JP5231382B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP5231382B2 JP5231382B2 JP2009269789A JP2009269789A JP5231382B2 JP 5231382 B2 JP5231382 B2 JP 5231382B2 JP 2009269789 A JP2009269789 A JP 2009269789A JP 2009269789 A JP2009269789 A JP 2009269789A JP 5231382 B2 JP5231382 B2 JP 5231382B2
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Description
図1は本発明の第1の実施形態に係る半導体装置の構成を断面図の形態で示したものである。また、図2はこの半導体装置におけるパッケージの部分を図1のA−A線に沿って平面的に見たときの概略構成を示している。
図3は本発明の第2の実施形態に係る半導体装置の構成を断面図の形態で示したものである。また、図4はこの半導体装置におけるパッケージの部分を図3のA−A線に沿って平面的に見たときの概略構成を示している。
20,20a…配線基板(パッケージ)、
22(a,b,c,d),23…配線層(導体部分)、
24,24a…ソルダレジスト層(最外層の絶縁層/ダム状部材)、
25…ソルダレジスト層(最外層の絶縁層/保護膜)、
28…はんだボール(外部接続端子)、
29…サーマルビア、
30…半導体素子(チップ)、
31…電極パッド(端子)、
32…ボンディングワイヤ(導体部分)、
33…チップ搭載用の接着剤(層)、
40…キャップ、
41…凹部、
42(42a)…側壁部(底面)、
43…段差状部分(樹脂溜め部分/凹部)、
45…キャップ搭載用の接着剤、
ANT…アンテナ、
CV…キャビティ、
P1,P2,P3…パッド(ボンディング用、層間接続用、外部接続用)、
WR…配線形成領域。
Claims (7)
- 基板と、
前記基板の第1面に形成されたキャビティと、
前記キャビティの周囲の前記基板の上に配置され、第1パッドを備えた高周波用の配線と、
前記キャビティの周囲の前記基板の上に配置され、第2パッドを備えた他の配線と、
前記基板の両面にそれぞれ形成され、前記第1面において、前記第1パッドを備えた高周波用の配線の全体を露出させると共に、前記第2パッドを露出させた状態で前記他の配線を被覆する保護絶縁層と
を備えた配線基板と、
前記配線基板のキャビティ内に搭載された半導体素子と、
前記配線基板の上に接着剤で接着され、前記半導体素子と前記高周波用の配線及び他の配線とを内部に収容する凹状のキャップと、
前記高周波用の配線及び他の配線が配置された領域と前記キャップの側壁部との間の領域に配置され、前記保護絶縁層の一部から形成されたダム状部材と、
前記キャップの側壁部の下面において内側部分が外側部分より下側になるように前記キャビティの側壁部の外側下部に形成された凹部と
を有することを特徴とする半導体装置。 - 前記高周波用の配線は、前記キャビティを挟んで対向する位置に配置されており、
前記半導体素子の電極パッドと前記高周波用の配線の第1パッドとを接続する第1ワイヤと、
前記半導体素子の電極パッドと前記他の配線の第2パッドとを接続する第2ワイヤとを有し、
前記第1ワイヤの長さは前記第2ワイヤの長さよりも短いことを特徴とする請求項1に記載の半導体装置。 - 前記ダム状部材の外側側面に前記キャップの対応する内側側面が接触するように押し当てられていることを特徴とする請求項1又は2に記載の半導体装置。
- 前記ダム状部材は、前記キャップの側壁部の内側周縁部の形状に従ってリング状に配設されていることを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置。
- 前記ダム状部材は、前記配線基板上の前記高周波用の配線の近傍にのみ部分的に配設されていることを特徴とする請求項1乃至3のいずれか一項に記載の半導体装置。
- 前記キャビティの直下の領域には、前記配線基板の厚みに方向に貫通するサーマルビアが形成されており、
前記サーマルビアは前記キャビティの底面に露出しており、接着剤層を介して前記半導体素子と熱的に結合していることを特徴とする請求項1乃至5のいずれか一項に記載の半導体装置。 - 前記保護絶縁層から露出する前記高周波用の配線が前記キャップで封止されていることを特徴とする請求項1乃至6のいずれか一項に記載の半導体装置。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009269789A JP5231382B2 (ja) | 2009-11-27 | 2009-11-27 | 半導体装置 |
US12/953,808 US8592959B2 (en) | 2009-11-27 | 2010-11-24 | Semiconductor device mounted on a wiring board having a cap |
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Application Number | Priority Date | Filing Date | Title |
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JP2009269789A JP5231382B2 (ja) | 2009-11-27 | 2009-11-27 | 半導体装置 |
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JP2011114192A JP2011114192A (ja) | 2011-06-09 |
JP2011114192A5 JP2011114192A5 (ja) | 2012-09-20 |
JP5231382B2 true JP5231382B2 (ja) | 2013-07-10 |
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Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011128140A (ja) * | 2009-11-19 | 2011-06-30 | Dainippon Printing Co Ltd | センサデバイス及びその製造方法 |
JP5827476B2 (ja) * | 2011-03-08 | 2015-12-02 | 株式会社東芝 | 半導体モジュール及びその製造方法 |
JP6003897B2 (ja) * | 2011-09-26 | 2016-10-05 | 日本電気株式会社 | 中空封止構造 |
KR20130041645A (ko) * | 2011-10-17 | 2013-04-25 | 삼성전기주식회사 | 인쇄회로기판 |
FR2995721B1 (fr) * | 2012-09-17 | 2014-11-21 | Commissariat Energie Atomique | Capot pour dispositif a rainure et a puce, dispositif equipe du capot, assemblage du dispositif avec un element filaire et procede de fabrication |
JP2014072346A (ja) * | 2012-09-28 | 2014-04-21 | Nec Corp | 中空封止構造及び中空封止構造の製造方法 |
JP6383147B2 (ja) * | 2013-12-10 | 2018-08-29 | 日本特殊陶業株式会社 | パッケージ |
JP6247106B2 (ja) * | 2014-02-03 | 2017-12-13 | 新光電気工業株式会社 | 半導体装置 |
US9693445B2 (en) * | 2015-01-30 | 2017-06-27 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Printed circuit board with thermal via |
US10916520B2 (en) | 2015-06-10 | 2021-02-09 | Mitsubishi Electric Corporation | Semiconductor device, and method of manufacturing the same |
JP2017038019A (ja) * | 2015-08-13 | 2017-02-16 | 富士電機株式会社 | 半導体装置 |
JP6342591B2 (ja) * | 2015-11-25 | 2018-06-13 | 京セラ株式会社 | 電子部品収納用パッケージ、電子装置および電子モジュール |
US10676344B2 (en) * | 2015-11-30 | 2020-06-09 | W. L. Gore & Associates, Inc. | Protective environmental barrier for a die |
US9870967B2 (en) * | 2016-03-10 | 2018-01-16 | Analog Devices, Inc. | Plurality of seals for integrated device package |
US9887143B2 (en) * | 2016-03-25 | 2018-02-06 | Infineon Technologies Americas Corp. | Surface mount device package having improved reliability |
US10177064B2 (en) * | 2016-08-26 | 2019-01-08 | Qorvo Us, Inc. | Air cavity package |
US10269669B2 (en) * | 2016-12-14 | 2019-04-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor package and method of forming the same |
US10629545B2 (en) * | 2017-03-09 | 2020-04-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device |
FR3069406A1 (fr) * | 2017-07-18 | 2019-01-25 | Stmicroelectronics (Grenoble 2) Sas | Boitier electronique et procede de fabrication |
WO2019093269A1 (ja) * | 2017-11-09 | 2019-05-16 | Ngkエレクトロデバイス株式会社 | 蓋体および電子装置 |
JP6929210B2 (ja) * | 2017-12-11 | 2021-09-01 | 株式会社ブリヂストン | タイヤ |
US10867955B2 (en) * | 2018-09-27 | 2020-12-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure having adhesive layer surrounded dam structure |
CN111193492B (zh) * | 2018-11-14 | 2023-08-15 | 天津大学 | 封装结构、半导体器件、电子设备 |
CN113692644A (zh) * | 2019-04-22 | 2021-11-23 | 京瓷株式会社 | 电子部件收纳用封装件、电子装置以及电子模块 |
US20200411407A1 (en) * | 2019-06-26 | 2020-12-31 | Intel Corporation | Integrated circuit packages with solder thermal interface material |
KR102430750B1 (ko) * | 2019-08-22 | 2022-08-08 | 스템코 주식회사 | 회로 기판 및 그 제조 방법 |
CN115312549A (zh) * | 2021-05-05 | 2022-11-08 | 胜丽国际股份有限公司 | 传感器封装结构 |
US11948893B2 (en) * | 2021-12-21 | 2024-04-02 | Qorvo Us, Inc. | Electronic component with lid to manage radiation feedback |
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JPS58106947A (ja) | 1981-12-21 | 1983-06-25 | Fujitsu Ltd | 光センサ |
JPS58177946A (ja) | 1982-04-13 | 1983-10-18 | Mitsui Toatsu Chem Inc | 3,3′−ジアミノベンゾフエノンの製造方法 |
JPS58106947U (ja) * | 1982-01-14 | 1983-07-21 | 株式会社日立製作所 | 半導体の実装構造 |
JPS58177946U (ja) * | 1982-05-21 | 1983-11-28 | 富士通株式会社 | Ic収容「きよう」体 |
JPH0216758A (ja) * | 1988-07-05 | 1990-01-19 | Nec Corp | 半導体装置用キャップ |
JPH03114247A (ja) * | 1989-09-28 | 1991-05-15 | Nec Yamagata Ltd | パッケージ型半導体装置 |
JP2906756B2 (ja) * | 1991-08-06 | 1999-06-21 | イビデン株式会社 | 電子部品搭載用基板 |
US5311402A (en) * | 1992-02-14 | 1994-05-10 | Nec Corporation | Semiconductor device package having locating mechanism for properly positioning semiconductor device within package |
JPH0746709A (ja) | 1993-08-04 | 1995-02-14 | Fuji Heavy Ind Ltd | パラレルハイブリッド車のバッテリ充放電制御装置 |
JPH09232551A (ja) * | 1996-02-26 | 1997-09-05 | Toshiba Corp | 光電変換装置 |
JP3859340B2 (ja) * | 1998-01-06 | 2006-12-20 | 三菱電機株式会社 | 半導体装置 |
US6983537B2 (en) * | 2000-07-25 | 2006-01-10 | Mediana Electronic Co., Ltd. | Method of making a plastic package with an air cavity |
JP3533159B2 (ja) * | 2000-08-31 | 2004-05-31 | Nec化合物デバイス株式会社 | 半導体装置及びその製造方法 |
US7064048B2 (en) * | 2003-10-17 | 2006-06-20 | United Microelectronics Corp. | Method of forming a semi-insulating region |
DE102004021365A1 (de) * | 2004-03-16 | 2005-10-06 | Robert Bosch Gmbh | Gehäuse für eine elektronische Schaltung und Verfahren zum Abdichten des Gehäuses |
JP4511278B2 (ja) * | 2004-08-11 | 2010-07-28 | 三洋電機株式会社 | セラミックパッケージ |
TWI299552B (en) * | 2006-03-24 | 2008-08-01 | Advanced Semiconductor Eng | Package structure |
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