TWI785515B - 半導體封裝體及包含半導體封裝體之裝置 - Google Patents

半導體封裝體及包含半導體封裝體之裝置 Download PDF

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TWI785515B
TWI785515B TW110107268A TW110107268A TWI785515B TW I785515 B TWI785515 B TW I785515B TW 110107268 A TW110107268 A TW 110107268A TW 110107268 A TW110107268 A TW 110107268A TW I785515 B TWI785515 B TW I785515B
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Taiwan
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conductive layer
carrier
semiconductor
die
semiconductor die
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TW110107268A
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TW202131479A (zh
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比爾吉 貝瑞西
阿布杜拉 賽立克
溫斯樂 朗德
聖托西 安尼爾 克德塔克
悠瑟福 阿特賽爾
圖路森 闊庫歐古
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愛爾蘭商亞德諾半導體國際無限公司
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Abstract

一種封裝體，包括一載體，載體包含位於第一側上之一第一導電層及位於相對於第一側之第二側上之一第二導電層。第一導電層包含銲線接合墊。此封裝體亦包括一半導體晶粒，其為安裝於載體第一側上之倒裝晶片。

Description

半導體封裝體及包含半導體封裝體之裝置
本發明所揭露內容係涉及半導體封裝體之領域。
透過倒裝晶片接合法將半導體晶粒附接至一板上需要昂貴之對準與機器人設備，此可能對於終端使用者較為不便。另一方面，銲線接合技術可能無法提供足夠之性能，特別是對於半導體晶粒處理高頻訊號之射頻（RF）應用。因此，仍有持續改進半導體封裝體之需求。
於一方面，係揭露一封裝體。此封裝體包括一載體，其包含位於第一側上之一第一導電層以及位於相對於第一側之第二側上之一第二導電層。第一導電層具有銲線接合墊。此封裝體亦包括一半導體晶粒，其為安裝於載體之第一側上之倒裝晶片。
於一實施例，載體包含從第一側至第二側之通孔。通孔可接收來自第二導電層之電性接地。
於一實施例，第一導電層包含線路，其電性連接半導體晶粒與銲線接合墊。
於一實施例，半導體晶粒為高頻率射頻（RF）晶粒，且第一導電層攜帶射頻訊號。
於一實施例，半導體晶粒為一絕緣層上覆矽（SOI）晶粒。
於一實施例，封裝體進一步包括銅柱，其係位於半導體晶粒與載體之間。
於一實施例，封裝體進一步包括造模材料，其係設置於半導體晶粒周圍。
於一實施例，載體包含一層壓基板、一陶瓷基板或一半導體基板。
於一方面，係揭露一裝置。此裝置包括一印刷電路板（PCB），其包含由介電質所隔開之第一導電層與第二導電層。第一導電層位於印刷電路板之第一側上。印刷電路板包括一凹槽，其位於第一側上，並且穿過第一導電層與介電質延伸至第二導電層。此裝置亦包括一載體，其具有位於第一側上之第一導電層以及位於第二側上之第二導電層。載體位於印刷電路板之凹槽中。載體之第二導電層係電性連接至凹槽中的印刷電路板之第二導電層。此裝置進一步包括一半導體晶粒，半導體晶粒係以倒裝晶片方式附接至載體之第一側，並且經配置以透過載體接受來自印刷電路板之第二導電層之電性接地。
於一實施例，此裝置進一步包含銲線，其連接印刷電路板之第一導電層上之銲墊與載體之第一導電層上之對應銲墊之間。半導體晶粒可為高頻率射頻（RF）晶粒，並且銲線可攜帶射頻訊號。
於一實施例，半導體晶粒為一絕緣層上覆矽（SOI）晶粒，並且載體透過導熱及導電之環氧樹脂附接至印刷電路板。
於一實施例，印刷電路板之第二導電層包含一接地平面。
於一實施例，載體包含一層壓基板、一陶瓷基板或一半導體基板。半導體基板可能不包括經製造於其上之任何電子元件或半導體裝置。半導體基板可能包含電子元件與半導體裝置元件。
於一實施例，第一導電層包含線路與銲線接合墊。
於一方面，係揭露一封裝體。此封裝體包括透過倒裝晶片安裝以承載一半導體晶粒之裝置。承載裝置包含位於一第一側上之第一導電層以及位於相對於第一側之第二側上之一第二導電層。第一導電層包含銲線接合墊。
於一實施例，此承載裝置包含由第一側至第二側之通孔，通孔接收來自第二導電層之電性接地，以及第一導電層包含線路，其電性連接半導體晶粒與銲線接合墊。
於此揭露與半導體封裝體相關之各種實施例。例如，於此揭露之實施例對於封裝射頻（RF）晶粒或晶片特別有益。然而，應理解的是，於此揭露之實施例對任何其他類型之半導體晶粒亦為有益。
一半導體晶粒或晶片包括一主動側，主動側可具有主動半導體元件，例如電晶體，製造於其中。主動側亦可包括接合墊，其可作為半導體晶粒及外部電路與元件之間之介面。例如，接合墊可包括用於發送與/或接收訊號之輸入與/或輸出銲墊，用於接收電源電壓之電源銲墊，與/或用於連接至接地面之接地銲墊。雖然已描述接合墊之各種示例，但半導體晶粒可包括用於提供各式功能之接合墊。於製造之後，可封裝半導體晶粒以助於將晶粒連接至更大之電子系統，例如印刷電路板（PCB）。
圖1為一封裝之倒裝晶片元件20之側面剖視示意圖，其包括一半導體晶粒21、一封裝載體22（例如，層壓板）、導電柱（例如，銅柱）24a-24c、銲點凸塊25a-25c以及一造模材料（例如，封膠27與底部填膠28）。封裝載體22包括第一導電層31、第二導電層32與介電質33。此外，佈線圖案與銲墊26a-26c可由第一導電層31形成。如圖1所示，層壓板通孔34將第一導電層31之部分連接至第二導電層32之部分。於所描繪實施例中，層壓板通孔34包含穿透載體通孔。於其他實施例中，載體可包括多個中間銲線層。半導體晶粒21包括一主動側37a與一背側37b，其主動側37a包括裝置（例如，電晶體）與金屬化。
封裝之倒裝晶片元件20可附接至一板，例如一印刷電路板（PCB）（圖1中未繪示），其藉由第二導電層32上之銲墊而連接至印刷電路板上之對應銲墊。
圖2為一封裝裝置80之示意圖，其包括一半導體封裝體23與一系統板（例如，印刷電路板（PCB）62）。 封裝體23包含一倒裝晶片晶粒21，其係附接至一載體42。於使用中，例如，封裝體23可設置於印刷電路板62之凹槽65中，使載體42之上表面與印刷電路板 62之上表面大致齊平，如圖所示。於其他實施例中，載體42之上表面可相對於印刷電路板62之上表面凹陷，或者可突出於印刷電路板 62之上表面上方。圖2中所繪示之封裝體23亦包括圍繞倒裝晶片晶粒21之一造模材料（例如，封膠27與底部填膠28）。於某些實施例中，例如，封膠27與底部填膠28可以多步驟製程提供。首先，具有柱體24與銲點凸塊25之半導體晶粒21可經迴焊至載體42上。底部填膠28可設置於晶粒21下方與/或周圍。然後，封膠27可設置於晶粒21與底部填膠28上方與/或周圍。
印刷電路板62包括第一導電層71、第二導電層72、介電層73、74及通孔（圖2未顯示）。所描繪實施例之印刷電路板62進一步包括凹槽65，其中載體42已利用導熱與/或導電性之一環氧樹脂63進行附接。於某些實施例中，載體42可部分地或完全地設置於凹槽65中。
載體42包括第一導電層51、第二導電層52、介電質53及用於連接導電層51、52部分之間之通孔54。第一導電層51可包含銲墊55。銲墊55可經配置以接收用於銲線接合之銲線，例如，用於銲線接合至印刷電路板 62之對應銲墊。於某些實施例中，第一導電層51亦可包含經配置以與載體42內之金屬層互連之線路（未繪示）。柱體24與線路可於銲墊55與晶粒21之間形成電連接。載體42藉由環氧樹脂63電連接與/或熱連接至印刷電路板62之第二導電層72（接地平面）。通孔54可有益於在晶粒21之接地銲墊與印刷電路板 62之第二導電層72（接地平面）之間提供一相對較低之電阻/低電感連接。
印刷電路板 62之第一導電層71與載體42之銲墊55可用以攜帶射頻訊號，例如頻率為介於10GHz至20GHz範圍內之電磁輻射。如圖2所示，印刷電路板62之第一導電層71包括線路與銲墊，用於將銲線（例如，銲線接合67與/或銲線帶68）連接至載體42之對應線路與銲墊55。於某些實施例中，具有較短之連接銲線可能較為有益，因較長之銲線可能導致更多雜訊。凹槽65可允許銲墊55更接近第一導電層71，其可使連接銲線比不具凹槽時更短。第二導電層72可接地並且不需包括任何訊號線路。因此，於某些實施例中，第二導電層72亦可稱為一接地平面。
於某些實施例中，載體42可包含用於承載半導體晶粒21之一承載裝置。於某些實施例中，載體42可包含一層壓基板。於某些實施例中，載體42可包括一陶瓷基板。於某些實施例中，載體42可包含一半導體基板，例如一砷化鎵（GaAs）基板，其不包括任何主動元件。於某些實施例中，載體42可包含一半導體基板，例如一砷化鎵基板，其包括形成於載體42同一側且作為第一導電層51之主動元件（例如，電晶體）。於該些實施例中，可提供一堆疊之晶粒組件。於某些實施例中，砷化鎵係為有益，因發現其於溫度發生變化時對柱體24產生相對較低之機械應力。
可以各種製程製造晶粒21。於某些實施例中，晶粒21包括絕緣層上覆矽（SOI）晶粒。圖2實施例之優點在於其允許絕緣層上覆矽晶粒可用於高性能射頻應用（例如，高射頻功率與/或高頻）。高頻之範圍可為例如介於10GHz至20GHz。例如，因典型之絕緣層上覆矽製程缺少穿過基板之通孔（TSVs），因此難以於某些高性能射頻應用中利用絕緣層上覆矽晶粒，因此不易獲得穩固之接地連接。相反地，砷化鎵晶粒可比絕緣層上覆矽晶粒更容易整合至射頻應用中，因為可透過砷化鎵製程中可用之TSVs提供穩固接地。因此，砷化鎵與/或任何其他類似之製程係傳統上用於高性能射頻應用。雖然絕緣層上覆矽晶粒可利用常規配置以使晶片倒裝附接，但其仍無法提供足夠之接地。然而，圖2實施例可適用於提供一穩固接地連接至一絕緣層上覆矽晶粒，因此允許絕緣層上覆矽晶粒用於高性能射頻應用。
圖3A顯示圖2半導體封裝體23具有造模材料（例如，封膠27與底部填膠28）設置於晶粒21周圍之側橫截面示意圖。圖3B顯示不具圖2與圖3A中所示造模材料27、28之半導體封裝體23之側橫截面示意圖。於某些實施例中，介電質53可包含如圖3A所示之一層壓基板與/或如圖3B所示之一陶瓷基板。可提供造模材料27、28以匹配晶粒21與介電質53之熱常數。使介電質53之材料具有與晶粒21類似之熱膨脹係數（CTE）是有益的，藉此可使造模材料減至最少或將其省略。此可能係為有益，因為相較於有造模材料例如封膠27之實施例，無造模材料之實施例允許晶粒21之背側37b（例如，主動側）暴露於空氣，由於較低的介電損耗此可提供相對較高之射頻性能。此外，無造模材料之實施例是有益的，因封裝體23之整體尺寸可小於包括造模材料例如封膠27之實施例。舉例而言，於某些實施例中，圖3B實施例之橫向尺寸可比具有造模材料之圖3A實施例小0.5mm（例如，0.4mm至0.6mm）。於某些實施例中，圖3B實施例可包括圖3A中所示至少一部分底部填膠28，但可省略封膠27。於某些其他實施例中，半導體封裝體23可包括至少一部分底部填膠28與/或至少一部分封膠27。
圖4為圖3B之封裝體23之俯視圖，其中晶粒21經隱藏以顯示出位於晶粒21下方之元件。介電質53上之第一導電層51可包含銲墊55。銲墊55可經配置以與銲線（例如，接合銲線，帶狀銲線等）電連接，以提供與晶粒21之主動元件之電性連接。第一導電層51亦可包含線路56，線路56可包含電性連接晶粒21之各種主動元件之互連。柱體24與線路56可於銲墊55與晶粒21之間形成電性連接。於某些實施例中，銲墊55可用以攜帶射頻訊號。於某些實施例中，第一導電層51之部分57可將來自晶粒21之接地連接分配至介電質53上之較寬區域。
圖5為根據各種實施例之封裝裝置80之一部分的俯視圖。圖5中封裝裝置80之部分顯示出銲墊55與印刷電路板 62之第一導電層71之部分71a之間以一銲線帶68進行之電連接。然而，於某些實施例中，銲墊55與印刷電路板 62之第一導電層71之部分71a可透過任何合適的接合方法（例如，透過較薄接合銲線，例如，金接合銲線）進行接合。
封裝裝置80可於半導體封裝體23與印刷電路板 62之第一介電層73之間具有一橫向間隙a。 於某些實施例中，橫向間隙a可例如在2mm至3mm之範圍內。橫向間隙a有助於將半導體封裝體23設置在形成於印刷電路板 62中之凹槽中。於某些實施例中，橫向間隙a可接收連接半導體封裝體23與第二導電層72之過量環氧樹脂63（參見例如圖2），其可例如防止環氧樹脂63觸及載體42之上表面與/或印刷電路板 62之上表面。
於某些實施例中，銲墊55可包括矩形形狀，如圖5所示。然而，應該理解可改變銲墊55之形狀。圖5之銲墊55可具有代表銲墊55的兩側之尺寸b與c。於某些實施例中，尺寸b可例如約155μm（例如，145μm至165μm），並且尺寸c可例如約175μm（例如，165μm至185μm）。
線路56可包含由晶粒21之邊緣至銲墊55之尺寸d。於某些實施例中，尺寸d可例如約250μm（例如，240μm至260μm）。應當理解，尺寸d可至少部分根據例如相對載體42的尺寸（參見例如圖2）與/或銲墊55之尺寸b與c之晶粒21尺寸進行變化。
於某些實施例中，載體42之第一導電層51於橫向尺寸上可小於載體42，藉以於載體42之邊緣周圍留下介電質53之未覆蓋部分。介電質53之未覆蓋部分可具有由載體42邊緣至第一導電層51邊緣之尺寸e。尺寸e可例如約50μm（例如，45μm至55μm）。當單片化（例如，切割）半導體封裝體23時，該未覆蓋部分可能係為有益。於某些實施例中，切割第一導電層51可能導致例如金屬殘餘物之產生，其可能導致短路。因此，未覆蓋部分可提供用於分割半導體封裝體23時之一切單通道。
銲線帶68可具有長度f與寬度g。銲線帶68之長度f可例如在10mm至12mm之範圍內。應當理解，銲線帶68之長度f可至少部分根據例如橫向間隙a與尺寸e、載體42之厚度、與/或凹槽65之厚度而變化。銲線帶68之寬度g可例如在2mm至3mm之範圍內。
圖6為半導體封裝體23之側剖面圖，其中銲線帶68係附接至載體42。銲線帶68具有第一與第二端75、77。圖6所描繪之實施例假設銲線帶68之第二端77係連接至印刷電路板上之一對應銲墊，此對應銲墊與接收銲線帶68之第一端75之銲墊55處於相同之相對高度（參見例如圖2）。銲線帶68可包括一帶厚度h。帶厚度h可落於例如0.012mm至0.051mm之範圍內。此銲線帶68具有由載體42之上表面至帶狀拱型最高點測量之一高度j。高度j可落於例如3mm至5mm之範圍內。
載體42可具有一載體厚度k ，其係由載體42之下表面垂直測量至載體42之上表面。厚度k 可落於例如4mm至5mm之範圍內。
柱體24可具有一高度l，其係由載體42之上表面測量至晶粒21之主動側37a。晶粒可具有厚度m，其係由晶粒之主動側37a垂直測量至背側37b。高度l與厚度m之總和可落於例如12mm至13mm之範圍內。
圖7為圖2封裝裝置80之頂部透視圖，其中晶粒21係以虛線表示以更佳描繪出柱體24。圖8為封裝裝置80之頂部透視圖，其不包括圖7中所示之凹槽65。封裝裝置80包括設置於圖7中印刷電路板 62之凹槽65中之半導體封裝體23。於圖8中所示實施例所使用之銲線帶68比圖7中所示實施例所使用之銲線帶68更長，以補償因缺少凹槽65所產生之高度差。封裝體23之銲墊55及印刷電路板 62之第一導電層71部分係透過銲線帶68電連接。應該理解的是，連接亦可以透過銲線接合或任何其他合適手段提供。
雖然已於某些實施例與範例之上下文中揭露本發明，但本領域技術人員將理解，本發明係超出具體揭露之實施例，並延伸至本發明之其他替代實施例與/或用途以及明顯之修改與其均等物。此外，雖然已詳細顯示與描述本發明之若干變化，但根據本發明之內容，本領域技術人員將易於理解於本發明範疇內之其他修改。可預期該些實施例可以各種組合方式或排列方式彼此相組合使用，並且仍落入本發明之範疇內。應該理解的是，所揭露之實施例之各種特徵、方面可彼此組合或替代，以形成本發明之變化模式。因此，於此所揭露本發明之範疇不應受上述特定揭露實施例所限制，而應僅以透過合理閱讀所附申請專利範圍所確定。
20:倒裝晶片元件 21:晶粒 22:載體 23:封裝體 24a:柱體 24b:柱體 24c:柱體 25a:銲點凸塊 25b:銲點凸塊 25c:銲點凸塊 26a:銲墊 26b:銲墊 26c:銲墊 27:封膠（造模材料） 28:底部填膠（造模材料） 31:第一導電層 32:第一導電層 33:介電質 34:通孔 37a:主動側 37b:背側 42:載體 51:第一導電層 52:第二導電層 53:介電質 54:通孔 55:銲墊 56:線路 57:部分 62:印刷電路板 63:環氧樹脂 65:凹槽 67:銲線接合 68:銲線帶 71:第一導電層 71a:部分 72:第二導電層/接地平面 73:介電層 74:介電層 75:第一端 77:第二端 80:封裝裝置 a:橫向間隙 b,c,d,e:尺寸 f:長度 g:寬度 h,k,m:厚度 j,l:高度
現在將參考以下附圖描述本發明之具體實施方式，該等附圖係作為例示而非作為限制。 圖1為根據一實施例之一封裝之倒裝晶片元件之側面剖視示意圖。 圖2為根據一實施例一封裝體裝置之側面剖視示意圖。 圖3A顯示具有造模材料之圖2半導體封裝體之側橫截面示意圖。 圖3B表示無圖2及圖3A中造模材料之半導體封裝體之側橫截面示意圖。 圖4為圖3B半導體封裝體之俯視圖，其中將晶粒隱藏以顯露柱體。 圖5為根據各種實施例封裝體裝置一部分之俯視圖，其顯示出一印刷電路板與半導體封裝體之間之一連結。 圖6為根據各種實施例之半導體封裝體具有帶狀物附接至一載體之側剖面示意圖。 圖7為圖2之封裝體裝置之頂部透視圖，其中以虛線表示晶粒以描繪柱體。 圖8為封裝體裝置之頂部透視圖，其不包括圖7中所示之凹槽。
20:倒裝晶片元件
21:晶粒
22:載體
24a:柱體
24b:柱體
24c:柱體
25a:銲點凸塊
25b:銲點凸塊
25c:銲點凸塊
26a:銲墊
26b:銲墊
26c:銲墊
27:封膠
28:底部填膠
31:第一導電層
32:第二導電層
33:介電質
34:通孔
37a:主動側
37b:背側

Claims (20)

  1. 一種半導體封裝體，包含：一載體，包含位於一第一側上之一第一導電層，以及位於相對於該第一側之一第二側上之一第二導電層，其中該載體包含一陶瓷基板或一半導體基板，且該第一導電層包含一第一部分，具有複數銲線接合墊，並經設置以電性連接該半導體封裝體和一外部基板或元件；以及一半導體晶粒，以倒裝晶片方式安裝於該載體之該第一側上，其中該載體包含一電性接地通孔，電性連接該半導體晶粒和該第二導電層，該第一導電層包含一第二部分，被配置從該半導體晶粒分配接地連接至該第二部分的一面積，該面積大於該半導體晶粒的面積，且該半導體晶粒部分地置於該第一導電層的該第二部分上。
  2. 如請求項1之半導體封裝體，其中該載體包含一單層基板，且該電性接地通孔由該第一側延伸至該第二側，並由該第二導電層接受電性接地。
  3. 如請求項1之半導體封裝體，其中該第一導電層包含複數線路，電性連接該半導體晶粒和該些銲線接合墊。
  4. 如請求項1之半導體封裝體，其中該半導體晶粒為一高頻率射頻(RF)晶粒，且該第一導電層攜帶射頻訊號。
  5. 如請求項1之半導體封裝體，其中該半導體晶粒為一絕緣層上覆矽(SOI)晶粒。
  6. 如請求項1之半導體封裝體，進一步包含複數銅柱，位於該半導體晶粒與該載體之間。
  7. 如請求項1之半導體封裝體，進一步包含造模材料，設置圍繞該半導體晶粒。
  8. 如請求項1之半導體封裝體，其中該載體包含一砷化鎵(GaAs)基板。
  9. 一種包含半導體封裝體之裝置，包含：一印刷電路板(PCB)，包含藉由一介電質隔開之一第一導電層與一第二導電層，其中該第一導電層位於該印刷電路板之一第一側上，且其中該印刷電路板包含一凹槽位於該第一側上，並且該凹槽延伸穿過該第一導電層與該介電質至該第二導電層；一載體，包含一陶瓷基板或一半導體基板，該載體包含位於一第一側上之一第一導電層，以及位於相對於該第一側之一第二側上之一第二導電層，其中該第一導電層包含一第一部分，具有複數銲線接合墊，該載體係位於該印刷電路板之該凹槽中，且該載體之該第二導電層係電性連接至該凹槽中之該印刷電路板之該第二導電層；以及一半導體晶粒，以倒裝晶片方式附接至該載體之該第一側，並經設置以透過該載體接收來自該印刷電路板之該第二導電層之電性接地，其中該載體包含一電性接地通孔，電性連接該半導體晶粒與該第二導電層，該第一導電層包含一第二部分，被配置從該半導體晶粒分配接地連接至該第二部分的一面積，該面積大於該半導體晶粒的面積，且該半導體晶粒部分地置於該第一導電層的該第二部分上。
  10. 如請求項9之包含半導體封裝體之裝置，進一步包含複數銲線，連接於該印刷電路板之該第一導電層上之複數銲墊至該載體之該第一導電層上之該些銲線接合墊之對應複數銲墊。
  11. 如請求項10之包含半導體封裝體之裝置，其中該半導體晶粒為一高頻率射頻(RF)晶粒，並且該些銲線攜帶射頻訊號。
  12. 如請求項9之包含半導體封裝體之裝置，其中該半導體晶粒為一絕緣層上覆矽(SOI)晶粒，並且該載體藉由具導熱及導電性之一環氧樹脂附接至該印刷電路板。
  13. 如請求項9之包含半導體封裝體之裝置，其中該印刷電路板之該第二導電層包含一接地平面。
  14. 如請求項9之包含半導體封裝體之裝置，其中該載體包含一砷化鎵(GaAs)基板。
  15. 如請求項9之包含半導體封裝體之裝置，其中該第一導電層包含線路，電性連接該半導體晶粒與該些銲線接合墊。
  16. 一種半導體封裝體，包含：一載體，具有一外部頂側，以及相對於該外部頂側的一外部底側，該載體包含位於該外部頂側的一第一導電層，以及位於相對於該外部頂側的該外部底側的一第二導電層，其中該第一導電層包含一第一部分，具有複數銲線接合墊，且該第二導電層包含一接地平面，具有一表面，經設置以透過一黏著劑連接至一系統板；一半導體晶粒倒裝晶片，安裝於該載體之該外部頂側上；以及 一電性接地通孔，延伸穿過該載體由該外部頂側至該外部底側，該電性接地通孔電性連接該半導體晶粒與該接地平面，該第一導電層包含一第二部分，被配置從該半導體晶粒分配接地連接至該第二部分的一面積，該面積大於該半導體晶粒的面積，且該半導體晶粒部分地置於該第一導電層的該第二部分上。
  17. 如請求項16之半導體封裝體，其中該載體包含一陶瓷基板或一半導體基板。
  18. 如請求項16之半導體封裝體，其中該載體包含該半導體基板，且該半導體基板不包含一電性組件或在該電性組件上製造的複數半導體元件部件。
  19. 如請求項16之半導體封裝體，其中該載體包含該半導體基板，且該半導體基板包含複數電性組件和半導體元件部件。
  20. 如請求項16之半導體封裝體，其中該黏著劑包含一導電環氧樹脂。
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