TWI514542B - 具有圍繞矽穿封裝孔（ＴＰＶ）的末端部分之開口的晶粒封裝及使用該晶粒封裝之層疊封裝（ＰｏＰ） - Google Patents

具有圍繞矽穿封裝孔（ＴＰＶ）的末端部分之開口的晶粒封裝及使用該晶粒封裝之層疊封裝（ＰｏＰ） Download PDF

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TWI514542B
TWI514542B TW102130057A TW102130057A TWI514542B TW I514542 B TWI514542 B TW I514542B TW 102130057 A TW102130057 A TW 102130057A TW 102130057 A TW102130057 A TW 102130057A TW I514542 B TWI514542 B TW I514542B
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package
layer
die
tpv
semiconductor
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TW102130057A
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TW201431039A (zh
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Jingcheng Lin
Juipin Hung
Lihui Cheng
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Taiwan Semiconductor Mfg Co Ltd
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Description

具有圍繞矽穿封裝孔(TPV)的末端部分之開口的晶粒封裝及使用該晶粒封裝之層疊封裝(PoP)
本發明係有關於一種半導體裝置，特別是有關於一種晶粒封裝及使用該晶粒封裝之層疊封裝。
半導體裝置用於多種電子應用中，諸如個人電腦、蜂巢式電話、數位相機及其他電子設備(作為實例)。半導體裝置通常藉由以下操作製造：在半導體基板上依序沉積材料的絕緣或介電層、導體層及半導體層，及使用微影術來圖案化各個材料層以在各個材料層上形成電路組件及元件。
半導體工業藉由不斷地減小最小特徵大小(此舉允許將更多組件整合於給定面積中)來持續改良各種電子組件(例如，電晶體、二極體、電阻器、電容器，等)之整合密度。在一些應用中，此等較小的電子組件亦需要較小封裝，該等較小封裝比過去的封裝利用較小的面積及/或較低的高度。
因此，已開始開發諸如層疊封裝(PoP)之新封裝技 術，層疊封裝中具有裝置晶粒的頂部封裝結合至具有另一裝置晶粒的底部封裝。藉由採用新封裝技術，可增加封裝之整合程度。用於半導體的此等相對較新類型的封裝技術面臨著製造挑戰。
本發明的一個態樣係關於一種半導體裝置，包 含：一半導體晶粒；一介電材料，鄰接該半導體晶粒；及一矽穿封裝孔(TPV)，安置於該介電材料中，其中該介電材料中之一開口圍繞該TPV之一末端部分以暴露該末端部分，且其中該開口之至少一部分介於該TPV之該末端部分與模製化合物之間。
本發明的另一態樣係關於一種半導體裝置，包 含：一半導體晶粒；鄰近於該半導體晶粒之一或多個介電層；安置於該一或多個介電層中之一或多個矽穿封裝孔，該一或多個TPV自該一或多個介電層之第一側延伸至該一或多個介電層之一第二側；以及在圍繞該一或多個TPV之相應末端的該一或多個介電層中之複數個凹部，該等凹部暴露該一或多個TPV之相應末端的側壁之至少一部分。
本發明的又一態樣係關於一種半導體裝置，包 含：一第一晶粒封裝及一第二晶粒封裝。該第一晶粒封裝包含：一第一半導體晶粒；在該第一半導體晶粒之相對側上的介電材料；以及在該介電材料中之一貫穿孔(TV)，其中在該介電材料中之一開口圍繞該TV之一末端部分以暴露該末端部分。該第二晶粒封裝包含：一第二半導體晶粒；及一外部連接器。其中，該第二晶粒封裝之該外部連接器使用焊料結 合至該第一晶粒封裝之該TV之該末端部分以形成一結合結構，其中該焊料至少部分在該開口內。
100‧‧‧封裝結構
110‧‧‧晶粒封裝
112‧‧‧半導體晶粒
113‧‧‧半導體晶粒
114‧‧‧結合線
115‧‧‧連接器/基板
116‧‧‧結合線
117‧‧‧連接器
118‧‧‧金屬墊
204‧‧‧塗鍍種子層
204F‧‧‧塗鍍種子層
204G‧‧‧塗鍍種子層
205‧‧‧光阻層
206‧‧‧開口
207‧‧‧導電層
208‧‧‧鈍化層
209‧‧‧表面
210‧‧‧膠接層
120‧‧‧晶粒封裝
120’‧‧‧經封裝晶粒
121‧‧‧半導體晶粒
122‧‧‧TPV
122’‧‧‧柱體
122”‧‧‧TPV
122A‧‧‧TPV
122B‧‧‧TPV
122C‧‧‧TPV
122D‧‧‧TPV
123‧‧‧重分配層/模製化合物
125‧‧‧重分配結構
126‧‧‧外部連接器
127‧‧‧連接器
130‧‧‧基板
141‧‧‧氧化銅層
142‧‧‧IMC層
142’‧‧‧IMC層
143‧‧‧IMC層
145‧‧‧外部連接器
201‧‧‧載體
202‧‧‧黏著層
203‧‧‧表面
212‧‧‧鈍化層
213‧‧‧RDL
214‧‧‧鈍化層
219‧‧‧帶
260‧‧‧結合結構
260’‧‧‧結合結構
260”‧‧‧結合結構
300A‧‧‧開口
300B‧‧‧開口
300C‧‧‧開口
300D‧‧‧開口
300E‧‧‧開口
300F‧‧‧開口
300G‧‧‧開口
300H‧‧‧開口
301‧‧‧表面
302‧‧‧表面
302A‧‧‧連接
302C‧‧‧連接
302E‧‧‧連接
303‧‧‧表面/側壁
304‧‧‧表面
為更完整地理解實施例及實施例的優勢，現參考結合附圖進行的以下描述，其中：第1A圖為根據一些實施例之封裝結構的透視圖；第1B圖圖示根據一些實施例之結合至另一晶粒封裝的晶粒封裝之橫截面圖；第2A圖至第2O圖圖示根據一些實施例的製備層疊封裝(PoP)裝置之依序製程流的橫截面圖；第3A圖至第3H圖圖示根據一些實施例的圍繞矽穿封裝孔(TPV)的暴露的頂部部分之各種結構的橫截面圖；及第4A圖至第4C圖圖示根據一些實施例的各種結合結構的橫截面圖。
下文詳細論述本發明之實施例的製作及使用。然而，應瞭解，諸實施例提供許多可應用的發明性概念，可於多種特定上下文中體現該等概念。所論述的特定實施例為說明性的，且並不限制本發明之範疇。
由於積體電路之發明，半導體工業已由於各種電子組件(例如，電晶體、二極體、電阻器、電容器，等)之整合密度的持續改良而經歷了持續快速增長。在很大程度上，整合密度之此改良已來自重複地減小最小特徵大小，從而允許將更多組件整合於給定面積中。
此等整合改良在性質上主要為二維(2D)，因為由 整合之組件佔據的體積主要處於半導體晶圓之表面上。儘管微影術之巨大改良已導致2D積體電路形成中的相當大的改良，但可在兩個維度上達成的密度存在實體限制。此等限制中之一者為製作此等組件所需之最小大小。而且，當將更多裝置置於一個晶片上時，需要更複雜設計。
因此，已製造三維積體電路(3D IC)來解決上述限 制。在3D IC之一些形成製程中，形成各自包括一積體電路之兩個或兩個以上晶圓。鋸切該等晶圓以形成晶粒。封裝且接著在該等裝置對準的情況下結合具有相同或不同裝置之晶粒。矽穿封裝孔(TPV)亦稱為模製穿孔(through-molding-via，TMV)，矽穿封裝孔愈來愈多地用作實施3D IC之方式。諸如TPV之貫穿孔(TV)常常用於3D IC及堆疊晶粒中，以提供電連接及/或輔助熱耗散。除了TPV及TMV之外，TV亦包括矽穿孔(TSV)及其他適用結構。
第1A圖為根據一些實施例的封裝結構100的透 視圖，封裝結構100包括結合至另一封裝120的封裝110，該封裝120進一步結合至另一基板130。晶粒封裝110及120中之每一者包括至少一半導體晶粒(未圖示)。半導體晶粒包括用於半導體積體電路製造中之半導體基板，且積體電路可形成於半導體基板中及/或半導體基板上。半導體基板係指包含半導體材料的任何構造，包括但不限於塊矽、半導體晶圓、絕緣體上矽(SOI)基板或矽鍺基板。亦可使用包括III族、IV族及V族元素之其他半導體材料。半導體基板可進一步包含複數個隔離特徵(未圖示)，諸如淺渠溝隔離(STI)特徵或矽局部氧化(LOCOS)特徵。該等隔離特徵可界定並隔離各種微電子 元件。可形成於半導體基板中之各種微電子元件的實例包括電晶體(例如，金屬氧化物半導體場效應電晶體(MOSFET)、互補金屬氧化物半導體(CMOS)電晶體、雙極接面電晶體(BJT)、高電壓電晶體、高頻率電晶體、p通道及/或n通道場效應電晶體(PFET/NFET)，等)、電阻器、二極體、電容器、電感器、熔絲及其他適當元件。執行各種製程以形成各種微電子元件，該等製程包括沉積、蝕刻、植入、光微影、退火及/或其他適當製程。微電子元件經互連以形成積體電路裝置，諸如邏輯裝置、記憶體裝置(例如，SRAM)、RF裝置、輸入/輸出(I/O)裝置、晶片上系統(SoC)裝置、上述裝置的組合，及其他適當類型的裝置。根據一些實施例，封裝120包括矽穿封裝孔(TPV)，且充當插入物。
基板130可由雙馬來醯亞胺三嗪(BT)樹脂、FR-4 (由編織玻璃纖維布與耐燃性環氧樹脂黏合劑組成之複合材料)、陶瓷、玻璃、塑膠、帶、薄膜，或可載運接收導電端子所需之導電墊或連接盤之其他支撐材料製成。在一些實施例中，基板130為多層電路板。封裝110經由連接器115結合至封裝120，且封裝120經由外部連接器145結合至基板130。 在一些實施例中，外部連接器145為結合之凸塊結構，諸如結合之焊料凸塊或藉由接合焊料層而結合之銅柱。此處描述之焊料可包括鉛或可為無鉛的。
第1B圖圖示根據一些實施例之在晶粒封裝120 上的晶粒封裝110之橫截面圖。如第1B圖中所示，封裝110包括兩個半導體晶粒112及113，其中晶粒113安置於晶粒112上。然而，封裝110可包括一個半導體晶粒或兩個以上半 導體晶粒。在一些實施例中，在晶粒112與113之間存在膠接層(未圖示)。半導體晶粒112及113可包括如上文關於半導體晶粒所描述之各種微電子元件。半導體晶粒112結合至基板115。基板115可包括上文關於基板100所描述之各種材料及/或組件。根據一些實施例，半導體晶粒112經由結合線114電連接至基板115中之導電元件(未圖示)。類似地，半導體晶粒112經由結合線116電連接至基板115中之導電元件。封裝110亦包括模製化合物111，模製化合物111覆蓋半導體晶粒112及113，且亦覆蓋結合線114及116。封裝110亦包括數個連接器117以用於外部連接。連接器117形成於金屬墊118上，金屬墊118藉由互連結構119電連接至結合線114及116，互連結構119可包括通孔及金屬線。
根據一些實施例，如第1B圖中所示，晶粒封裝 120包括半導體晶粒121及圍繞晶粒121之TPV 122。封裝120亦包括重分配結構125，重分配結構125包括一或多個重分配層(RDL)123。重分配層(RDL)123為金屬互連層(該等金屬互連層可包括金屬線及通孔)，且由介電材料圍繞。RDL 123實現晶粒121之扇出。如第1B圖中所圖示，諸如球柵陣列(BGA)之外部連接器126附接至重分配結構125上之金屬墊(未圖示)。如第1B圖中所示，TPV 122連接至封裝110之連接器117。晶粒121及外部連接器126處於重分配結構125之相反側上。晶粒121經由連接器127連接至重分配結構125。
在一些實施例中，晶粒封裝110之連接器117係 由焊料製成。在一些實施例中，連接器117包括在焊料柱末端具有焊料之銅柱。連接器117之焊料結合至填充有銅之TPV 122之暴露銅表面。然而，暴露之銅表面可在暴露於大氣時形成氧化銅。結果，如第1B圖之TPV 122D 中所示，氧化銅層141可形成於TPV 122之表面上。在一些實施例中，儘管可在TPV 122之表面上塗覆助熔劑以移除形成於TPV 122之表面上的氧化銅層，但移除過程不一致。結果，氧化銅層141或至少一部分氧化銅層141保留於諸如TPV 122D 之一些TPV 122上。連接器126之焊料並不很好地結合至氧化銅層141；因此，接點將較弱，此可影響良率及可靠性。
即使助熔劑自諸如TPV 122A 、122B 及122C 之TPV 移除氧化銅層，連接器126之焊料與TPV之銅之間的直接接觸仍將導致形成金屬間化合物(IMC)，諸如Cu：Sn。第1B圖圖示根據一些實施例，形成於連接器126之焊料與TPV 122A 、122B 及122C 之銅之間的IMC層142。由於封裝120上的不同元件的熱膨脹係數(CTE)不同，封裝120可能在封裝過程期間及/或之後折曲。此折曲(或翹曲)對於由結合連接器126與TPV 122形成於封裝120與封裝110之間的結合結構產生應力。應力將引起在結合結構260(由連接器117及TPV 122形成)之TPV 122與連接器117之間的介面處形成的IMC層142附近斷裂，從而影響層疊封裝(PoP)結構之良率及可靠性。因此，需要用於在晶粒封裝之間形成結合結構而無上述問題的機構。
第2A圖至第2O圖圖示根據一些實施例的製備層 疊封裝(PoP)裝置之依序過程流的橫截面圖。第2A圖圖示在載體201上的黏著層(或膠接層)202。根據一些實施例，載體201由玻璃製成。然而，其他材料亦可用於載體201。在一 些實施例中，黏著層202沉積或層壓於載體201上。黏著層202可由膠形成，或可為諸如箔片之層壓材料。在一些實施例中，黏著層202為光敏層，且易於藉由在完成所涉及的封裝過程120之後將紫外(UV)光或雷射照射於載體201上而自載體201脫離。舉例而言，黏著層202可為由3M公司(St.Paul，Minnesota)製造之光熱轉換(LTHC)塗層。在一些其他實施例中，黏著層202係熱敏層。
在一些實施例中，在黏著層202上形成鈍化層 208。鈍化層208係介電的，且充當晶粒封裝上之鈍化層。在一些實施例中，鈍化層208係由諸如聚醯亞胺、聚苯并噁唑(PBO)或焊料抗蝕劑之聚合物製成。鈍化層208改良形成於載體201上的塗鍍種子層(下文描述)之黏附。若塗鍍種子層可良好地黏附至黏著層202，則可略去鈍化層208之形成。
根據一些實施例，如第2B圖中所示，接著在鈍化層208上形成塗鍍種子層204。在一些實施例中，塗鍍種子層204係由銅製成，且係藉由物理氣相沉積(PVD)而形成。然而，亦可使用其他導電薄膜。舉例而言，塗鍍種子層204可由Ti、Ti合金、Cu及/或Cu合金製成。Ti合金及Cu合金可包括銀、鉻、鎳、錫、金、鎢，及上述之組合。在一些實施例中，塗鍍種子層204之厚度可在約0.05微米(μm)至約1.0μm之範圍內。在一些實施例中，塗鍍種子層204包括擴散障壁層，該擴散障壁層係在沉積塗鍍種子層之前形成。塗鍍種子層204亦可充當至下層的黏附層。在一些實施例中，擴散障壁層係由Ti製成，厚度在約0.01μm至約0.1μm之範圍內。然而，擴散障壁層可由諸如TaN或其他適用材料之其他材料 製成，且厚度範圍不限於上述範圍。在一些實施例中，擴散障壁層係藉由PVD形成。
根據一些實施例，如第2C圖中所示，在沉積塗 鍍種子層204之後，在塗鍍種子層204上形成光阻層205。光阻層205可藉由諸如旋塗製程之濕式製程或藉由諸如幹薄膜之乾式製程形成。在形成光阻層205之後，對光阻層205進行圖案化以形成開口206，開口206經填充以形成上文在第1B圖中所述之TPV。所涉及之製程包括光微影及抗蝕劑顯影。在一些實施例中，開口206之寬度W可在約40μm至約260μm之範圍內。在一些實施例中，開口206之深度D可在約5μm至約300μm之範圍內。
此後，根據一些實施例，如第2D圖中所示，在 塗鍍種子層204上塗鍍導電層207以填充開口206。在一些實施例中，導電層207係由銅或銅合金製成。在一些實施例中，層207之厚度D可在約5μm至約300μm之範圍內。
在塗鍍以填充間隙之製程之後，藉由蝕刻製程移 除光阻層205，該蝕刻製程可為乾式或濕式製程。在一些實施例中，在移除光阻層205之前，使用平坦化製程以移除形成於光阻層205之表面203上的過多導電層207。第2E圖圖示根據一些實施例在移除光阻層205且將開口206中之導電層207暴露為(導電)柱體122’之後的載體201上的結構之橫截面圖。
在移除光阻層205且將導電層207圖示為柱體 122’之後，移除暴露之塗鍍種子層204或塗鍍種子層204之不在導電層207下方的部分。塗鍍種子層204係藉由蝕刻，諸 如藉由濕式蝕刻移除。為移除銅，可使用具有磷酸(H3 PO4 )及過氧化氫(H2 O2 )之水溶液。若塗鍍種子層204包括諸如Ti層之擴散障壁層，可使用HF水溶液。第2E圖圖示保留在導電層207下方之塗鍍種子層204，且移除其餘部分(或暴露部分)。
此後，根據一些實施例，如第2F圖中所示，藉由膠接層210將半導體晶粒121附著至載體201上的表面209。根據一些實施例，膠接層210係由晶粒附著薄膜(DAF)製成。DAF可由環氧樹脂、酚醛樹脂、丙烯酸橡膠、矽石填充物或上述材料之組合製成。第2F圖圖示晶粒121之連接器127背對在鈍化層208上的表面209。接著將液體模製化合物材料塗覆於載體201上塗鍍種子層204之表面上以填充導電柱體122’與晶粒121之間的空間，且覆蓋晶粒121及導電柱體122’。接著施加熱製程以硬化模製化合物材料，並將模製化合物材料轉變為模製化合物123。根據一些實施例，如第2G圖中所示，在模製化合物123經形成以圍繞導電柱體122’時，導電柱體122’變為TPV 122”。
此後，應用平坦化製程以移除過多模製化合物123，從而暴露TPV 122”及晶粒121之連接器127。在一些實施例中，平坦化製程為研磨製程。在一些其他實施例中，平坦化製程為化學機械拋光(CMP)製程。根據一些實施例，第2H圖中圖示後平坦化結構。
根據一些實施例，如第2I圖中所示，在平坦化製程之後，重分配結構125形成於第2H圖之結構上的表面211上。第2I圖圖示第二重分配結構125包括RDL 213，RDL 213 藉由諸如層212及214之一或多個鈍化層絕緣。RDL 213可包括金屬線及導電通孔。RDL 213係由導電材料製成，且直接接觸TPV 122”及晶粒121之連接器127。在一些實施例中，RDL 213係由鋁、鋁合金、銅或銅合金製成。然而，RDL 213可由其他類型的導電材料製成。鈍化層212及214係由介電材料製成，且對在結合外部連接器126與基板130期間引起的結合應力提供應力釋放。在一些實施例中，鈍化層212及214係由諸如聚醯亞胺、聚苯并噁唑(PBO)或苯并環丁烯(BCB)之聚合物製成。鈍化層214經圖案化以形成開口(未圖示)，以暴露RDL 123之多個部分以形成結合墊(未圖示)。在一些實施例中，在結合墊上形成凸塊下冶金(UBM)層。UBM層亦可對鈍化層214的開口的側壁加襯。在一些實施例中，RDL213可為單一層。
重分配層及結合結構以及重分配層及結合結構的 形成方法之實例描述於2012年3月22日申請(代理人檔案號碼TSMC2011-1339)之題為「Bump Structures for Multi-Chip Packaging」的美國申請案第13/427,753號及2011年12月28日申請(代理人檔案號碼TSMC2011-1368)之題為「Packaged Semiconductor Device and Method of Packaging the Semiconductor Device」的美國申請案第13/338,820號中。上述兩申請案之全文皆以引用之方式併入本文中。
根據一些實施例，如第2J圖中所示，在形成重分 配結構125之後，將外部連接器126安裝於(或結合至)重分配結構125之結合墊(未圖示)上。根據一些實施例，對載體201上之晶粒進行電測試以檢查晶粒之功能性，且亦檢 查TPV 122”、重分配結構125及結合之外部連接器126的形成品質。在一些實施例中，亦執行可靠性測試。
根據一些實施例，如第2K圖中所示，在將外部連接器126安裝於結合墊上之後，將第2J圖中之結構翻轉且附著至帶219。根據一些實施例，帶219為光敏性的，且可易於藉由將紫外(UV)光照射於帶219上而自晶粒121之晶粒封裝脫離。在將第2J圖之結構附著至帶219之後，移除黏著層202。根據一些實施例，使用雷射來提供熱以移除黏著層202。第2L圖圖示移除黏著層202之後的第2K圖之結構。
根據一些實施例，如第2M圖中所示，在移除黏著層202之後，移除模製化合物123及鈍化層208之圍繞TPV 122”之頂部部分(遠離連接器126之部分，或末端部分)的部分。在一些實施例中，使用雷射工具來移除(藉由鑽孔)材料，諸如圍繞TPV 122”之頂部部分的模製化合物123及鈍化層208，以暴露頂部部分。第3A圖至第3H圖圖示圍繞TPV 122之暴露之頂部部分的結構之各種實施例，該等結構將在下文更詳細描述。
在移除模製化合物123及鈍化層208之圍繞TPV 122”之頂部部分的部分之後，完成半導體晶粒121之封裝過程，且將半導體晶粒121封裝為經封裝晶粒120’。根據一些實施例，接著將帶219上之經封裝晶粒120’切割為個別經封裝晶粒120’。藉由晶粒鋸來完成切割。在完成切割之後，自經封裝晶粒移除帶219。第2N圖圖示根據一些實施例的在移除帶219之後的經封裝晶粒120’。第2N圖中區域X包括TPV 122”。區域X中之結構的各種實施例圖示於第3A圖至第3H 圖中且於下文描述。
接著將個別經封裝晶粒120’結合至其他晶粒封裝 以形成層疊封裝(PoP)結構。根據一些實施例，如第2O圖中所示，將晶粒封裝110置放於晶粒封裝120’之上且結合至晶粒封裝120’。將晶粒封裝110之外部連接器117結合至晶粒封裝120’之TPV 122”以形成結合結構260’。每一TPV 122”包括由銅製成之主體及可由銅、Ti或銅及Ti的組合製成之塗鍍種子層204。將連接器117結合至PTV 122”涉及回焊製程，該回焊製程可使得在PTV 122”之外部(及先前暴露之)輪廓附近形成IMC層142’。若IMC層142”包括於塗鍍種子層204中，則IMC層142”含有銅、焊料及Ti。在一些實施例中，IMC層142'之厚度可在約0.5μm至約10μm之範圍內。
藉由移除圍繞TPV 122”之頂部部分的材料以形成 圍繞TPV 122”之頂部部分的開口220，形成於每一TPV 122”上之IMC層142”並不為諸如第1B圖之IMC層142之二維(2D)表面層，該二維(2D)表面層容易在應力下於拐角處破裂。而是，如第2O圖中所示，IMC層142”為覆蓋TPV 122”之部分的表面之三維(3D)層，該三維(3D)層突出於模製化合物123之上。此3D層較強韌且較不可能在應力下破裂。結果，藉由連接器117及TPV 122”形成之結合結構比無開口220之結構(諸如第1B圖中描述之結構)更強韌。第2O圖中之區域Y包括具有連接器117及TPV 122”之結合結構260’。區域Y中之結構的各種實施例圖示於第4A圖至第4C圖中且於下文描述。
第3A圖圖示根據一些實施例的第2N圖之區域X 的放大圖。區域X包括TPV 122”，該TPV 122”由模製化合物123圍繞。TPV 122”連接至RDL 213，如上所述，RDL 213藉由鈍化層212及214絕緣。第3A圖圖示TPV 122”包括在導電層207上之塗鍍種子層204。諸如藉由雷射鑽孔來移除鈍化層208及覆蓋塗鍍種子層204及導電層207之頂部部分之模製化合物123，以形成開口300。若塗鍍種子層204及導電層207皆由諸如銅或銅合金之相同導電材料製成，則TPV 122”將看似係由單一材料製成而無明顯介面。
開口300具有在208之表面301下方的深度D1 。 在一些實施例中，D1 在約2μm至約100μm之範圍內。開口300具有在塗鍍種子層204之表面302下方的深度D2 。在一些實施例中，D2 在約1μm至約70μm之範圍內。開口300之下部部分具有自TPV 122”之側壁之表面304至模製化合物123之側壁的表面303之寬度W1 。在一些實施例中，W1 在約2μm至約50μm之範圍內。開口300之頂部寬度W2 寬於TPV 122”之寬度W。在一些實施例中，W2 在約30μm至約300μm之範圍內。
第3A圖圖示開口之側壁303實質上豎直且實質 上垂直於開口300之底表面。此外，側壁之表面係連續且光滑的。或者，根據一些實施例，如第3B圖中所示，開口300’之模製化合物123處的拐角可經磨圓。諸如開口300’之D1 、D2 、W1 及W2 的範圍之其餘部分類似於開口300。
第3A圖及第3B圖圖示鈍化層208之側壁及模製 化合物123之側壁的連接302A 及302B 係光滑的。側壁之間的光滑連接302A 及302B 係藉由控制雷射鑽孔製程而達成，雷射 鑽孔製程的處理參數包括鑽孔能量、鑽孔角度及鑽孔時間。鑽孔製程經調諧以移除鈍化層208及模製化合物123，而不移除塗鍍層204或導電層207。在一些實施例中，鑽孔能量在0.1 mJ至約30 mJ之範圍內。在一些實施例中，鑽孔角度在約0度(垂直於表面301)至約85度(與鈍化層208之表面301的法線所成的角度)之範圍內。在一些實施例中，鑽孔時間對於每一開口300A 或300B 在約1 s至約150 s之範圍內。
如上所述，第3A圖及第3B圖圖示鈍化層208之側壁及模製化合物123之側壁的連接302A 及302B 係光滑的。或者，此等兩個層之側壁之間的連接可為不光滑的。第3C圖示根據一些實施例之開口300C ，其中模製化合物123之側壁303實質上豎直。然而，鈍化層208之側壁與平行於鈍化層208之表面302的表面成角度而傾斜。在一些實施例中，角度在約1度至約85度之範圍內。結果，鈍化層208之開口300C 的側壁與模製化合物123之間的連接302C 並不光滑且具有尖銳拐角。開口300C 之最寬部分具有寬度W3 。在一些實施例中，W3 在約30μm至約300μm之範圍內。諸如開口300C 之D1 、D2 、W1 及W3 的範圍之其餘部分類似於第3A圖之彼等範圍。雷射鑽孔製程可經調諧以產生第3A圖中所示之輪廓。鈍化層208及模製化合物123之其他側壁輪廓亦係可能的。
第3D圖圖示根據一些實施例之開口300D ，其中鈍化層208及模製化合物123之側壁與平行於鈍化層208之表面301的表面成角度而傾斜。在一些實施例中，角度在 約10度至約85度之範圍內。諸如第3D圖之D1 、D2 及W3 的範圍之其餘部分類似於第3C圖。
第3E圖圖示根據一些實施例的開口300E ，其具 有模製化合物123上之傾斜側壁及鈍化層208上之實質上豎直側壁。在模製化合物123之側壁與鈍化層208之側壁之間的連接302E 上存在一突出部分。突出部分的距離W4 在約2μm至約40μm之範圍內。諸如第3E圖之D1 、D2 、W2 、W3 及角度的範圍之其餘部分類似於第3C圖及第3D圖中所描述之彼等範圍。
第3F圖圖示根據一些實施例之開口300F ，其中塗鍍種子層204F 大於導電層207。第3F圖之結構類似於第3A圖之結構，不同之處在於塗鍍種子層204F 寬於導電層207。寬度差(或突出寬度)W5 在約0.001μm至約1μm之範圍內。如第2E圖中所示，塗鍍種子層204F 之突出部分係在移除未由導電層207覆蓋之塗鍍種子層204期間形成。移除製程之蝕刻時間經控制以留下小部分未由導電層207覆蓋之塗鍍種子層204。諸如第3F圖之D1 、D2 、W1 及W2 的範圍之其餘部分類似於第3A圖中描述之彼等範圍。然而，第3B圖至第3E圖中描述之其他輪廓亦可應用於第3F圖之實施例中。
第3G圖圖示根據一些實施例之開口300G ，其中塗鍍種子層204F 自導電層207凹入。第3G圖類似於第3F圖，不同之處在於塗鍍種子層204G 窄於導電層207。凹部W6 在約0.001μm至約1μm之範圍內。如第2E圖中所描述，凹部可藉由在移除未由導電層207覆蓋之塗鍍種子層204期間之過蝕刻(或具有較長蝕刻時間)而形成。類似地，第3B圖至第 3E圖中描述之其他輪廓亦可應用於第3G圖之實施例中。
第3H圖圖示根據一些實施例的開口300H ，該開口300H 具有模製化合物123上之實質上側壁而不具有鈍化層208。在此情況下移除鈍化層208。根據一些實施例，鈍化層208係在形成開口300H 之前被移除。諸如第3H圖之D2 、W1 及W2 的範圍之其餘部分類似於第3A圖中描述之彼等範圍。第3B圖(開口之經磨圓下部拐角)、第3D圖(傾斜側壁)、第3F圖(突出之塗鍍種子層)及第3G圖(凹入之塗鍍種子層)中描述之其他輪廓亦可應用於第3H圖之實施例中。
如上所述，第2O圖中之區域Y包括結合結構260’，該結合結構260’具有來自上部晶粒封裝110之連接器117及下部晶粒封裝120’之TPV 122”。下文描述區域Y中之結構的各種實施例。第4A圖圖示根據一些實施例之結合結構260’，結合結構260’具有結合至未嵌入於模製化合物123及鈍化層208中之TPV 122”的頂部部分之連接器117。結合之前在TPV 122”附近的結構為上述第3D圖與第3E圖之結構之間的混合。開口300’具有在鈍化層208及模製化合物123兩者上的傾斜側壁。如第4A圖中所示，鈍化層208自模製化合物123之邊緣凹回。在結合製程(熱製程)之後，藉由諸如Cu、Ti或兩者之材料在塗鍍種子層204及連接器之焊料材料中形成IMC層142’。取決於結合製程，導電層207(銅)之一部分可處於IMC層142’中。IMC層142’在TPV 122”之突出部分周圍封頂。IMC層142具有實質上平坦之頂部部分及形成圍繞突出之TPV 122”的環之側部部分。IMC層142’具有在約0.2μm至約8μm之範圍內的厚度。連接器117之上部 部分可形成具有結合墊118之另一IMC層143。IMC層143之厚度取決於結合墊118之材料。諸如Ni、Au、Ag之一些導電材料並不與連接器117中的焊料形成極薄的IMC層143。因此，在一些實施例中，IMC層143可能不存在。
由於圍繞TPV 122"之突出部分的開口300’，連接器117之置放將更準確，且連接器117將不會水平滑動至TPV 122”之遺漏部分。當連接器117經置放且結合至與模製化合物123齊平之TPV 122(諸如第1B中之TPV)時，可能發生連接器117之水平滑動。此滑動可能導致連接器117短路至鄰近TPV 122。此外，所形成之IMC層142’經成形為蓋帽(3D結構)而非表面(2D結構)。結果，IMC 142’並不容易變為結合結構之最弱點，且並不如第1B圖之結合結構260般容易破裂。若干研究支持此觀測結果。結合結構260’之良率及可靠性比結合結構260好。
第4B圖圖示根據一些實施例之結合結構260’的嵌入於聚合物層270中的部分。如上所述，已諸如藉由雷射鑽孔移除圍繞TPV 122”之頂部部分之模製化合物123。鈍化層208可或可不存在於模製化合物123上。鈍化層208之存在係任選的。聚合物層270形成於結合結構260”之下部部分周圍。在將晶粒封裝110結合至晶粒封裝120’之前，可將助熔劑塗覆於晶粒封裝120’之表面上，且覆蓋TPV 122”及模製化合物123之暴露表面。所塗覆之助熔劑在結合製程期間呈現暴露之塗鍍種子層204及導電層207之來自環境的氧化。當將助熔劑塗覆於封裝120’之表面上時，助熔劑為含有聚合物之液體，且通常在完成結合製程之後諸如藉由清潔溶液而 移除。然而，助熔劑可留在封裝120’之表面上，且成為聚合物層270，聚合物層270在應力下屈服且可保護結合結構260’免於破裂。含於助熔劑中之聚合物可為環氧樹脂或其他類型之聚合物。聚合物層270之厚度DF 在約0.5μm至約30μm之範圍內。厚度DF可在鈍化層208不存在的情況下自模製化合物123之表面量測，或在鈍化層208存在的清下自鈍化層208之表面量測。封裝110之面向封裝120’的表面305與模製化合物123之表面306之間存在距離DS 。根據一些實施例，DF 小於DS 。
第4C圖圖示根據一些實施例之嵌入於未充滿填 充物(underfill)275中之結合結構260’。如上所述，已諸如藉由雷射鑽孔移除圍繞TPV 122”之頂部部分之模製化合物123。鈍化層208可或可不存在於模製化合物123上。鈍化層208之存在係任選的。未充滿填充物275經形成以在將連接器117結合至TPV 122”之後圍繞結合結構260’。未充滿填充物275含有聚合物，諸如UF3808及UF3810(兩者皆為基於環氧樹脂之未充滿填充材料)。如第4C圖中所示，未充滿填充物275填充晶粒封裝110與120’之間的空間。由聚合物製成之未充滿填充物275產生較小應力且保護結合結構260’免於破裂。
提供用於形成矽穿封裝孔(TPV)之機制及具有利 用TPV之結合結構的層疊封裝(PoP)裝置之各種實施例，該等矽穿封裝孔具有圍繞TPV之末端部分的開口。該等開口係諸如藉由雷射鑽孔移除圍繞TPV之末端部分的材料而形成。圍繞晶粒封裝之TPV的末端部分之開口使得形成於另一晶粒封 裝之間的結合結構的焊料能夠保持於開口中而不滑動，且因此增加結合結構之良率及可靠性。亦可添加聚合物以填充圍繞TPV之開口，或甚至填充晶粒封裝之間的空間以減小結合結構在應力下之破裂。
在一些實施例中，提供一種半導體裝置。該半導 體裝置包括一半導體晶粒及鄰近於該半導體晶粒之介電材料。該半導體裝置亦包括安置於該介電材料中之矽穿封裝孔(TPV)。該介電材料中之開口圍繞TPV之末端部分以暴露該末端部分，且其中該開口之至少一部分介於該TPV之末端部分與模製化合物之間。
在一些實施例中，提供一種半導體裝置。該半導 體裝置包括一半導體晶粒及鄰近於該半導體晶粒之一或多個介電層。該半導體晶粒亦包括安置於該一或多個介電層中之一或多個矽穿封裝孔(TPV)。該一或多個TPV自該一或多個介電層之第一側延伸至該一或多個介電層之第二側。該半導體裝置進一步包括在圍繞該一或多個TPV之相應末端的一或多個介電層中之凹部。該等凹部暴露該一或多個TPV之相應末端的側壁之至少一部分。
在又一些實施例中，提供一種半導體裝置。該半 導體裝置包括第一晶粒封裝。該第一晶粒封裝包括第一半導體晶粒及在該第一半導體晶粒之對置側上的介電材料。該第一晶粒封裝亦包括在該介電材料中之貫穿孔(TV)，且在該介電材料中之開口圍繞該TV之一末端部分以暴露該末端部分。該半導體裝置亦包括第二晶粒封裝。該第二晶粒封裝包括第二半導體晶粒及外部連接器。該第二晶粒封裝之該外部 連接器使用焊料結合至該第一晶粒封裝之TV之末端部分以形成結合結構。該焊料至少部分在該開口內。
儘管已詳細描述實施例及該等實施例的優勢，但應理解，可在不脫離如由隨附申請專利範圍界定之實施例之精神及範疇的情況下在本文中進行各種改變、替代及更改。此外，本申請案之範疇並不意欲限於本說明書中所描述之製程、機器、製造以及物質組合、構件、方法及步驟之特定實施例。一般熟習此項技術者將自本發明易於瞭解，可根據本發明利用當前存在或稍後開發之與本文描述之相應實施例執行實質上相同之功能或達成實質上相同之結果的製程、機器、製造、物質組成、構件、方法或步驟。因此，所附申請專利範圍意欲在本發明範疇內包括此些製程、機器、製造、物質組成、構件、方法或步驟。此外，每一請求項構成一單獨實施例，且各請求項及實施例之組合在本發明之範疇內。
110‧‧‧晶粒封裝
112‧‧‧半導體晶粒
113‧‧‧半導體晶粒
114‧‧‧結合線
115‧‧‧連接器/基板
116‧‧‧結合線
117‧‧‧連接器
118‧‧‧金屬墊
120‧‧‧晶粒封裝
121‧‧‧半導體晶粒
122‧‧‧TPV
122A‧‧‧TPV
122B‧‧‧TPV
122C‧‧‧TPV
122D‧‧‧TPV
123‧‧‧重分配層/模製化合物
125‧‧‧重分配結構
126‧‧‧外部連接器
127‧‧‧連接器
141‧‧‧氧化銅層
142‧‧‧IMC層
260‧‧‧結合結構

Claims (10)

  1. 一種半導體裝置，包含：一半導體晶粒；一介電材料，鄰接該半導體晶粒；及一矽穿封裝孔(TPV)，安置於該介電材料中，其中該介電材料界定一開口以暴露該TPV之一末端部分，且其中該開口產生一寬度介於該TPV之該末端部分與該介電材料之間。
  2. 如請求項1所述之半導體裝置，其中該TPV之該末端部分包括一塗鍍種子層及一導電層，且其中該塗鍍種子層覆蓋該導電層之一末端表面。
  3. 如請求項1所述之半導體裝置，其中該TPV之該末端部分包括一塗鍍種子層及一導電層，且其中該塗鍍種子層覆蓋該導電層之一末端表面之僅一部分。
  4. 如請求項1所述之半導體裝置，其中該開口具有一有角度的表面輪廓。
  5. 如請求項1所述之半導體裝置，其中該開口包括該介電材料之一直線側壁，該直線側壁與該TPV之一直線側壁相交。
  6. 如請求項1所述之半導體裝置，其中該介電材料包含一模製化合物層及在該模製化合物層上之一鈍化層，且其中該鈍化層及該模製化合物環繞該TPV之該末端部分。
  7. 一種半導體裝置，包含：一半導體晶粒；鄰近於該半導體晶粒之一或多個介電層；一或多個矽穿封裝孔(TPV)，安置於該一或多個介電層中之， 該一或多個TPV自該一或多個介電層之第一側延伸至該一或多個介電層之一第二側；以及複數個凹部，在圍繞該一或多個TPV之相應末端的該一或多個介電層中，該等凹部暴露該一或多個TPV之相應末端的側壁之至少一部分。
  8. 一種半導體裝置，包含：一第一晶粒封裝，其中該第一晶粒封裝包含：一第一半導體晶粒；在該第一半導體晶粒之相對側上的介電材料；以及在該介電材料中之一貫穿孔(TV)，其中在該介電材料中之一開口圍繞該TV之一末端部分以暴露該末端部分；及一第二晶粒封裝，其中該第二晶粒封裝包含：一第二半導體晶粒；及一外部連接器；其中該第二晶粒封裝之該外部連接器使用焊料結合至該第一晶粒封裝之該TV之該末端部分以形成一結合結構，其中該焊料至少部分在該開口內。
  9. 如請求項8所述之半導體裝置，進一步包含形成於該外部連接器與該TV之該末端部分之間的一金屬間化合物(IMC)層，其中該IMC層覆蓋該TV之該末端部分。
  10. 如請求項9所述之半導體裝置，其中該PV之該末端部分自該開口之一底部突出約1μm至約70μm之一距離。
TW102130057A 2013-01-31 2013-08-22 具有圍繞矽穿封裝孔（ＴＰＶ）的末端部分之開口的晶粒封裝及使用該晶粒封裝之層疊封裝（ＰｏＰ） TWI514542B (zh)

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