JP4917874B2 - 積層型パッケージ及びその製造方法 - Google Patents
積層型パッケージ及びその製造方法 Download PDFInfo
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- JP4917874B2 JP4917874B2 JP2006336276A JP2006336276A JP4917874B2 JP 4917874 B2 JP4917874 B2 JP 4917874B2 JP 2006336276 A JP2006336276 A JP 2006336276A JP 2006336276 A JP2006336276 A JP 2006336276A JP 4917874 B2 JP4917874 B2 JP 4917874B2
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Description
基板に電子素子が搭載された複数のパッケージを、接続部を用いて電気的に接続しつつ積層してなる積層型パッケージにおいて、
前記積層型パッケージは、
上層基板の両面にソルダーレジストが形成され、前記ソルダーレジストの開口部から露出するように電極が設けられ、
前記上層基板の一方の面には半導体素子が実装され、前記半導体素子は前記上層基板の同一面に形成された電極と電気的に接続され、
前記上層基板の他方の面に形成された電極上にはんだ接合部が設けられた上層パッケージと、
下層基板の両面にソルダーレジストが形成され、前記ソルダーレジストの開口部から露出するように電極が設けられ、
前記下層基板の一方の面には半導体素子が実装され、前記半導体素子は前記下層基板の同一面に形成された電極と電気的に接続され、
前記下層基板は下層基板を厚さ方向に貫通して形成された挿通孔を有し、
前記挿通孔には電極が形成され、
前記下層基板の他方の面の電極、前記挿通孔には、はんだボールが形成された下層パッケージと、を有しており、
前記上層パッケージと前記下層パッケージとは、柱状部材を用いて積層されており、
前記柱状部材の上端部は前記はんだ接合部と接続され、下端部は前記挿通孔に形成された前記電極と電気的に接続していることを特徴とするものである。
請求項1記載の積層型パッケージにおいて、
前記柱状部材は、銅製のピンであり、その表面に金メッキの表面膜が施されていることを特徴とするものである。
請求項1又は2記載の積層型パッケージにおいて、
前記柱状部材は、弾性変形可能な材料よりなることを特徴とするものである。
請求項1乃至3いずれか一項に記載の積層型パッケージにおいて、
前記柱状部材と前記貫通孔に形成された前記電極との接続において、前記下層基板の一方の面の表面にはんだが設けられていることを特徴とするものである。
基板に電子素子が搭載された複数のパッケージを、接続部を用いて電気的に接続しつつ積層する積層型パッケージの製造方法であって、
上層基板の両面にソルダーレジストが形成され、前記ソルダーレジストの開口部から露出するように電極が設けられ、
前記上層基板の一方の面には半導体素子が実装され、前記半導体素子は前記上層基板の同一面に形成された電極と電気的に接続されている上層パッケージを形成する工程と、
下層基板の両面にはソルダーレジストが形成され、前記ソルダーレジストの開口部から露出するように電極が設けられ、
前記下層基板の一方の面には半導体素子が実装され、前記半導体素子は前記下層基板の同一面に形成された電極と電気的に接続され、
前記下層基板は下層基板を厚さ方向に貫通して形成された挿通孔を有しており、
前記挿通孔には電極が形成されている下層パッケージを形成する工程と、
前記上層基板の他方の面のはんだ接合部に前記柱状部材を配設する配設工程と、
前記柱状部材を前記下層パッケージの挿通孔に挿入することにより前記下層パッケージ上に前記上層パッケージが支持されるよう積層し、該柱状部材と前記下層パッケージとを接合する接合工程と
前記下層基板の他方の面の電極、前記挿通孔に、はんだボールを形成する工程と、
を有することを特徴とするものである。
11A〜11C 下層パッケージ
12A〜12C 上層パッケージ
13A〜13C 柱状部材
14A〜14C 下層基板
15A〜15C 上層基板
16 はんだボール
17,37 下部電極
18,38 上部電極
20,21,40,41 半導体素子
25,26,45,46 ワイヤ
27,47 はんだ接合部
28 表面膜
29 挿通孔
Claims (5)
- 基板に電子素子が搭載された複数のパッケージを、接続部を用いて電気的に接続しつつ積層してなる積層型パッケージにおいて、
前記積層型パッケージは、
上層基板の両面にソルダーレジストが形成され、前記ソルダーレジストの開口部から露出するように電極が設けられ、
前記上層基板の一方の面には半導体素子が実装され、前記半導体素子は前記上層基板の同一面に形成された電極と電気的に接続され、
前記上層基板の他方の面に形成された電極上にはんだ接合部が設けられた上層パッケージと、
下層基板の両面にソルダーレジストが形成され、前記ソルダーレジストの開口部から露出するように電極が設けられ、
前記下層基板の一方の面には半導体素子が実装され、前記半導体素子は前記下層基板の同一面に形成された電極と電気的に接続され、
前記下層基板は下層基板を厚さ方向に貫通して形成された挿通孔を有し、
前記挿通孔には電極が形成され、
前記下層基板の他方の面の電極、前記挿通孔には、はんだボールが形成された下層パッケージと、を有しており、
前記上層パッケージと前記下層パッケージとは、柱状部材を用いて積層されており、
前記柱状部材の上端部は前記はんだ接合部と接続され、下端部は前記挿通孔に形成された前記電極と電気的に接続していることを特徴とする積層型パッケージ。 - 前記柱状部材は、銅製のピンであり、その表面に金メッキの表面膜が施されていることを特徴とする請求項1記載の積層型パッケージ。
- 前記柱状部材は、弾性変形可能な材料よりなることを特徴とする請求項1又は2記載の積層型パッケージ。
- 前記柱状部材と前記貫通孔に形成された前記電極との接続において、前記下層基板の一方の面の表面にはんだが設けられていることを特徴とする請求項1乃至3いずれか一項に記載の積層型パッケージ。
- 基板に電子素子が搭載された複数のパッケージを、接続部を用いて電気的に接続しつつ積層する積層型パッケージの製造方法であって、
上層基板の両面にソルダーレジストが形成され、前記ソルダーレジストの開口部から露出するように電極が設けられ、
前記上層基板の一方の面には半導体素子が実装され、前記半導体素子は前記上層基板の同一面に形成された電極と電気的に接続されている上層パッケージを形成する工程と、
下層基板の両面にはソルダーレジストが形成され、前記ソルダーレジストの開口部から露出するように電極が設けられ、
前記下層基板の一方の面には半導体素子が実装され、前記半導体素子は前記下層基板の同一面に形成された電極と電気的に接続され、
前記下層基板は下層基板を厚さ方向に貫通して形成された挿通孔を有しており、
前記挿通孔には電極が形成されている下層パッケージを形成する工程と、
前記上層基板の他方の面のはんだ接合部に前記柱状部材を配設する配設工程と、
前記柱状部材を前記下層パッケージの挿通孔に挿入することにより前記下層パッケージ上に前記上層パッケージが支持されるよう積層し、該柱状部材と前記下層パッケージとを接合する接合工程と
前記下層基板の他方の面の電極、前記挿通孔に、はんだボールを形成する工程と、
を有することを特徴とする積層型パッケージの製造方法。
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US11/953,365 US7928557B2 (en) | 2006-12-13 | 2007-12-10 | Stacked package and method for manufacturing the package |
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US8981559B2 (en) | 2012-06-25 | 2015-03-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package on package devices and methods of packaging semiconductor dies |
US9378982B2 (en) * | 2013-01-31 | 2016-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Die package with openings surrounding end-portions of through package vias (TPVs) and package on package (PoP) using the die package |
JP2015015302A (ja) * | 2013-07-03 | 2015-01-22 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
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US9659891B2 (en) * | 2013-09-09 | 2017-05-23 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device having a boundary structure, a package on package structure, and a method of making |
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