TWI466265B - 積層型封裝體及其製造方法 - Google Patents

積層型封裝體及其製造方法 Download PDF

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Publication number
TWI466265B
TWI466265B TW096147601A TW96147601A TWI466265B TW I466265 B TWI466265 B TW I466265B TW 096147601 A TW096147601 A TW 096147601A TW 96147601 A TW96147601 A TW 96147601A TW I466265 B TWI466265 B TW I466265B
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Taiwan
Prior art keywords
package
substrate
electrode
solder
laminated
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TW096147601A
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English (en)
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TW200828565A (en
Inventor
Oi Kiyoshi
Chino Teruaki
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Shinko Electric Ind Co
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Publication of TW200828565A publication Critical patent/TW200828565A/zh
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Publication of TWI466265B publication Critical patent/TWI466265B/zh

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    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
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    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
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    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
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Description

積層型封裝體及其製造方法
本申請案主張2006年12月13日所提出之日本專利申請案第2006－336276號之優先權，以提及方式併入該優先權申請案之全部。
本揭露係有關於一種積層型封裝體及一種製造該封裝體之方法。更特別地，本揭露係有關於一種堆疊複個封裝體同時使用連接部將該複數個封裝體電性連接在一起之積層型封裝體及一種用以製造該封裝體之方法。
例如像專利文件1所述，最近已商業化一種稱為一藉由封裝複數個半導體元件或被動零件而成為單一封裝體所實現之系統級封裝單體(system－in－package)的模組產品。圖7顯示依據該相關技藝之一範例的一系統級封裝單體100。
該圖式所示之系統級封裝單體100且有一種結構，其中在一下封裝體111上堆疊一上封裝體112。藉由覆晶接合在一下基板114之上表面上安裝一半導體元件120，以及在該下基板114之下表面上提供焊球116。此外，在該下基板114之上表面上形成上電極118。
在該上封裝體112中，在一上基板115上堆疊半導體元件140及141，以及藉由打線接合使該等半導體元件140及141與該上基板115彼此連接。以樹脂密封該等半導體元件140及141。再者，再者，在該上基板115之下表面上形成下電極138。
為了在該下封裝體111上安裝該上封裝體112，在該等上電極118與該等下電極138間插入用於堆疊目的之焊球113，藉以電性連接該上封裝體112至該下封裝體111及在該下封裝體111上支撐該上封裝體112。
[專利文件1]日本專利未審查公告第11－008474號
然而，在該等焊球113做為用以電性連接該下封裝體111至該上封裝體112之裝置及用以在該下封裝體111上支撐該上封裝體112之結構中，由該等焊球113之尺寸(直徑)決定該下封裝體111與該上封裝體112間之距離。
因此，例如：當在該下封裝體111中之下基板114上堆疊複數個半導體元件以導致該下封裝體111之高度的增加時，必須相應地增加該等焊球113之直徑。當增加該等焊球113之直徑以便對應於該等封裝體111及112間之距離時，該等焊球113自然會相對於該等基板114及115之每一基板的平面方向(水平方向)增大，因為該等焊球113為球形。
於是，必須增加在該下基板114之上表面上所形成之上電極118的面積及在該上基板115之下表面上所形成之下電極138的面積，以符合該等焊球113之尺寸。基於此理由，對該下基板114之上表面及該上基板115之下表面所實施之佈線規則非常受限於該等焊球113，此成為對該系統級封裝單體100之高密度及小型化的阻礙之影響因素。
在一種用以使用該等焊球113以電性地及機械地連接該下封裝體111至該上封裝體112之方法下，必須在該下封裝體111與該上封裝體112間插入一底部填充樹脂，以便增加可靠性。然而，用以插入該底部填充樹脂之處理係麻煩的，此成為該系統級封裝單體100之成本增加的原因。
本發明之示範性具體例提供一種積層型封裝體，該積層型封裝體使能佈線之高密度及產品成本之減少而無關於一做為一上層之基板與一做為一下層之基板間的距離，以及提供一種用以製造該封裝體之方法。
本發明之特徵在於下面所述之手段。
一在第一觀點中所界定之發明係有關於一種堆疊型封裝體，包括：複數個封裝體，該複數個封裝體係彼此堆疊在上部且藉由一連接部之使用來電性連接在一起，每一封裝體具有一基板及一在該基板上所安裝之電子元件，其中該連接部具有一用以在該做為一下層之基板上支撐該做為一上層之基板的柱狀構件。
此外，在一由第二觀點所界定之發明中，該第一觀點所界定之積層型封裝體的進一步特徵在於：該柱狀構件係藉由焊料之使用結合至該基板。
在一由第三觀點所界定之發明中，該第一或第二觀點所界定之積層型封裝體的進一步特徵在於：該柱狀構件係一由銅所構成之插梢。
在一由第四觀點所界定之發明中，該第一或第二觀點所界定之積層型封裝體的進一步特徵在於：該柱狀構件係由一彈性可變形材料所構成。
在一由第五觀點所界定之發明中，該第一或第二觀點所界定之積層型封裝體的進一步特徵在於：該柱狀構件至少被插入該做為上層之基板或該做為下層之基板。
一在第六觀點中所界定之方法係有關於一種用以製造一積層型封裝體之方法，該積層型封裝體包括複數個封裝體，該複數個封裝體係彼此堆疊在上部且藉由一連接部之使用來電性連接在一起，每一封裝體具有一基板及一在該基板上所安裝之電子元件，該方法包括：一配置程序，用以放置一柱狀構件於至少該做為一下層之基板或該做為一上層之基板上；以及一連結程序，用以在該做為下層之基板上藉由該柱狀構件支撐該做為上層之基板的方式堆疊該等封裝體及用以連結該柱狀構件至該等基板。
依據本發明，藉由包括用以在一做為一下層之基板上支撐一做為一上層之基板的柱狀構件來建構以一電性連接方式使複數個封裝體彼此在上部堆疊之連接部，藉此可使該等相鄰連接部間之間距較小。結果，可試圖獲得佈線之高密度、改善一佈線規則之自由度及小型化一積層型封裝體。再者，避免需要在基板間提供一底部填充樹脂，以便可試圖減少零件之數目及成本。
從下面詳細描述、所附圖式及申請專利範圍可以明顯易知其它特徵及優點。
現在將參考圖式以描述用以實施本發明之最佳模式。
圖1顯示依據本發明之第一具體例的一積層型封裝體10A。該圖式所示之積層型封裝體10A包括一下封裝體11A、一上封裝體12A及連接部。
該下封裝體11A係由一下基板14A、焊球16、下電極17、上電極18、一半導體元件20等所構成。該下基板14A係一樹脂基板且係以在一基板主體之上下表面上形成一導電膜(例如：一銅膜)之方式來配置，其中該基板主體係以電鍍之類由一絕緣樹脂所構成。
以蝕刻等使該導電膜經歷一預定圖案化，藉以在該基板主體之上下表面上形成佈線。在該基板主體之下表面上所形成之下佈線(未顯示)的部分構成該等下電極17，以及在該基板主體之上表面上所形成之上佈線19的部分構成該等上電極18。該等下佈線及該等上佈線19係藉由介層(未顯示)電性連接在一起，以便垂直地穿過該基板主體。
並且，在該下基板14A之下表面上形成一下防焊層30，以及在該下基板14A之上表面上形成一上防焊層24。在該上防焊層24上之對應於該等上電極18之形成位置的位置上形成開口部，以及在該下防焊層30上之對應於該等下電極17之形成位置的位置上形成開口部。因此，經由該等開口部從該等防焊層24及30暴露該等電極17及18。
此外，在該下基板14A之下表面上形成做為該積層型封裝體10A之外部連接端的焊球16。在經由在該下防焊層30中所形成之開口部所暴露的個別下電極17上提供該等焊球16。
在本具體例中該半導體元件20係例如一邏輯IC及藉由覆晶接合被安裝至該下基板14A。特別地，在該半導體元件20上提供凸塊22，以及藉由覆晶接合使該等凸塊22接合至在該下基板14A之上表面上所形成之上佈線19，藉此在該下基板14A上安裝該半導體元件20。並且，在該半導體元件20與該下基板14A間插入一用以增加連接之可靠性的底部填充樹脂23。
同時，該上封裝體12A係由一上基板15A、半導體元件40及41、下電極37、上電極38、一密封樹脂49等所構成。該上基板15A係一樹脂基板，以及在一基板主體之上下表面上形成一導電膜(例如：一銅膜)，其中該基板主體係以電鍍之類由一絕緣樹脂所構成。
以蝕刻等使該導電膜經歷一預定圖案化，藉此在該基板主體之上下表面上形成佈線。在該基板主體之下表面上所形成之下佈線(未顯示)的部分構成該等下電極37，以及在該基板主體之上表面上所形成之上佈線(未顯示)的部分構成該等上電極38。該等下佈線及該等上佈線係藉由介層(未顯示)電性連接在一起，以便垂直地穿過該基板主體。
此外，在該上基板15A之下表面上形成一下防焊層60，以及在該上基板15A之上表面上形成一上防焊層44。在該上防焊層44上之對應於該等上電極38之形成位置的位置上形成開口部，以及在該下防焊層60上之對應於該等下電極37之形成位置的位置上形成開口部。因此，經由該等開口部從該等防焊層44及60暴露該等電極37及38。
該等半導體元件40及41係為例如記憶體IC及經由一間隔物48以一堆疊方式被安裝於該上基板15A上。該等半導體元件40及41係以金屬線45及46電性連接至在該上基板15A上所形成之上電極38。
該密封樹脂49係為一絕緣樹脂(例如：環氧樹脂之類)及係形成用以密封該等個別半導體元件40、41及該等金屬線45、46。該密封樹脂49係以例如轉注成形法(transfer molding)所形成。
本具體例之積層型封裝體10A係配置成藉由在該下封裝體11A上堆疊如上提及所配置之上封裝體12A以達成高密度及較小安裝面積。特別地，藉由該等連接部之使用以在該下封裝體11A上堆疊該上封裝體12A。
該等連接部展現一種在該下封裝體11A上支撐該上封裝體12A之功能及使該等封裝體11A及12A彼此電性連接。在本具體例之積層型封裝體10A中，該等連接部之特徵在於由柱狀構件13A及焊點部27及47所構成。以下將描述由該等柱狀構件13A及該等焊點部27及47所構成之連接部。
本具體例中所使用之半導體元件20在操作期間產生高溫。因此，在本具體例之積層型封裝體10A中，期望使該上封裝體12A與該下封裝體11A隔開，以便增加該半導體元件20之散熱。然而，將圖7所述之相關技藝系統級封裝單體100的配置應用至此封裝體時，增加用於堆疊目的之焊球113的尺寸，因而像先前所述造成阻礙高密度及小型化之問題。
然而，在本具體例中，本具體例之連接部係由該等柱狀構件13A及該等焊點部27及47所構成。該等柱狀構件13A係由銅所構成之插梢且具有一圓柱形狀，以及在該等柱狀構件之表面上形成一像鍍金之表面膜28。該等柱狀構件13A係由一比傳統上用於該等焊點部之焊料硬且展現較高剛性之材料所構成。因此，甚至當該等柱狀構件具有小直徑時，該等柱狀構件可提供一同等於用於堆疊目的之相關技藝焊球113所提供之功能的支撐功能(一種用以在該下封裝體11A上支撐該上封裝體12A之功能)。此外，關於電氣特性，銅在導電率方面優於焊料。因此，該等柱狀構件13A之使用以取代用於堆疊目的之焊球113能試圖提高在該下封裝體11A與該上封裝體12A間所達成之電氣特性。
該等柱狀構件13A之下端藉由焊料之使用以連接至在該下封裝體11A上所形成之上電極18(連結部稱為焊點部27)。此外，該等個別柱狀構件13A之上端藉由焊料之使用以連結至在該上封裝體12A上所形成之下電極37(連結部稱為焊點部47)。因此，以由該等柱狀構件13A及該等焊點部27及47所構成之連接部在該下封裝體11A上堆疊該上封裝體12A。
本具體例之積層型封裝體10A係以藉由該等柱狀構件13A之使用在該下封裝體11A上堆疊該上封裝體12A之方式來配置。可只根據能支撐該上封裝體12A之機械強度來決定該等柱狀構件13A之直徑(該柱狀構件之剖面的直徑)而不受在該下封裝體11A與該上封裝體12A間之間隔的影響。
因此，甚至當增加在該下封裝體11A與該上封裝體12A間之間隔時，相較於在該相關技藝中使用用於堆疊目的之焊球113做為該等連接部，可減少本具體例中所使用之柱狀構件13A的直徑。結果，可減少該等相鄰柱狀構件13A間之間距，以及可試圖減少該等上電極18之面積及該等下電極17之面積。因此，可試圖獲得佈線之高密度、改善該佈線規則之自由度及小型化該積層型封裝體10A。再者，避免需要在該下封裝體11A與該上封裝體12A間插入一底部填充樹脂，以及亦可試圖減少零件之數目及成本。
該等柱狀構件13A亦可以成為一彈性可變形結構或由一彈性可變形材料所構成。在該等柱狀構件成為一彈性可變形結構之情況中，當在該下封裝體11A或該上封裝體12A上強加外力或應力時，藉由該等柱狀構件13A之彈性變形吸收該外力或應力，藉以防止對另一封裝體之力或應力的傳送。結果，可藉由該結構之採用以具體化一抗外力及應力之高可靠積層型封裝體。例如：該彈性可變形材料之彈性模數為1000至2300億巴斯可。再者，可以使用一像鈹銅、磷青銅之類的彈簧材料做為該彈性可變形材料。
上述具體例已描述一使用一具有圓形剖面輪廓之柱狀構件做為該等柱狀構件13A之範例。然而，該等柱狀構件13A並非侷限於此一形狀，而可以採用像剖面矩形輪廓或三角形形狀的另一形狀。此外，可以藉由調整該等柱狀構件13A之剖面面積或長度以改變強度及彈性之程度。再者，該等柱狀構件13A之形狀不需要是一直線形狀。為了達成一像上述之彈性可變形結構，亦可以在該等柱狀構件13A之每一柱狀構件中形成一彎曲部。雖然該等柱狀構件13A可具有各種形狀，但是該圓形剖面輪廓係更合宜的，因為容易分散外力或應力及容易實施如圖5所示之對該下基板之插孔的插入。例如：該柱狀構件13A具有該圓形剖面輪廓，最好，該柱狀構件13A之直徑為100至200μm及該柱狀構件13A之長度為200至500μm。
雖然甚至在本具體例中使用焊料做為該等焊點部27及47，但是足夠量之焊點部27及47能固定該等柱狀構件13A至該等個別電極18及37。因此，甚至當使用焊料以接合該等柱狀構件13A至該等個別電極18及37時，不會產生在該相關技藝中所發生之高密度的變差及尺寸的增加。
接著，將描述一用以製造如上述所配置之積層型封裝體10A的方法。圖2係顯示用以製造該積層型封裝體10A之方法的製造程序之圖式。在圖2中，相同於圖1所示之結構係指定有相同元件符號，因而省略其說明。
在該積層型封裝體10A之製造時，如圖2A所示，先準備已經由個別程序所製造之下封裝體11A及上封裝體12A。
隨後，如圖2B所示，在該下基板14A之上電極18上提供將做為該等焊點部27之焊膏27a，以及在該下基板15A之下電極37上提供將做為該等焊點部47之焊膏47a。在該焊膏27a或47a上配置該等柱狀構件13A(一配置程序)。在圖2B所示之範例中，在該上基板15A上所提供之焊膏47a上配置該等柱狀構件13A。
在該配置程序之完成後，接下來將該上封裝體12A安裝在該下封裝體11A上。在此時，在該上基板15A上配置該等柱狀構件13A，以便插入在該下基板14A上所提供之焊膏27a。因此，經由該等柱狀構件13A及該等焊膏27a及47a將該上封裝體12A暫時配置在該下封裝體11A上。
該等焊膏27a、47a係處於膏狀物之形式且具有軟特性。因此，當該上封裝體12A較重時，可能會有該上封裝體12A在該下封裝體11A上變得不穩定之情況。在此情況中，亦可以採用一種結構，其中藉由使用一治具(jig)以在該下封裝體11A上支撐該上封裝體12A，直到在稍後所述之迴焊處理後為止。
當如以上所述在該下封裝體11A上暫時安裝該上封裝體12A時，將該下封裝體11A及該上封裝體12A放入一迴焊爐，在此情況中使該等封裝體經歷迴焊處理。因此，該等焊膏27a及47a中所含之焊料熔化，以及去除揮發成分。該等柱狀構件13A藉由該等焊點部47接合至該等下電極37，以及藉由該等焊點部27接合至該等上電極18(一連結程序)。
如以上所述，依據本具體例之製造方法，可有效地且容易地製造該積層型封裝體10A。雖然在該連結程序之完成後使該等下電極17經歷該等焊球16之形成的程序，但是使用一已知方法來實施此程序，以及因而省略其說明。
隨後，將描述本發明之另一具體例。圖3及4係描述依據本發明之第二具體例的一積層型封裝體10B及一用以製造該封裝體之方法的圖式。圖5及6係描述依據本發明之第三具體例的一積層型封裝體10C及一用以製造該封裝體之方法的圖式。在圖3至6中，對應於圖1及2所示之結構的結構係指定有相同元件符號，因而省略它們的說明。
圖3所示之第二具體例的積層型封裝體10B之特徵在於：在一下封裝體11B上堆疊複數個半導體元件20及21(在本具體例中為兩個半導體元件)。
該下封裝體11B係以下列方式來建構：經由一間隔物31在一下基板14B之上表面上堆疊該半導體元件20及該半導體元件21。再者，該等個別半導體元件20、21藉由金屬線25及26電性連接至該下電極14B。
形成一密封樹脂50，以便密封該等個別半導體元件20及21以及該等金屬線25及26。形成該密封樹脂50的範圍係受限於形成該等個別半導體元件20及21以及該等金屬線25及26的面積。形成欲提供有柱狀構件13B之上電極18係經由該防焊層暴露出來。
同時，在本具體例中，以提供唯一半導體元件40之方式建構一上基板15B。該半導體元件40藉由覆晶接合以凸塊42之使用來接合至上電極38。
附帶地，像在本具體例中，可以是下面之情況：在該積層型封裝體10B中，在該做為一下層之下封裝體11B上必須堆疊該複數個半導體元件20及21。在該結構中，在該做為一下層之下基板14B上堆疊該複數個半導體元件20及21。因此，該下封裝體11B之總高度變高。特別地，在藉由該等金屬線25及26使該等半導體元件20及21與該下基板14B連接在一起之結構的情況中，像是在本具體例之情況中，形成該密封樹脂50，以便密封該等金屬線25及26，以及因而該下封裝體11B之高度變得較大(此將在下面稱為"較高輪廓現象")。
在該下封裝體11B之輪廓增大之結構中，當在該下封裝體11B上堆疊該上封裝體12B時，在該下基板14B與該上基板15B間之距離必然變得較大。因此，在該相關技藝中已將一具有增大輪廓之封裝體當做一上封裝體及將一具有保持小輪廓之封裝體當做一下封裝體。
然而，當如上所述限制該等封裝體之型態時，阻礙一積層型封裝體(一系統級封裝單體)之電路結構的自由度，此造成很難獲得期望電氣特性之問題。此外，當將具有增大輪廓以達成一期望電氣特性之封裝體當做一下封裝體時，該積層型封裝體將變得龐大。
相較下，在本具體例中，使用該等柱狀構件13B及該等焊點部27及47做為連接部。因此，可將一較高輪廓封裝體當做該下封裝體11B，以及可試圖小型化該積層型封裝體10B，同時獲得期望電氣特性。
圖4顯示一用以製造上述積層型封裝體10B之方法。如所述，可藉由實質上相同於用以製造圖2所述之積層型封裝體10A的方法之程序來製造本具體例之積層型封裝體10B。結果，甚至當增大該下封裝體11B之輪廓時，可有效地且容易地製造該積層型封裝體10B。
圖5顯示第三具體例之積層型封裝體10C。該積層型封裝體10C之特徵在於：將構成該等連接部之個別柱狀構件13C的至少上或下端插入在一上或下基板中所形成之插孔。
在本具體例中，該等柱狀構件13C之上端藉由焊點部47之使用來接合至一上封裝體12C(一上基板15C)之下電極37，以及將該等柱狀構件13C之下端插入在一下封裝體11C(一下基板14C)中所形成之插孔29。
在該下基板14C之個別插孔29中形成電極55，以及將該等柱狀構件13C插入等個別插孔29，因而變成電性連接至該等電極55。該等電極55亦可以由通孔或介層所形成，或者亦可以分別提供接觸零件。
藉由本具體例之結構，保持該等柱狀構件13C，同時將它們的部分插入在該下基板14C中所形成之個別插孔29。因此，可牢固地固定該等柱狀構件13C。因此，可藉由該等柱狀構件13C在該下封裝體11C上可靠地支撐該上封裝體12C，以及可進一步增加該積層型封裝體10C之可靠性。
本具體例顯示只在該下封裝體11C中形成插有該等柱狀構件13C之插孔29的結構。然而，可以在該上封裝體12C中形成插有該等柱狀構件13C之插孔或者可以在該等個別封裝體11C及12C中形成該等插孔。再者，為了在該等柱狀構件13C與該等電極55間具有更可靠電氣及機械連接，亦可以採用下面結構：使該等柱狀構件13C及該等電極55焊接至該基板之表面。
然後，將描述一用以製造上述配置之積層型封裝體10C的方法。
首先，如圖6A所示，準備以不同程序所分別製造之下封裝體11C及上封裝體12C，以便製造該積層型封裝體10C。在此時，在該下封裝體11C上之要提供該等柱狀構件13C的位置中形成具有電極55之插孔29。
隨後，在該上基板15C之下電極37上提供做為該等焊點部47之焊膏47a，以及在該焊膏47a上提供(暫時提供)該等柱狀構件13C。在本具體例中，在如上所述在該焊膏47a上暫時提供該等柱狀構件13C後，將該上封裝體12C放入該迴焊爐，在該迴焊爐使該封裝體經歷迴焊處理。結果，熔化該焊膏47a中所含之焊料，以及去除該焊膏之揮發成分，藉此該等柱狀構件13C藉由該等焊點部47接合至該等下電極37。
當如上所述該等柱狀構件13C接合至該上基板15C(該等下電極37)時，如圖6B所示以該等柱狀構件13C面對該等個別插孔29之方式在該下封裝體11C上放置該上封裝體12C。
隨後，如圖6C所示，在該下封裝體11C上安裝該上封裝體12C。在此時，使在上基板15C上所提供之柱狀構件13C附著，以便插入在該下基板14C中所形成之個別插孔29。因此，在該下封裝體11C上堆疊該上封裝體12C。在堆疊操作之完成後，使該等下電極17經歷該等焊球16之製造的程序。
如以上所述，依據本具體例之製造方法，該等柱狀構件13C插入該等個別插孔29的結果是可有效地且簡單地製造可試圖達成較高可靠性之積層型封裝體10C。
雖然上述具體例已描述使用該等插梢之柱狀構件13A至13C做為連接部之範例，但是該等柱狀構件通常不是插梢。例如：接合線藉由一打線接合設備連接至下電極，以及在已向上供給後切割該等金屬線，藉以從該等金屬線形成該等柱狀構件。
雖然已描述關於有限數目之具體例的本發明，但是受益於本揭露之熟習該項技藝者將察覺到可想出不脫離在此所揭露之本發明的範圍之其它具體例。於是，應該只由所附申請專利範圍來限制本發明之範圍。
10A．．．積層型封裝體
10B．．．積層型封裝體
10C．．．積層型封裝體
11A．．．下封裝體
11B．．．下封裝體
11C．．．下封裝體
12A．．．上封裝體
12B．．．上封裝體
12C．．．上封裝體
13A．．．柱狀構件
13B．．．柱狀構件
13C．．．柱狀構件
14A．．．下基板
14B．．．下基板
14C．．．下基板
15A．．．上基板
15B．．．上基板
15C．．．上基板
16．．．焊球
17．．．下電極
18．．．上電極
19．．．上佈線
20．．．半導體元件
21．．．半導體元件
22．．．凸塊
23．．．底部填充樹脂
24．．．上防焊層
25．．．金屬線
26．．．金屬線
27．．．焊點部
27a．．．焊膏
28．．．表面膜
29．．．插孔
30．．．下防焊層
31．．．間隔物
37．．．下電極
38．．．上電極
40．．．半導體元件
41．．．半導體元件
42．．．凸塊
44．．．上防焊層
45．．．金屬線
46．．．金屬線
47．．．焊點部
47a．．．焊膏
48．．．間隔物
49．．．密封樹脂
50．．．密封樹脂
55．．．電極
60．．．下防焊層
100．．．系統級封裝單體
111．．．下封裝體
112．．．上封裝體
113．．．焊球
114．．．下基板
115．．．上基板
116．．．焊球
118．．．上電極
120．．．半導體元件
138．．．下電極
140．．．半導體元件
141．．．半導體元件
圖1係顯示依據本發明之第一具體例的一半導體裝置之剖面圖；圖2A至2C係描述一用以製造第一具體例之半導體裝置的方法之圖式；圖3係顯示依據本發明之第二具體例的一半導體裝置之剖面圖；圖4A至4C係描述一用以製造第二具體例之半導體裝置的方法之圖式；圖5係顯示依據本發明之第三具體例的一半導體裝置之剖面圖；圖6A至6C係描述一用以製造第三具體例之半導體裝置的方法之圖式；以及圖7係依據該相關技藝之一範例的一系統級封裝單體的剖面圖。
10A．．．積層型封裝體
11A．．．下封裝體
12A．．．上封裝體
13A．．．柱狀構件
14A．．．下基板
15A．．．上基板
16．．．焊球
17．．．下電極
18．．．上電極
19．．．上佈線
20．．．半導體元件
22．．．凸塊
23．．．底部填充樹脂
24．．．上防焊層
27．．．焊點部
28．．．表面膜
30．．．下防焊層
37．．．下電極
38．．．上電極
40．．．半導體元件
41．．．半導體元件
44．．．上防焊層
45．．．金屬線
46．．．金屬線
47．．．焊點部
48．．．間隔物
49．．．密封樹脂
60．．．下防焊層

Claims (5)

  1. 一種積層型封裝體，其將於基板上搭載有電子元件之複數個封裝體，藉由連接部一方面加以電氣連接，一方面加以積層而形成；其特徵為，上述積層型封裝體具備有：上封裝體，其於上基板之兩面形成有防焊層，且自上述防焊層之開口部以暴露之方式設置有電極，並於上述上基板之一側的面，安裝有半導體元件，上述半導體元件係與於上述上基板之同一面所形成之電極電氣連接，並且在於上述上基板之另一側的面所形成之電極上，設置有焊點部；及下封裝體，其於下基板之兩面形成有防焊層，且自上述防焊層之開口部以暴露之方式設置有電極，並於上述下基板之一側的面，安裝有半導體元件，上述半導體元件係與於上述下基板之同一面所形成之電極電氣連接，上述下基板係具有於厚度方向以穿過下基板之方式而形成之插孔，於上述插孔形成有電極，於上述下基板之另一側的面之電極、及上述插孔，形成有焊球；而上述上封裝體與上述下封裝體，係藉由柱狀構件而加以積層， 上述柱狀構件之上端，係與上述焊點部產生連接，而下端，係與於上述插孔所形成之上述電極電氣連接，上述柱狀構件與上述電極，係以直接接觸之方式加以連接。
  2. 如申請專利範圍第1項之積層型封裝體，其中，該柱狀構件係一由銅所構成之插梢，於其表面施加有鍍金之表面膜。
  3. 如申請專利範圍第1或2項之積層型封裝體，其中，該柱狀構件係由一彈性可變形材料所構成。
  4. 如申請專利範圍第1至3項中任一項之積層型封裝體，其中，在上述柱狀構件與於上述插孔所形成之上述電極間之連接，於上述下基板之一側的面之表面，設置有焊料。
  5. 一種積層型封裝體之製造方法，其將於基板上搭載有電子元件之複數個封裝體，藉由連接部一方面加以電氣連接，一方面加以積層；其特徵為，具備有：形成上封裝體之步驟，其於上基板之兩面形成有防焊層，且自上述防焊層之開口部以暴露之方式設置有電極，並於上述上基板之一側的面，安裝有半導體元件，上述半導體元件係與於上述上基板之同一面所形成之電極電氣連接；形成下封裝體之步驟，其於下基板之兩面形成有防焊層，且自上述防焊層之開口部以暴露之方式設置有電極， 並於上述下基板之一側的面，安裝有半導體元件，上述半導體元件係與於上述下基板之同一面所形成之電極電氣連接，上述下基板係具有於厚度方向以穿過下基板之方式而形成之插孔，於上述插孔形成有電極；配設步驟，其將柱狀構件配設於上述上基板之另一側的面之焊點部；連結步驟，其藉由將上述柱狀構件插入至上述下封裝體之插孔，並以於上述下封裝體上支撐上述上封裝體之方式加以積層，而將該柱狀構件與上述下封裝體加以連結；及形成焊球之步驟，其形成於上述下基板之另一側的面之電極、及上述插孔。
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