JP2008270446A - 積層型半導体装置とその製造方法 - Google Patents
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- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/73201—Location after the connecting process on the same surface
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Abstract
【解決手段】積層型半導体装置1は、配線基板2上に並列して搭載された複数の半導体素子6を有する下段側半導体素子群を具備する。下段側半導体素子群上には複数の半導体素子6にまたがって上段側半導体素子10が積層されている。下段側半導体素子6と上段側半導体素子10とはフリップチップ接続されている。上段側半導体素子10は半田のセルフアライメント効果に基づいて位置決め用基板上に位置決めされた複数の下段側半導体素子6に対してフリップチップ接続される。
【選択図】図1
Description
Claims (5)
- 素子搭載部を有する配線基板と、
前記配線基板の前記素子搭載部に並列して搭載された複数の半導体素子を有する下段側半導体素子群と、
前記下段側半導体素子群上に前記複数の半導体素子にまたがって積層され、かつ前記下段側半導体素子群の前記複数の半導体素子より大形状を有すると共に、前記複数の半導体素子に対してフリップチップ接続された上段側半導体素子と
を具備することを特徴とする積層型半導体装置。 - 請求項1記載の積層型半導体装置の製造方法であって、
位置決め用基板に第1の半田パッドを形成する工程と、
前記下段側半導体素子群を構成する前記複数の半導体素子の前記上段側半導体素子が積層される面とは反対側の面に、それぞれ前記第1の半田パッドと同一パターンを有する第2の半田パッドを形成する工程と、
前記第1の半田パッドと前記第2の半田パッドとが対向するように、前記位置決め用基板上に前記複数の半導体素子を配置する工程と、
前記第1および第2の半田パッドに熱処理を施して、前記半田パッドのセルフアライメント効果に基づいて、前記複数の半導体素子を位置決めする工程と、
前記位置決め用基板上で、前記下段側半導体素子群上に前記複数の半導体素子にまたがって前記上段側半導体素子を積層し、前記複数の半導体素子と前記上段側半導体素子とをフリップチップ接続する工程と、
前記下段側半導体素子群と前記上段側半導体素子との接続体を、前記位置決め用基板から取り外す工程と、
前記位置決め用基板から取り外した前記接続体を、前記配線基板の前記素子搭載部に搭載する工程と
を具備することを特徴とする積層型半導体装置の製造方法。 - 請求項2記載の積層型半導体装置の製造方法において、
前記第2の半田パッドは前記第1の半田パッドと同一形状を有することを特徴とする積層型半導体装置の製造方法。 - 請求項2または請求項3記載の積層型半導体装置の製造方法において、
前記第1および第2の半田パッドは前記上段側半導体素子をフリップチップ接続するためのバンプ電極より低い融点を有し、かつ前記第1および第2の半田パッドと前記バンプ電極との融点の差に基づいて、前記接続体を前記位置決め用基板から取り外すことを特徴とする積層型半導体装置の製造方法。 - 請求項2または請求項3記載の積層型半導体装置の製造方法において、
前記複数の半導体素子に前記上段側半導体素子をフリップチップ接続した後に、前記複数の半導体素子と前記上段側半導体素子との間に樹脂を充填して固化させる工程と、
前記樹脂を固化させた後に、前記位置決め用基板に前記第1および第2の半田パッドを介して接続された前記複数の半導体素子に熱処理を施して、前記接続体を前記位置決め用基板から取り外す工程と
を具備することを特徴とする積層型半導体装置の製造方法。
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JP2008270446A true JP2008270446A (ja) | 2008-11-06 |
JP4417974B2 JP4417974B2 (ja) | 2010-02-17 |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011044654A (ja) * | 2009-08-24 | 2011-03-03 | Shinko Electric Ind Co Ltd | 半導体装置 |
WO2014122882A1 (ja) * | 2013-02-05 | 2014-08-14 | パナソニック株式会社 | 半導体装置 |
JP2015201735A (ja) * | 2014-04-07 | 2015-11-12 | キヤノン株式会社 | 集積回路装置および画像処理装置 |
JP7527358B2 (ja) | 2019-10-04 | 2024-08-02 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 相互接続ブリッジの組立てのための位置合わせキャリア |
-
2007
- 2007-04-19 JP JP2007110080A patent/JP4417974B2/ja not_active Expired - Fee Related
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011044654A (ja) * | 2009-08-24 | 2011-03-03 | Shinko Electric Ind Co Ltd | 半導体装置 |
WO2014122882A1 (ja) * | 2013-02-05 | 2014-08-14 | パナソニック株式会社 | 半導体装置 |
US9318470B2 (en) | 2013-02-05 | 2016-04-19 | Socionext Inc. | Semiconductor device |
JP2015201735A (ja) * | 2014-04-07 | 2015-11-12 | キヤノン株式会社 | 集積回路装置および画像処理装置 |
JP7527358B2 (ja) | 2019-10-04 | 2024-08-02 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 相互接続ブリッジの組立てのための位置合わせキャリア |
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