TWI497658B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

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TWI497658B
TWI497658B TW098144929A TW98144929A TWI497658B TW I497658 B TWI497658 B TW I497658B TW 098144929 A TW098144929 A TW 098144929A TW 98144929 A TW98144929 A TW 98144929A TW I497658 B TWI497658 B TW I497658B
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layer
chip package
semiconductor substrate
redistribution
redistribution circuit
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TW201113992A (en
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Chien Hung Liu
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Xintec Inc
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Description

晶片封裝體及其製造方法
本發明係有關於一種晶片封裝體，特別有關於一種具有導通孔以及重佈線路層的晶片封裝體及其製造方法。
傳統的晶片封裝技術係將晶片黏著於印刷電路板上，然後再利用打線接合的方式，電性連接晶片與印刷電路板，最後利用封膠材料覆蓋打線接合處，以形成晶片封裝體。
然而由於傳統的晶片封裝體在打線接合處會形成封膠材料之凸塊，使得傳統的晶片封裝體之表面為凹凸面，當其應用於指紋辨識器時，晶片封裝體的凹凸面會降低指紋辨識率。
因此，業界亟需一種晶片封裝體，其可以使得晶片封裝體具有平坦的表面。
一種晶片封裝體，包括：一半導體基底，具有一第一表面和相對的一第二表面，其中半導體基底包含一半導體元件和一導電墊，設置於第一表面上。一導通孔，自半導體基底的第二表面向內延伸並連通至導電墊。一重佈線路層，位於半導體基底第二表面之下，並與導通孔內之導電墊電性連接，且該重佈線路層之邊緣外露於 該半導體基底側壁。一導線層，位於重佈線路層之下，且延伸至半導體基底側壁而與重佈線路層構成一電性接觸。
此外，本發明還提供一種晶片封裝體的製造方法，包括：提供一半導體晶圓，具有一第一表面和相對的一第二表面，其中該半導體晶圓包含複數個半導體元件和複數個導電墊，設置於該第一表面上；自該半導體晶圓的第二表面形成複數個導通孔，其向內延伸並連通至該些導電墊；自該半導體基底第二表面之下形成一重佈線路層，其與該些導通孔內之導電墊電性連接，且該重佈線路層之邊緣外露於該半導體基底側壁；及自該重佈線路層之下形成一導線層，其延伸至該半導體基底側壁而與該重佈線路層構成一電性接觸。
為了讓本發明之上述目的、特徵、及優點能更明顯易懂，以下配合所附圖式，作詳細說明如下：
以下以實施例並配合圖式詳細說明本發明，在圖式或說明書描述中，相似或相同之部分係使用相同之圖號。且在圖式中，實施例之形狀或是厚度可擴大，以簡化或是方便標示。再者，圖式中各元件之部分將以描述說明之，值得注意的是，圖中未繪示或描述之元件，為所屬技術領域中具有通常知識者所知的形式。另外，特定之實施例僅為揭示本發明使用之特定方式，其並非用以限定本發明。
本發明係以一製作感測元件封裝體(sensor package)的實施例作為說明，特別是應用在指紋辨識器之晶片封裝體。然而，可以了解的是，在本發明之晶片封裝體的實施例中，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System；MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測元件、發光二極體(light-emitting diodes；LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶片進行封裝。
其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝 體。
本發明之實施例提供一種晶片封裝體及其製造方法，利用導通孔(through hole)以及形成T型接觸(T-contact)之製程技術，使得晶片封裝體具有平坦的感測表面。
請參閱第1A至1J圖，其係顯示依據本發明之一實施例，形成晶片封裝體之製造方法的剖面示意圖。如第1A圖所示，首先提供一半導體基板100，一般為半導體晶圓(如矽晶圓)或矽基板。其次，半導體基板定義有多個元件區100A，圍繞元件區100A者為周邊接墊區100B。元件區100A及周邊接墊區100B共同形成部分的晶粒區。
接續，於元件區100A製作半導體元件102，例如指紋辨識器、影像感測器元件或是其他微機電結構，而覆蓋上述半導體基板100及半導體元件102者為層間介電層103(IMD)，一般可選擇低介電係數(low k)的絕緣材料，例如多孔性氧化層。接著於周邊接墊區100B的層間介電層103中製作複數個導電墊結構104。在此實施例中，所形成之導電墊結構包括多層金屬層，較佳可以由銅(copper；Cu)、鋁(aluminum；Al)或其它合適的金屬材料所製成。
此外，半導體基板100可覆蓋有一晶片保護層106(passivation layer)，同時為將晶片內的元件電性連接至外部電路，可事先定義晶片保護層106以形成複數個暴露出導電墊結構的開口106h。
接著，請參閱第1B圖，提供載體層110，例如為半 導體基底或玻璃基底，半導體基底可以是另一空白矽晶圓，藉由黏著層(adhesive layer)108將載體層110與半導體晶圓100的第一表面100a接合，黏著層108可以是含有環氧樹脂的黏著劑，其中為方便說明起見，上述半導體基板100係僅揭示半導體元件102和導電墊結構104。然後，藉由例如是化學機械研磨(chemical mechanical polishing；CMP)法或蝕刻(etching)、銑削(milling)、磨削(grinding)或研磨(polishing)的方式，將半導體晶圓100薄化，在一實施例中，薄化後的半導體晶圓100’之厚度約為30至50μm。
請參閱第1C圖，以微影及蝕刻製程在半導體晶圓100’的第二表面100b上形成多個導通孔112，暴露出該些導電墊104，接著在半導體晶圓100’之第二表面100b上以塗佈的方式形成絕緣層114，且延伸至該些導通孔112的側壁上，絕緣層114的材料可以是氧化層或是感光絕緣材料，例如含有環氧樹脂(epoxy)的光阻材料，其中位於導通孔112底部的絕緣層114可利用顯影方式去除。在一實施例中，絕緣層114的厚度可介於約5至15μm之間，較佳為10μm。
接著，進行重佈線路層的製作。請參閱第1D圖，在絕緣層114上順應性地形成導電層116，且延伸至導通孔112的側壁及底部上，與導電墊104接觸，產生電性連接。由於導電層116可重新佈局傳遞訊號的傳導線路，因此導電層116也可以稱為重佈線路層。可藉由例如是濺鍍(sputtering)、蒸鍍(evaporating)或電鍍(electroplating)的方 式，沈積例如是銅、鋁或鎳(nickel；Ni)的導電材料層(未繪示)於絕緣層114上以及導通孔112內，再藉由微影及蝕刻製程圖案化導電材料層，以形成上述導電層116。
請參閱第1E圖，在半導體晶圓100’的第二表面100b上形成絕緣層118，覆蓋導電層116和絕緣層114，絕緣層118的材料可以是氧化層或是感光絕緣材料，例如含有環氧樹脂(epoxy)的光阻材料，在一實施例中，絕緣層118的厚度可介於約20至30μm之間，較佳為25μm。此外，在一實施例中，絕緣層118的材料可以與絕緣層114相同。
接著，以曝光顯影方式在絕緣層118中形成開口120，暴露出導電層116的一部份，然後在絕緣層118上順應性地形成重佈線路層122，且延伸至開口120的側壁及底部上，與導電層116接觸，以產生電性連接。可藉由例如是濺鍍(sputtering)、蒸鍍(evaporating)或電鍍(electroplating)的方式，沈積例如是銅、鋁或鎳(nickel；Ni)的導電材料層(未繪示)於絕緣層118上以及開口120內，再藉由微影及蝕刻製程圖案化導電材料層，以形成上述重佈線路層122。其中值得注意的是，由於後續製程會於晶粒區外緣形成一溝槽凹口130，因此重佈線路層116係內縮而與溝槽凹口相隔一間距，而重佈線路層122則至少延伸至溝槽凹口之預定區域內或晶粒區的外緣，以便與後續的重佈線路層132形成接觸。
請參閱第1F圖，提供一封裝層126，封裝層126例如為半導體基底或玻璃基底，藉由黏著層124，例如為含 有環氧樹脂的黏著劑，將封裝層126接合於重佈線路層122以及絕緣層118上，封裝層126可以支撐薄化後的半導體晶圓100’，強化晶片封裝體的機械強度。接著，在封裝層126上形成絕緣層128，例如為環氧樹脂(epoxy)或阻焊膜(solder mask)之材料，其可以作為應力釋放層(stress release layer)。
請參閱第1G圖，對半導體晶圓100’之第二表面100b上的絕緣層128、封裝層126、黏著層124、重佈線路層122以及絕緣層118進行刻痕(notching)步驟，形成溝槽凹口(channel of notch)130，溝槽凹口130由絕緣層128延伸至絕緣層118，但並未貫穿絕緣層118，並且重佈線路層122的邊緣經由溝槽凹口130暴露出來，其中，絕緣層118係作為緩衝，以避免切割刀切至矽基底100’。
接著，請參閱第1H圖，在絕緣層128上形成導線層132，且延伸至溝槽凹口130的側壁及底部上，與重佈線路層122構成電性接觸，例如形成一T型接觸T。可藉由例如是濺鍍(sputtering)、蒸鍍(evaporating)或電鍍(electroplating)的方式，沈積例如是銅、鋁或鎳(nickel；Ni)的導電材料層(未繪示)於絕緣層128上以及溝槽130內，再藉由微影及蝕刻製程圖案化導電材料層，以形成上述導線層132。然後，在絕緣層128以及導線層132上塗佈一例如是阻焊膜(solder mask)的保護層134，覆蓋導線層132，接著，圖案化保護層134，形成開口136，以暴露部份的導線層132。接著，在保護層134的開口136內塗佈焊料，且進行回焊(reflow)步驟，以形成導電凸塊138， 導電凸塊138可以是球狀柵格陣列(ball grid array；BGA)或平面柵格陣列(land grid array；LGA)。
請參閱第1I圖，在一實施例中，此載體層110可予以除去，例如藉由化學機械研磨(chemical mechanical polishing；CMP)法或蝕刻(etching)、銑削(milling)、磨削(grinding)或研磨(polishing)的方式將暫時的載體層110除去，或者也可以利用剝離的方式移除暫時的載體層110。然後在一選擇性的步驟中，於黏著層108上形成保護層140，其可以是阻焊膜(solder mask)的材料，硬度高(約大於7)，因此具有防刮及耐磨之功效。
然後沿著切割線SL將半導體晶圓100’分割，即可形成複數個晶片封裝體200，如第1J圖所示。
請參閱第1J圖，其係顯示依據本發明一實施例之晶片封裝體的剖面示意圖，沿著切割線SL分離晶圓成晶片封裝體200。半導體基底100’例如由包含晶粒區之薄化後半導體晶圓分割而來，晶粒區中，半導體基底100’之元件區100A上具有半導體元件102，以及位於周邊接墊區100B之複數個導電墊(conductive pad)104係圍繞著元件區100A。導電墊104例如為接合墊(bonding pad)，可透過金屬連線(未顯示)連接至半導體元件102。
在一實施例中，晶片封裝體200可應用於指紋辨識器，或感測元件，例如互補式金氧半導體元件(CMOS)或電荷耦合元件(charge-couple device；CCD)，此外如微機電元件等亦不在此限。
在一實施例中，上述重佈線路層116、122以及導線 層132可藉由例如是濺鍍(sputtering)、蒸鍍(evaporating)或電鍍(electroplating)的方式，沈積例如是銅、鋁或鎳(nickel；Ni)的導電材料層(未繪示)，再藉由微影及蝕刻製程圖案化導電材料層而形成，並且電性連接至導電墊104。
依據本發明之實施例，可在晶片封裝體內利用導通孔112、重佈線路層116、122，以及與其中之重佈線路層122之邊緣構成電性接觸的導線層132，達到與晶片之導電墊104產生電性連接之目的，並形成具有平坦封裝表面的晶片封裝體。當本發明實施例之晶片封裝體應用於指紋辨識器時，可提升指紋辨識率。
值得注意的是，重佈線路層以及絕緣層可增加形成T型接觸所需的絕緣層厚度，避免構成T型接觸的導線層132過於接近半導體基底100’。
另外，本發明實施例之晶片封裝體中的導通孔係形成於減薄後的晶圓內，由於導通孔的深度可降低，導通孔的直徑也可以隨之縮小，因此可應用於導電墊之間距(pitch)較小的晶片上，在一實施例中，晶片之導電墊的間距可小於100μm。
此外，本發明實施例之晶片封裝體中的封裝層126可支撐減薄後的半導體基底100’，增加晶片封裝體200的機械強度，而設置於封裝層126上的絕緣層128則可以作為應力釋放層，當晶片封裝體受到外力衝擊時，可避免晶片封裝體被損壞。另外，設置於晶片封裝體外圍的保護層140則可以提供防刮及耐磨之功效，避免晶片 封裝體受到損害。
雖然本發明已揭露較佳實施例如上，然其並非用以限定本發明，任何熟悉此項技藝者，在不脫離本發明之精神和範圍內，當可做些許更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定為準。
100‧‧‧半導體基底
100’‧‧‧薄化的半導體基底
100a‧‧‧半導體基底的第一表面
100b‧‧‧半導體基底的第二表面
102‧‧‧晶片
104‧‧‧導電墊
108、124‧‧‧黏著層
110‧‧‧暫時的載體層
112‧‧‧導通孔
114、118、128‧‧‧絕緣層
120、136‧‧‧開口
116、122‧‧‧重佈線路層
126‧‧‧封裝層
130‧‧‧溝槽凹口
132‧‧‧導線層
134、140‧‧‧保護層
138‧‧‧導電凸塊
T‧‧‧T型接觸
SL‧‧‧切割線
200‧‧‧晶片封裝體
第1A-1J圖係顯示依據本發明之一實施例，形成晶片封裝體之製造方法的剖面示意圖。
100’‧‧‧半導體基底
102‧‧‧晶片
104‧‧‧導電墊
108、124‧‧‧黏著層
112‧‧‧導通孔
114、118、128‧‧‧絕緣層
116、122‧‧‧重佈線路層
126‧‧‧封裝層
132‧‧‧導線層
134、140‧‧‧保護層
138‧‧‧導電凸塊
T‧‧‧T型接觸
200‧‧‧晶片封裝體

Claims (23)

  1. 一種晶片封裝體，包括：一半導體基底，具有一第一表面和相對的一第二表面，包含一半導體元件和一導電墊，設置於該第一表面上；一導通孔，自該半導體基底的第二表面向內延伸並連通至該導電墊；一重佈線路層，位於該半導體基底第二表面之下，並與該導通孔內之導電墊電性連接，且該重佈線路層之邊緣外露於該半導體基底側壁；一第一絕緣層，設置於該半導體基底的該第二表面下方且具有一開口，其中該重佈線路層順應性地形成在該第一絕緣層的下方及該開口內；以及一導線層，位於該重佈線路層之下，且延伸至該半導體基底側壁而與該重佈線路層構成電性接觸。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中，該重佈線路層為一堆疊層，包括：一第一重佈線路層，位於該導通孔內以電性連接該導電墊，且延伸至該半導體基底第二表面之下；及一第二重佈線路層，位於該第一重佈線路層之下並與該第一重佈線路層電性連接。
  3. 如申請專利範圍第2項所述之晶片封裝體，更包括：一第二絕緣層，設置於該半導體基底與該第一重佈線路層之間，且該第一絕緣層設置於該第一重佈線路層與該第二重佈線路層之間。
  4. 如申請專利範圍第3項所述之晶片封裝體，其中該第一絕緣層內的該開口暴露出該第一重佈線路層，該第二重佈線路層形成於該開口中，與該第一重佈線路層電性連接，且延伸至該第一絕緣層上。
  5. 如申請專利範圍第3項所述之晶片封裝體，其中該第一絕緣層的材料包括一感光絕緣材料。
  6. 如申請專利範圍第3項所述之晶片封裝體，其中該半導體基底側壁具有一溝槽凹口，該溝槽凹口底部延伸至該第一絕緣層上。
  7. 如申請專利範圍第6項所述之晶片封裝體，其中該導線層經由該溝槽凹口側壁延伸至該第一絕緣層上。
  8. 如申請專利範圍第7項所述之晶片封裝體，其中該第一重佈線路層與該溝槽凹口相隔一間距，該第二重佈線路層延伸至該溝槽凹口邊緣而與該導線層電性連接。
  9. 如申請專利範圍第1項所述之晶片封裝體，更包括一封裝層，位於該半導體基底第二表面之下，且介於該重佈線路層與該導線層之間。
  10. 如申請專利範圍第9項所述之晶片封裝體，其中該封裝層包括一半導體基底或一玻璃基底。
  11. 如申請專利範圍第9項所述之晶片封裝體，更包括：一黏著層，位於該重佈線路層與該封裝層之間；及一第三絕緣層，位於該封裝層與該導線層之間。
  12. 如申請專利範圍第11項所述之晶片封裝體，其中該第三絕緣層包括一應力釋放層。
  13. 如申請專利範圍第1項所述之晶片封裝體，更包括：一第一保護層，覆蓋該導線層，並具有一開口以暴露出該導線層；及一導電凸塊，設置於該第一保護層的開口中，以與該導線層電性連接。
  14. 如申請專利範圍第13項所述之晶片封裝體，其中該導電凸塊包括球狀柵格陣列(BGA)或平面柵格陣列(LGA)。
  15. 如申請專利範圍第1項所述之晶片封裝體，更包括：一第二保護層，覆蓋該半導體基底之第一表面；及一黏著層，位於該半導體基底與該第二保護層之間。
  16. 如申請專利範圍第15項所述之晶片封裝體，其中該第二保護層具有一平坦表面，且該第二保護層的材料包括一硬度7以上之耐磨材料。
  17. 一種晶片封裝體的製造方法，包括：提供一半導體晶圓，具有一第一表面和相對的一第二表面，其中該半導體晶圓包含複數個半導體元件和複數個導電墊，設置於該第一表面上；自該半導體晶圓的第二表面形成複數個導通孔，其向內延伸並連通至該些導電墊；自該半導體基底第二表面之下形成一重佈線路層，其與該些導通孔內之導電墊電性連接，且該重佈線路層之邊緣外露於該半導體基底側壁； 形成一第一絕緣層於該半導體基底的該第二表面下方且具有一開口，其中該重佈線路層順應性地形成在該第一絕緣層的下方及該開口內；以及自該重佈線路層之下形成一導線層，其延伸至該半導體基底側壁而與該重佈線路層構成一電性接觸。
  18. 如申請專利範圍第17項所述之晶片封裝體的製造方法，形成該重佈線路層之步驟包括：形成一第一重佈線路層於該些導通孔內以電性連接該些導電墊，且延伸至該半導體晶圓第二表面之下；以及形成一第二重佈線路層於該第一重佈線路層之下並與該第一重佈線路層電性連接。
  19. 如申請專利範圍第18項所述之晶片封裝體的製造方法，更包括：順應性地形成一第二絕緣層於該半導體晶圓的該第二表面上以及該些導通孔之側壁上，且該第一絕緣層覆蓋該第一重佈線路層與該第一絕緣層，且該第一絕緣層內的該開口暴露出該第一重佈線路層；以及形成一第二重佈線路層於該第一絕緣層的該開口內以電性連接該第一重佈線路層，且延伸至該第一絕緣層上。
  20. 如申請專利範圍第19項所述之晶片封裝體的製造方法，更包括： 提供一載體層，與該半導體晶圓之該第一表面接合；薄化該半導體晶圓；提供一封裝層，接合於該半導體晶圓的該第二表面之下；形成一第三絕緣層於該封裝層之下；以及形成複數個溝槽凹口於該第三絕緣層、該封裝層和該第一絕緣層中，暴露出該第二重佈線路層之邊緣，並與該第一重佈線路層相隔一間距，其中該導線層順應性地形成於該些溝槽凹口內，且延伸至該第三絕緣層上。
  21. 如申請專利範圍第20項所述之晶片封裝體的製造方法，其中該載體層包括一半導體基底或一玻璃基底。
  22. 如申請專利範圍第21項所述之晶片封裝體的製造方法，更包括：形成一第一保護層覆蓋該導線層；形成複數個開口於該第一保護層中，暴露出該導線層；以及形成複數個導電凸塊於該第一保護層的該些開口中，與該導線層電性連接。
  23. 如申請專利範圍第22項所述之晶片封裝體的製造方法，其更包括移除該載體層；形成一第二保護層於該半導體晶圓的該第一表面之上；以及分割該半導體晶圓，形成複數個晶片封裝體。
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