TWI747261B - 晶粒封裝結構的製造方法 - Google Patents

晶粒封裝結構的製造方法 Download PDF

Info

Publication number
TWI747261B
TWI747261B TW109114389A TW109114389A TWI747261B TW I747261 B TWI747261 B TW I747261B TW 109114389 A TW109114389 A TW 109114389A TW 109114389 A TW109114389 A TW 109114389A TW I747261 B TWI747261 B TW I747261B
Authority
TW
Taiwan
Prior art keywords
layer
conductive
masks
manufacturing
copper
Prior art date
Application number
TW109114389A
Other languages
English (en)
Other versions
TW202141650A (zh
Inventor
賴建志
林泓彣
Original Assignee
典琦科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 典琦科技股份有限公司 filed Critical 典琦科技股份有限公司
Priority to TW109114389A priority Critical patent/TWI747261B/zh
Priority to US16/888,844 priority patent/US11302664B2/en
Publication of TW202141650A publication Critical patent/TW202141650A/zh
Application granted granted Critical
Publication of TWI747261B publication Critical patent/TWI747261B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H01L21/4828—Etching
    • H01L21/4832—Etching a temporary substrate after encapsulation process to form leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68313—Auxiliary support including a cavity for storing a finished device, e.g. IC package, or a partly finished device, e.g. die, during manufacturing or mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

一種晶粒封裝結構的製造方法包含下述操作。提供具有多個凹槽的導電基板。在各凹槽中設置晶粒。形成導電層，覆蓋晶粒及導電基板。形成圖案化光阻層於導電層上，圖案化光阻層具有多個開口暴露出導電層的多個區域。在導電層的各區域上形成遮罩，其中各遮罩包含銅層及位於銅層上的金屬層。在形成遮罩後，移除圖案化光阻層。利用遮罩，選擇性蝕刻導電層及其下的導電基板至預定深度，以形成多個導電凸塊以及多個電極，其中剩餘的導電基板包含底板，電極位在底板上，且導電凸塊位在晶粒上。形成上封膠層覆蓋底板及晶粒，其中遮罩的各金屬層或遮罩的各銅層露出上封膠層。

Description

晶粒封裝結構的製造方法
本發明係關於一種封裝結構的製造方法，特別有關於一種埋入式晶粒封裝結構的製造方法。
隨著消費性電子商品的普及，例如：手機、平板電腦、筆電等，消費者對於電子產品的高功能性與小型尺寸之需求越趨明顯。而晶片封裝製程是形成電子產品過程中之一的重要步驟。為使晶片封裝體之尺寸縮小化，並且進一步提升晶片封裝體之效能成為重要課題。
傳統的封裝製程係對切割自晶圓的半導體晶粒逐一進行封裝，其製程除了銲晶(Die Bonding)之外，尚包含打線接合(Wire bonding)、封膠(Molding)等，相當耗時費工。再者，傳統作法是將功率模組中的功率晶片使用銲線的方式進行電氣連接，功率晶片所產生的熱能不容易被有效的散熱。
有鑑於此，本發明之一目的在於提出一種可解決上述問題之晶粒封裝結構的製造方法。
根據本發明的多個實施例，提供一種晶粒封裝體的製造方法包含以下操作：提供具有多個凹槽的導電基板；在各凹槽中設置晶粒；形成導電層，覆蓋晶粒及導電基板；形成圖案化光阻層於導電層上，圖案化光阻層具有多個開口暴露出導電層的多個區域；在導電層的各區域上形成遮罩，其中各遮罩包含銅層及位於銅層上的金屬層；在形成遮罩後，移除圖案化光阻層；利用遮罩，選擇性蝕刻導電層及其下的導電基板至預定深度，以形成多個導電凸塊以及多個電極，其中剩餘的導電基板包含底板，電極位在底板上，且導電凸塊位在晶粒上；以及形成上封膠層覆蓋底板及晶粒，其中遮罩的各金屬層或該些遮罩的各該銅層露出上封膠層。
根據本發明的一些實施例，導電基板實質上由銅構成。
根據本發明的一些實施例，導電基板具有第一厚度及各凹槽具有深度，深度為第一厚度的45%至55%的範圍內。
根據本發明的一些實施例，各金屬層包含為鎳層以及位於鎳層上的金層。
根據本發明的一些實施例，所述方法更包含：在形成上封膠層之後，薄化底板，以形成薄化底層；以及圖案化薄化底層，而形成線路層。
根據本發明的一些實施例，所述方法更包含：在形 成線路層之後，形成下封膠層覆蓋線路層；以及切割上封膠層及下封膠層，以得到彼此分離的多個封裝結構。
根據本發明的一些實施例，封裝結構的厚度為約130μm至約200μm的範圍內。
根據本發明的一些實施例，形成導電層包含：使用化學鍍形成銅種子層；以及使用電鍍，在銅種子層上形成銅電鍍層。
根據本發明的一些實施例，形成上封膠層覆蓋底板及晶粒包含：形成封膠材料層覆蓋底板、晶粒、遮罩、電極及導電凸塊；以及薄化封膠材料層，使遮罩的各金屬層外露於薄化的封膠材料層。
根據本發明的一些實施例，形成上封膠層覆蓋底板及晶粒包含：形成封膠材料層覆蓋底板、晶粒、遮罩、電極及導電凸塊；薄化封膠材料層，其中遮罩的各金屬層被移除，使遮罩的各銅層外露於薄化的封膠材料層；以及在外露的遮罩的各銅層上形成金屬墊。
以下將以實施方式對上述之說明做詳細的描述，並對本發明之技術方案提供更進一步的解釋。
10:導電基板
10’:底板
10’’:薄化底層
12:黏著膠
20:凹槽
22:晶粒
24:區域
26:電極
28:導電凸塊
30:銅種子層
31:導電層
32:銅電鍍層
34:光阻層
35:遮罩
35A:銅層
35B:金屬層
36:上封膠層
37:封膠材料層
38:下封膠層
40:金屬墊
50:線路層
300:封裝結構
A:區域
H1:厚度
H2:深度
H3:厚度
H4:厚度
H5:厚度
本發明之觀點從後續描述以及附圖可以獲得更佳的理解。應注意的是，根據本產業的標準作業，許多特徵結構未按照比例繪製。事實上，許多特徵結構之尺寸可以任意地放大或縮小以清楚論述。
第1A至1B圖繪示本發明多個實施方式之封裝結構的製造方法的流程圖。
第2圖至第14圖繪示本發明多個實施方式之封裝結構的製造方法在不同製程階段的剖面示意圖。
為了使本發明實施方式的敘述更加詳盡與完備，下文針對了本發明的實施態樣與具體實施例提出了說明性的描述；但這並非實施或運用本發明具體實施例的唯一形式。以下所揭露的各實施例，在有益的情形下可相互組合或取代，也可在一實施例中附加其他的實施例，而無須進一步的記載或說明。
在以下描述中，將詳細敘述許多特定細節以使讀者能夠充分理解以下的實施例。然而，可在無此等特定細節之情況下實踐本揭露之實施例。在其他情況下，為簡化圖式，熟知的結構與裝置僅示意性地繪示於圖中。
在實施方式與申請專利範圍中，除非內文中對於冠詞有所特別限定，否則「一」與「該」可泛指單一個或複數個。關於本文中所使用之「約」、「大約」或「大致」的用語一般通常係指數值之誤差或範圍約百分之二十以內，較佳地是約百分之十以內，更佳地則是約百分五之以內。
本發明之一態樣是提供一種埋入式晶粒封裝結構的製造方法，藉由此製造方法可以簡化傳統的製程方法和減少封裝體的散熱問題。第1A至1B圖繪示本發明之一實 施方式之封裝結構的製造方法100的流程圖。第2至14圖繪示封裝結構的製造方法100中各製程階段的剖面示意圖。如第1A圖及第1B圖所示，方法100包含步驟S200、步驟S202、步驟S204、步驟S206、步驟S208、步驟S210、步驟S212、步驟S214、步驟S216、步驟S218、步驟S220、步驟S222、以及步驟S224。
參照步驟S200中，如第2圖所示，提供或接收導電基板10。導電基板10係由導電材質製成，例如：金屬、石墨烯、或半導體材質等。在一些實施例中，導電基板10實質上由銅製成。在一些實施例中，導電基板10的厚度H1為約欲進行封裝的晶粒(繪示於第4圖)之厚度的約2倍。例如，晶粒的厚度為約100μm，導電基板的厚度為約200μm。
參照步驟S202，如第3圖所示，在導電基板10上形成多個凹槽20。舉例來說，形成光阻層在導電基板10上，藉由微影製程在光阻層上形成多個開口。接著，藉由蝕刻製程將開口圖案轉移至導電基板10。形成的多個凹槽20各具有深度H2。在一些實施例中，深度H2約為厚度H1的45%-55%之範圍內，例如50%。在一些實施例中，蝕刻製程可包含乾式或濕式蝕刻。在一些實施例中，光阻層是乾式膜抗蝕劑(dry film resist，DFR)。
參照步驟S204，如第4圖所示，在各凹槽20中設置一晶粒22。晶粒22可包含，但不限於此，動態隨機存取記憶體(dynamic random access memory， DRAM)裝置、快閃記憶體(flash memory)裝置、固態隨機存取記憶體(static random access memory，SRAM)裝置、被動裝置、無線電頻率模組(radio frequency module)裝置、其他適合的裝置、或前述之組合。
在一些實施例中，晶粒22可藉由黏著製程(Die bonding)而固定在凹槽20內。具體而言，先在導電基板10的各凹槽20中放置黏著膠12，接著，在各凹槽20中設置一晶粒22。各晶粒22藉著各黏著膠12附著在各凹槽20底部，並且各晶粒22的側壁實質上碰觸或部份地碰觸各凹槽20的側壁。各晶粒22的頂表面實質上相較導電基板10的上表面略低、略高或齊平。接著，可選擇性地對導電基板10加熱，從而加速黏著反應。在一些實施例中，在每個凹槽20中設置一個晶粒22。在一些實施例中，每個晶粒具有一個晶片(Single chip)。在另一個實施例中，每個晶粒具有二個晶片(Dual chip)。在一些實施例中，凹槽的長寬約為0.1x0.16mm2。
參照步驟S206，如第5圖所示，在導體基板10上形成導電層31。在一些實施例中，導電層31包含銅種子層30及位於銅種子層30上的銅電鍍層32。詳細地說，形成銅種子層30以覆蓋晶粒22以及導體基板10之後，再形成銅電鍍層32於銅種子層30上。舉例來說，先在導體基板10的上以化學鍍銅形成銅種子層30，再於銅種子層30上方以電鍍方式形成銅電鍍層32。在一些實施例中， 銅種子層的厚度為約10μm至100μm。在一些實施例中，銅電鍍層的厚度為約10μm至100μm。
繼續參照第5圖，在形成導電層31之後，可選作地對導電層31實施平坦化製程，使其具有實質上平坦的表面。在一些實施例中，平坦化製程可包含機械研磨(grinding)製程、化學機械研磨(Chemical Mechanical Polish，CMP)、一或多種其他可應用的製程、或前述之組合。
參照步驟S208，如第6A圖所示，在導電層31上方形成圖案化的光阻層34，圖案化光阻層34具有多個開口暴露出導電層31的多個區域24。在一些實施例中，光阻層是乾式膜抗蝕劑(dry film resist；DFR)。
接續步驟S210，參照第6B圖，在光阻層34的各區域24上形成遮罩35，其作為後續步驟的抗蝕刻材料層。在一些實施例中，遮罩35包含銅層35A以及位於銅層35A上的金屬層35B。在一些實施例中，金屬層35B包含鎳層以及位於所述鎳層上的金層(出於簡化未繪示)。遮罩35的銅層35A或金屬層35B係以電鍍(electroplating)製程、無電鍍(electroless plating)製程、或其他合適的方法形成。在一些實施例中，金屬層35B由對於銅具有蝕刻選擇性的材質所製成。在一些實施例中，金屬層35B由可焊錫材質製成。
接續步驟S212，參照第6C圖，在形成遮罩35之後，移除圖案化光阻層34，從而餘留覆蓋在各區域24 上方的遮罩35。在一些實施例中，使用光阻剝除液或灰化法(Ash)移除光阻層34。
接續步驟S214，如第7圖所示，利用遮罩35作為抗蝕刻材料層，選擇性蝕刻導電層31及其下的導電基板10至預定深度，以形成多個導電凸塊28以及多個電極26。剩餘的導電基板包含底板10’，所形成的電極26位在底板10’上，導電凸塊28位在晶粒22上。在一些實施例中，使用濕式蝕刻法蝕刻導電層31及導電基板10。在一些實施例中，所述預定深度實質上約等於各凹槽20的深度。在一些實施例中，底板10’的厚度H3實質上與晶粒的厚度相等或更厚。
接續步驟S216，參照第8A至8C圖。如第8A圖所示，形成封膠材料層37覆蓋底板10’、晶粒22、遮罩35、電極26及導電凸塊28。然後，如第8B及8C圖所示，使用諸如研磨等方式對封膠材料層37進行薄化製程，而形成上封膠層36，其中遮罩35的金屬層35B或遮罩35的銅層35A露出上封膠層36。詳細地說，在本發明的一實施例中，如第8B圖所示，在進行薄化製程之後，遮罩35的金屬層35B外露於薄化的封膠材料層36，換句話說，遮罩35的金屬層35B被保留下來。在本發明的另一實施例中，如第8C圖所示，在進行薄化製程之後，遮罩35的金屬層35B被移除，而使遮罩35的銅層35A外露於上封膠層36。
在一些實施例中，封膠材料層37的形成方式之示 例包含射出(injecting)製程、旋塗製程、灌膠(dispensing)製程、薄膜層合(film lamination)製程、塗敷製程(application process)、或前述之組合。在一些實施例中，在封膠材料層37之形成過程中使用熱固化製程(thermal curing process)。
再參照步驟S216，在薄化封膠材料層37期間，藉由控制薄化製程，遮罩35的金屬層35B可為未被移除(如第8B圖)或被移除(如第8C圖)。若不移除遮罩35的金屬層35B，在各電極26及各導電凸塊28上的遮罩35之金屬層35B可直接作為金屬墊，提供封裝結構300與外部電路電氣連接之用。
值得注意的是，本發明所揭示的遮罩35提供至少二個功能。第一功能如步驟S214所述，使用遮罩35作為抗蝕刻材料層，以選擇性蝕刻導電層31及其下的導電基板10。另一功能如步驟S216中形成上封膠層36之後，露出的遮罩35的金屬層35B可直接用作金屬墊40(繪示於第9圖)，提供封裝結構300與外部電路電氣連接之用。此外，在步驟S208中，習知的作法之一係使用第一張光罩用於圖案化光阻層34，以光阻層作為選擇性蝕刻導電層31及其下的導電基板10的抗蝕刻材料層。然而，此方法將需要第二張光罩用於形成金屬墊40。由此可知，本發明所揭示的製造方法可簡化晶粒封裝結構的製造過程及減少生產成本。
接續操作步驟S218，參照第9圖，在形成上封膠 層36之後，若遮罩35的金屬層35B被移除，則在外露的遮罩35之銅層35A上形成多個金屬墊40。在一些實施例中，金屬墊使用電鍍(electroplating)製程、無電鍍(electroless plating)製程、化學氣相沉積(CVD)製程、物理氣相沉積(PVD)製程、印刷(printing)製程、或其他可應用的製程所形成。在一些實施例中，金屬墊由可焊錫材質製成。在一些實施例中，金屬墊包含鎳層以及位於所述鎳層上的金層。
參照第10圖，在形成金屬墊40之後，先薄化底板10’，以形成薄化底層10’’。薄化製程可包含機械研磨(Grinding)製程、化學機械研磨(Chemical Mechanical Polish，CMP)、或其他可應用的製程。
接續步驟S220，參照第11圖，將薄化底層10’’圖案化，以形成線路層50。例如，利用微影蝕刻製程，以形成具有圖案的線路層50。在一些實施例中，線路層50中的線路之線寬為晶粒之長度或寬度的約50%至約100%。
接續步驟S222，參照第12圖，在形成線路層50之後，形成下封膠層38覆蓋線路層50，使得下封膠層38實質上覆蓋線路層50以提供保護的功能。在一些實施例中，下封膠層38由環氧樹脂(epoxy-based resin)製成。在一些實施例中，下封膠層38之形成包含射出(injecting)製程、旋塗製程、灌膠(dispensing)製程、薄膜層合(film lamination)製程、塗敷製程(application process)、 或其他可應用的製程。在一些實施例中，在下封膠層38之形成過程中使用熱固化製程(thermal curing process)。
參照第12圖，接在形成下封膠層38之後，可對下封膠層38執行可選作的薄化製程，使得整個封裝結構的厚度可以控制在預定範圍內。薄化製程可包含機械研磨(grinding)製程、化學機械研磨(Chemical Mechanical Polish，CMP)、一或多種其他可應用的製程、或前述之組合。
接續步驟S224，進行切單製程，係沿第13圖所示之切割路徑S(即對應區域A之邊緣)切割上封膠層36及下封膠層38，如第14圖所示，以獲取複數個彼此分離的封裝結構300。在一些實施例中，封裝結構具有厚度H5為約130μm至約200μm的範圍，亦可產品需求作調整，厚度H5的範圍不在此限。
在多個實例中，晶粒封裝體可用以封裝光感測元件或發光元件。然其應用不限於此，舉例來說，其可應用於各種包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System；MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變 化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)製程對影像感測元件、發光二極體(light-emitting diodes；LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)或噴墨頭(ink printer heads)等半導體晶粒進行封裝。
綜上所述，本發明之晶片封裝結構的製造方法省去傳統製造方法中的打線接合(Wire bond)製程，且在蝕刻製程的選擇限制較少，可以簡化晶粒封裝結構的製造過程。再者，本發明包含一種埋入式晶粒封裝結構的製造方法，可以達到晶粒封裝結構在垂直方向上的微小化以及改善功率晶片的散熱效果。
前述內容概述了許多實施例或示例的特徵，使本技術領域中具有通常知識者可以從各方面更佳了解本發明。本技術領域中具有通常知識者應可理解，且輕易地以本發明為基礎來設計或修飾其他製程和結構，並以此達到相同的目的及/或達到與在此介紹的實施例等相同的優點。本技術領域中具有通常知識者也應理解這些相等的結構並未背離本發明的發明精神與範圍。在不背離本發明的發明精神和範圍的情況下，可對本發明進行各種改變，替換和變更。
36:上層封裝膠
38:下層封裝膠
50:線路層
40:金屬墊
H4:厚度

Claims (10)

  1. 一種晶粒封裝結構的製造方法，包含：
    提供具有多個凹槽的一導電基板；
    在各該凹槽中設置一晶粒；
    形成一導電層，覆蓋該些晶粒及該導電基板；
    形成一圖案化光阻層於該導電層上，該圖案化光阻層具有多個開口暴露出該導電層的多個區域；
    在該導電層的各該區域上形成一遮罩，其中各該遮罩包含一銅層及位於該銅層上的一金屬層；
    在形成該些遮罩後，移除該圖案化光阻層；
    利用該些遮罩，選擇性蝕刻該導電層及其下的該導電基板至一預定深度，以形成多個導電凸塊以及多個電極，其中剩餘的該導電基板包含一底板，該些電極位在該底板上，且該些導電凸塊位在該些晶粒上；以及
    形成一上封膠層覆蓋該底板及該些晶粒，其中該些遮罩的各該金屬層或該些遮罩的各該銅層露出該上封膠層。
  2. 如請求項1所述之晶粒封裝結構的製造方法，其中該導電基板實質上由銅構成。
  3. 如請求項1所述之晶粒封裝結構的製造方法，其中該導電基板具有一第一厚度及各該凹槽具有一深度，該深度為該第一厚度的45%至55%的範圍內。
  4. 如請求項1所述之晶粒封裝結構的製造方法，其中各該金屬層包含為一鎳層以及位於該鎳層上的一金層。
  5. 如請求項1所述之晶粒封裝結構的製造方法，更包含：
    在形成該上封膠層之後，薄化該底板，以形成一薄化底層；以及
    圖案化該薄化底層，而形成一線路層。
  6. 如請求項5所述之晶粒封裝結構的製造方法，更包含：
    在形成該線路層之後，形成一下封膠層覆蓋該線路層；以及
    切割該上封膠層及該下封膠層，以得到彼此分離的多個封裝結構。
  7. 如請求項6所述之晶粒封裝結構的製造方法，其中各該封裝結構具有一厚度為約130μm至約200μm的範圍內。
  8. 如請求項1所述之晶粒封裝結構的製造方法，其中形成該導電層包含：
    使用化學鍍形成一銅種子層；以及
    使用電鍍，在該銅種子層上形成一銅電鍍層。
  9. 如請求項1所述之晶粒封裝結構的製造方法，其中形成該上封膠層覆蓋該底板及該些晶粒包含：
    形成一封膠材料層覆蓋該底板、該些晶粒、該些遮罩、該些電極及該些導電凸塊；以及
    薄化該封膠材料層，使該些遮罩的各該金屬層外露於薄化的該封膠材料層。
  10. 如請求項1所述之晶粒封裝結構的製造方法，其中形成該上封膠層覆蓋該底板及該些晶粒包含：
    形成一封膠材料層覆蓋該底板、該些晶粒、該些遮罩、該些電極及該些導電凸塊；
    薄化該封膠材料層，其中該些遮罩的各該金屬層被移除，使該些遮罩的各該銅層外露於薄化的該封膠材料層；以及
    在外露的該些遮罩的各該銅層上形成一金屬墊。
TW109114389A 2020-04-29 2020-04-29 晶粒封裝結構的製造方法 TWI747261B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW109114389A TWI747261B (zh) 2020-04-29 2020-04-29 晶粒封裝結構的製造方法
US16/888,844 US11302664B2 (en) 2020-04-29 2020-05-31 Method of manufacturing die package structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW109114389A TWI747261B (zh) 2020-04-29 2020-04-29 晶粒封裝結構的製造方法

Publications (2)

Publication Number Publication Date
TW202141650A TW202141650A (zh) 2021-11-01
TWI747261B true TWI747261B (zh) 2021-11-21

Family

ID=78293321

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109114389A TWI747261B (zh) 2020-04-29 2020-04-29 晶粒封裝結構的製造方法

Country Status (2)

Country Link
US (1) US11302664B2 (zh)
TW (1) TWI747261B (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200908249A (en) * 2007-03-08 2009-02-16 Advanced Chip Eng Tech Inc Structure of semiconductor device package and the method of the same
TW201113992A (en) * 2009-10-07 2011-04-16 Xintec Inc Chip package and fabrication method thereof
TW201810551A (zh) * 2016-06-16 2018-03-16 思鷺科技股份有限公司 封裝結構

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060087010A1 (en) * 2004-10-26 2006-04-27 Shinn-Gwo Hong IC substrate and manufacturing method thereof and semiconductor element package thereby

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200908249A (en) * 2007-03-08 2009-02-16 Advanced Chip Eng Tech Inc Structure of semiconductor device package and the method of the same
TW201113992A (en) * 2009-10-07 2011-04-16 Xintec Inc Chip package and fabrication method thereof
TW201810551A (zh) * 2016-06-16 2018-03-16 思鷺科技股份有限公司 封裝結構

Also Published As

Publication number Publication date
US11302664B2 (en) 2022-04-12
US20210343672A1 (en) 2021-11-04
TW202141650A (zh) 2021-11-01

Similar Documents

Publication Publication Date Title
US11631611B2 (en) Wafer level chip scale packaging intermediate structure apparatus and method
TWI718606B (zh) 半導體元件及其形成方法
TWI727107B (zh) 封裝結構及其製造方法
TWI719189B (zh) 半導體封裝體、半導體元件及其形成方法
TWI694557B (zh) 半導體基板、半導體封裝件及其製造方法
CN107689333A (zh) 半导体封装件及其形成方法
CN105355569A (zh) 封装方法
WO2022012538A1 (zh) 多芯片3d封装结构及其制作方法
JP2013507788A (ja) マイクロエレクトロニクスパッケージ及びその製造方法
US10943846B2 (en) Chip package structure with heat conductive component and manufacturing thereof
CN102810520A (zh) 热改善的集成电路封装件
TW202025410A (zh) 封裝方法、面板組件、晶圓封裝體以及晶片封裝體
CN105374731A (zh) 封装方法
TW201806090A (zh) 封裝結構
CN105225974A (zh) 封装方法
TWI587464B (zh) 封裝結構及其製造方法
TWI704668B (zh) 晶粒封裝結構的製造方法
CN105390429A (zh) 封装方法
TWI602275B (zh) 封裝結構及其製作方法
TWI747261B (zh) 晶粒封裝結構的製造方法
US9324686B2 (en) Semiconductor chips having improved solidity, semiconductor packages including the same and methods of fabricating the same
CN113571431A (zh) 晶粒封装结构的制造方法
CN113380641A (zh) 晶粒封装结构的制造方法
CN113471160A (zh) 芯片封装结构及其制作方法
KR20130077565A (ko) 반도체 패키지 및 그 제조 방법