1331808 九、發明說明： • 【發明所屬之技術領域】 ' 本發明係有關於積體電路封裝體，特別是—種具 =善之導電性及穩固性之積體電路封裝體及其製^方 【先前技術】 I積體電路裝置的製程中，積體電路必須經過 步驟處理後’以使用於各種不同的應㈣域，例如，電 腦、手機或數位相機等。因此，積體電路封裝體的釺構 也直接影響最終積體電路裝置的效能。 … - 第1圖顯示一種習知的積體電路封裝體！。在第j -圖中，感光元件4形成於積體電路晶片2的上方，且電 性連接接合墊6。接著，保護層8形成在上述積體電路晶 片2上方，且覆蓋接合墊6。導電層1〇形成於積體電路 晶片2的側壁上，且電性連接接合墊6’如第1圖所示。 在習知之積體電路封裝體t，導電層僅與接合墊的側壁 接觸，因此，介於導電層與接合墊之間的導電性並不佳。 再者，由於導電層僅與接合墊的側壁接觸，使得導電層 與接合墊之間的結構強度較弱。 因此，亟需一種新的積體電路封裝體及其製作方 法，以增加導電層與接合墊的接觸面積及其結構強度。 【發明内容】 有鑑於此，本發明之一目的係提供一種具有高傳導 9002-A32786TWF；yungchieh 6 1331808 面積的積體電路封梦辨 ok 積趙電路晶片，具有體=封裝體’包含- 形成有-感光元件；—接及开 :：表面’且該上表面 的兮上声面卜0 ^ 接&墊，形成於該積體電路晶片 的。X上表面上’且電性連接該感光元件；以及 形成於該積體電路晶# ~ 導電層， 良成 ^ 日日月的側壁上，且包覆該接合墊的一 邊緣，以電性連接該接合墊。 ^發明之另一目的係提供一種具有高 體電路封裝體的製作古、、土 L ^ 積 / 。上述積體電路封裝體的製作 方法’包括提供具有—上#而芬一丁太it ^ ^ 曰 表面及一下表面的一積體電路 曰曰片 上表面形成有-感光元件，·形成-接合墊於 該積體電路的該上表面上’且電性連接該感光塾： 及形成導電層於該積體電路晶片的側壁上，且 接合墊的一邊緣，以電性連接該接合墊。 μ 上述積體電路封裝體中，由於導電層會包覆接合墊 的侧壁’使得導電層會同時接觸接合墊的上表面、側壁 及下表面，以增加導電層與接合墊的接觸面積，進而ς 加導電層與接合墊之間的導電性（conductivity)。再者，由曰 於上述導電層會包覆接合塾的側壁，因此，也可以增加 導電層與接合墊接觸部位的結構強度，進而增加積^電 路封裝體的機械強度以及穩固性（fastness)。 【實施方式】 接下來以實施例並配合圖式以詳細說明本發明，在 圖式或描述中，相似或相同部份係使用相同之符號。在 9002-A32786TWF;yungchieh 7 ⑴ 1808 圖式中，實施例之形狀或厚度可擴大，以簡化或是方便 標示。圖式中元件之部份將以描述說明之。可了解的是， 未綠示或描述之元件，可以是具有各種熟f該項技^者 所知的形式。此外，當敘述_層係位於—基材或是另一 層上時，此層可直接位於基材或是另一層上，或是盆間 亦可以有中介層。 〃 第2A-2G圖顯示根據本發明實施例製作積體電 裝體的剖面圖。在第2A圖中，係顯示一積體電路晶片 102的上視圖’且在上述積體電路晶片1()2的上表面區分 中央區104及周邊區106。第2β圖顯示沿著第2a圖a 至A，的剖面圖。在第2β圖中，提供具有上表面⑽及 下表面109的積體電路晶片102，且設置感光元件ιι〇於 積體電路晶片1〇2上方的中央區1〇4。又如第跎圖所示： 形成-接合墊108於積體電路晶# 1〇2上方的周邊區 106,且電性連接感光元件】】〇。上述接合墊⑽會圍繞 各中央區104的感光元件11〇，如第2Α圖所示。 第2C圖所示，形成一保護層（Dam) 112於積體 路晶片102的上表面107,且覆蓋接合墊1〇8，以保護接 ，塾108,而避免接合塾1〇8的氧化現象。接著，藉由黏 著片11 114貼附一第—基板116於積體電路晶片102的上 方幵/成間隙118於第一基板！ ^ 6與積體電路晶片 102之間。上述第一基板U6也可以稱為蓋板。 在一較佳實施例中，上述第-基板116較佳可以是 玻璃 '石英、蛋白石、_或其它合適的透明基板。上 9002-A32786TWF；yungchieh 1331808 述保護層112較佳可以是聚醯亞胺樹脂（p〇iyimide;打卜 環氧樹脂（epoxy)或其它合適的絕緣材料。_實施例中 上述黏著劑114較佳可以是包含環氧樹脂的黏、著^^料。’ 又如第2C圖所示，使用微影及蝕刻步驟，沿著切 開個別晶粒的預定切割線，移除部分積體電路晶片】， 且形成開口 120,以切開個別的晶粒。上述開口 12〇會暴 ，接合塾⑽的底部表面及保護々112。上賴刻步ς較 佳可以是乾姓刻或溼蝕刻。 在上述切開個的晶粒之前，也可選擇性地進行一 is的::化積體電路晶…厚度，以利切開晶 在第2D圖中，藉由膠材122，貝占附 ==102的下表面上1〇9。接著，形二1331808 IX. Description of the invention: • [Technical field to which the invention pertains] ' The present invention relates to an integrated circuit package body, in particular, an integrated circuit package body having a conductivity and stability of good quality and its manufacturing method. Prior Art In the process of the integrated circuit device, the integrated circuit must be processed in steps to be used in various fields (for example, computers, mobile phones or digital cameras). Therefore, the structure of the integrated circuit package also directly affects the performance of the final integrated circuit device. ... - Figure 1 shows a conventional integrated circuit package! . In the j-th diagram, the photosensitive member 4 is formed above the integrated circuit wafer 2, and is electrically connected to the bonding pad 6. Next, a protective layer 8 is formed over the above-described integrated circuit chip 2, and covers the bonding pad 6. The conductive layer 1 is formed on the sidewall of the integrated circuit wafer 2, and is electrically connected to the bonding pad 6' as shown in Fig. 1. In the conventional integrated circuit package t, the conductive layer is only in contact with the sidewall of the bonding pad, and therefore, the conductivity between the conductive layer and the bonding pad is not good. Moreover, since the conductive layer is only in contact with the sidewall of the bonding pad, the structural strength between the conductive layer and the bonding pad is weak. Therefore, there is a need for a new integrated circuit package and a method of fabricating the same to increase the contact area of the conductive layer with the bond pad and its structural strength. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide a high-conductivity 9002-A32786TWF; yungchieh 6 1331808 area of the integrated circuit seal dream ok product Zhao circuit wafer, with body = package 'include - formed with - Photosensitive element; - Connected and opened:: Surface 'and the upper surface of the upper surface of the surface is formed on the integrated circuit chip. The upper surface of the upper surface of the X is electrically connected to the photosensitive element; and is formed on the sidewall of the integrated circuit crystal ## conductive layer, which is formed on the sidewall of the solar cell, and covers an edge of the bonding pad to electrically connect the edge Mating pad. Another object of the invention is to provide an ancient, earthy L ^ product / with a high-body circuit package. The method for fabricating the above-mentioned integrated circuit package includes providing an integrated circuit having a surface on the surface of the upper surface and a lower surface. The upper surface of the wafer is formed with a photosensitive element, and the bonding pad is formed. The upper surface of the integrated circuit is electrically connected to the photosensitive layer: and a conductive layer is formed on the sidewall of the integrated circuit wafer, and an edge of the bonding pad is electrically connected to the bonding pad. In the above integrated circuit package, since the conductive layer covers the sidewall of the bonding pad, the conductive layer simultaneously contacts the upper surface, the sidewall and the lower surface of the bonding pad to increase the contact area between the conductive layer and the bonding pad, and further ς The conductivity between the conductive layer and the bond pad. Further, since the conductive layer covers the sidewall of the bonding pad, the structural strength of the contact portion between the conductive layer and the bonding pad can be increased, thereby increasing the mechanical strength and the fastness of the circuit package. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail with reference to the accompanying drawings, in which FIG. In the 9002-A32786TWF; yungchieh 7 (1) 1808 pattern, the shape or thickness of the embodiment can be expanded to simplify or facilitate the marking. Portions of the elements in the drawings will be described by way of illustration. It will be appreciated that elements that are not shown or described in the art may be in a form known to those skilled in the art. In addition, when the layer is located on the substrate or on another layer, the layer may be directly on the substrate or on another layer, or may have an interposer between the basins. 〃 2A-2G are cross-sectional views showing the fabrication of an integrated electrical body in accordance with an embodiment of the present invention. In Fig. 2A, a top view of an integrated circuit wafer 102 is shown, and a central region 104 and a peripheral region 106 are distinguished on the upper surface of the integrated circuit wafer 1 (2). The 2β-graph shows a cross-sectional view along the 2a to a. In the 2β-picture, the integrated circuit wafer 102 having the upper surface (10) and the lower surface 109 is provided, and the photosensitive member is disposed in the central portion 1〇4 above the integrated circuit wafer 1〇2. Further, as shown in the figure: the bonding pad 108 is formed in the peripheral region 106 above the integrated circuit crystal #1〇2, and is electrically connected to the photosensitive member. The bonding pad (10) surrounds the photosensitive member 11 of each central region 104 as shown in Fig. 2. As shown in FIG. 2C, a protective layer (Dam) 112 is formed on the upper surface 107 of the integrated circuit wafer 102, and covers the bonding pads 1〇8 to protect the bonding, 塾108, and avoid the oxidation of the bonding 塾1〇8. . Next, a first substrate 116 is attached to the upper substrate/gap 118 of the integrated circuit wafer 102 by the adhesive sheet 11 114 on the first substrate! ^ 6 is between the integrated circuit chip 102. The first substrate U6 may also be referred to as a cover. In a preferred embodiment, the first substrate 116 may preferably be a glass 'quartz, opal, _ or other suitable transparent substrate. Upper protective layer 112 may preferably be a polyimide resin or other suitable insulating material. The above-mentioned adhesive 114 is preferably used in the embodiment. It may be an adhesive containing epoxy resin. 'As shown in FIG. 2C, using a lithography and etching step, a part of the integrated circuit chip is removed along a predetermined cutting line for cutting individual crystal grains,] And forming an opening 120 to cut individual crystal grains. The opening 12 is violent, and the bottom surface of the bonding crucible (10) and the protective crucible 112. Preferably, the etching step may be dry etching or wet etching. Before the grain, it is also possible to selectively perform an is::the thickness of the integrated circuit crystal to facilitate the opening of the crystal in the 2D figure, by the adhesive 122, on the lower surface of the bond ==102 1〇9. Then, shape two
滑126於苐二基板, L 槪24的下表面上。上述膠材122較佳 二二含環氧樹脂、聚酸亞胺樹脂或其它合適的材 的A柄=基ί 124可以是與上述第-基板相似材質 適$料的不主思的是’第二基才反124也可以是其它合 晶片呢的承載基板。第—基板124可作為積體電路 預定圖中，藉由刻痕裝置，沿著切開個別晶粒的 = 線，進行一刻痕步驟，以形成一凹槽U8，且暴 露膠材122、接合墊y u且暴 m的表Φ。接著進保護層112的側壁及第-基板 122的步驟，以暴露接1丁執—移除部分保護層112及膠材 暴路接合墊108的部分上表面及下表面。 9002-A32786TWF；yu„gchieh 9 1331808 在一較佳實施例中，藉由上述移除步驟，較佳例如 是使用氧氣（〇2)或四氟化碳(CF4)氣體的電装㈣步驟， 移除凹槽128内部分保護層112及部分膠材122，使得膠 材122的側壁1221及保護層112的側壁ιΐ2ι會往後縮， 以暴露接合塾1G8的上表面及τ表面，如第2e圖所示。 在第2F圖中，接著，形成導電層13〇於上述凹槽 m之中，且電性連接接合塾⑽。在—較佳實施例中: 猎由例如是_ (sputtering)、無電錢法（也价〇1咖咖㈣ 或電鍍(plating)的方式，形成例如是銅、鋁、鎳或1它合 適的金屬層，於絕緣層126的下表面上，且由第二基^ 124及積體電路晶片1〇2的侧壁，延伸至接合墊】⑽的下 表面、侧壁及上表面，以包覆接合墊108的側壁。接著， 以微影及姓刻製程圖案化金屬層’以形成導電層13〇。在 另-實施财，也可以是使用_的方式形成金屬層於 絕緣層126的下表面上，接著再進行無電鍍法(也可以稱 為化學電鍍），形成金屬層於凹槽128之中。 值得注意的是’由於上述導電層13G會包覆接合塾 108的側壁，使得導電層13〇會同時接觸接合塾⑽的上 表面、側壁及下表面’以增加導電層130與接合墊1〇8 的接觸面積’進而增加導電層13〇與接合墊1〇8之間的 導電性。 又如第2F圖所示’形成阻辉膜132於上述導電層 130上，且暴露部分導電層13〇。接著，形成焊料球體134 於暴露的導電層13〇上。在完成上述步驟後，接著，藉 9002-A32786TWF;yungchieh 10 1331808 由切割刀片沿著個別晶粒的預切割線，分割成個別曰曰 粒，以完成一積體電路封裝體14〇，如第所示。曰曰 在第2G圖中，提供一上方形成有感光元件m及 接合墊108之積體電路晶片1〇2，且一保護層ιΐ2覆蓋於 接合墊108上。又如第2G圖所示，第一基板ιΐ6設置於 積體電路晶片102的上方，以及藉由膠材122貼附第二 基板Π4於積體電路晶片1〇2的下表面上。一導電層 形成於積體電路晶# 1〇2 _壁上’且包覆接合墊⑽ 的側壁，以電性連接上述接合墊1〇8，如第2(}圖所示。 之後，阻焊膜覆蓋部分導電層13〇，以暴露部分導電層。 且，焊料球體134形成暴露的導電層13〇上，電性連接 導電層130 ’以完成積體電路封裝體14〇。 值得注意的是，由於導電層會包覆接合墊的側壁， 使得導電層會同時接觸接合墊的上表面、側壁及下表 面，以增加導電層與接合墊的接觸面積，進而增加導電 層與接合墊之間的導電性。再者，由於上述導電層會包 覆接合墊的側壁，因此，也可以增加導電層與接合墊接 觸部位的結構強度’進而增加積體電路封裝體的機械強 度以及其穩固性。 雖然本發明已以較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之 精神和範圍内，當可作此許之更動與潤飾，因此本發明 之保護範圍當視後附之申請專利範圍所界定為準。 9002-A32786TWF；yungchieh 11 1331808 【圖式簡單說明】 第1圖係顯示習知積體電路封裝體的剖面圖；以及 第2A-2G圖係顯示根據本發明之實施例製作積體電 路封裝體的剖面圖。Slide 126 on the lower surface of the second substrate, L 槪 24. The above-mentioned rubber material 122 preferably has an epoxy resin, a polyimine resin or other suitable material, and the A handle=base ί 124 may be similar to the above-mentioned first substrate, and the material is not considered to be the first The second base can also be a carrier substrate for other wafers. The first substrate 124 can be used as a predetermined circuit in the integrated circuit. The scoring device performs a scoring step along the line of the individual crystal grains to form a groove U8, and exposes the adhesive material 122 and the bonding pad. And the table Φ of the storm m. The steps of the sidewalls of the protective layer 112 and the first substrate 122 are then exposed to expose portions of the upper protective layer 112 and the upper and lower surfaces of the adhesive slab bond pads 108. 9002-A32786TWF; yu„gchieh 9 1331808 In a preferred embodiment, by the above removal step, preferably, for example, an electrical (IV) step using oxygen (〇2) or carbon tetrafluoride (CF4) gas is removed. A portion of the protective layer 112 and the portion of the adhesive 122 in the recess 128 are such that the sidewall 1221 of the adhesive 122 and the sidewall ι2 of the protective layer 112 are retracted to expose the upper surface of the joint G1G8 and the surface of the τ, as shown in FIG. 2e. In Fig. 2F, next, a conductive layer 13 is formed in the above-mentioned recess m, and is electrically connected to the joint (10). In the preferred embodiment: the hunting is, for example, _ (sputtering), no electricity a method of forming a metal layer such as copper, aluminum, nickel or a suitable metal layer on the lower surface of the insulating layer 126 by a second substrate or The sidewalls of the integrated circuit wafer 1 2 extend to the lower surface, the sidewalls and the upper surface of the bonding pad (10) to cover the sidewalls of the bonding pad 108. Then, the metal layer is patterned by the lithography and the etch process. In order to form the conductive layer 13 〇. In another implementation, it is also possible to form a metal layer using _ On the lower surface of layer 126, an electroless plating process (also referred to as electroless plating) is performed to form a metal layer in the recess 128. It is noted that 'because the above conductive layer 13G will cover the sidewall of the bonded germanium 108 So that the conductive layer 13 同时 will simultaneously contact the upper surface, the sidewall and the lower surface ' of the bonding pad ( 10 ) to increase the contact area of the conductive layer 130 with the bonding pad 1 〇 8 and thereby increase between the conductive layer 13 〇 and the bonding pad 1 〇 8 Further, as shown in Fig. 2F, a resist film 132 is formed on the conductive layer 130, and a portion of the conductive layer 13 is exposed. Then, a solder ball 134 is formed on the exposed conductive layer 13A. After the step, next, by 9002-A32786TWF; yungchieh 10 1331808, the dicing blade is divided into individual granules along the pre-cut lines of the individual dies to complete an integrated circuit package 14〇, as shown in the figure. In FIG. 2G, an integrated circuit wafer 1 2 having a photosensitive element m and a bonding pad 108 formed thereon is provided, and a protective layer ι 2 is overlaid on the bonding pad 108. As shown in FIG. 2G, the first The substrate ΐ6 is set in the integrated body Above the wafer 102, and a second substrate Π4 is attached to the lower surface of the integrated circuit wafer 1〇2 by the adhesive material 122. A conductive layer is formed on the integrated circuit crystal #1〇2_wall and coated The sidewall of the bonding pad (10) is electrically connected to the bonding pad 1 〇 8 as shown in the second figure. After that, the solder resist film covers a portion of the conductive layer 13 以 to expose a portion of the conductive layer. Moreover, the solder ball 134 is formed. The exposed conductive layer 13 is electrically connected to the conductive layer 130' to complete the integrated circuit package 14A. It is worth noting that since the conductive layer covers the sidewall of the bonding pad, the conductive layer contacts the upper surface, the sidewall and the lower surface of the bonding pad at the same time to increase the contact area between the conductive layer and the bonding pad, thereby increasing the conductive layer and bonding. Conductivity between the pads. Furthermore, since the conductive layer covers the sidewall of the bonding pad, the structural strength of the conductive layer and the contact portion of the bonding pad can be increased, thereby increasing the mechanical strength of the integrated circuit package and its stability. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is to be understood that the present invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. 9002-A32786TWF; yungchieh 11 1331808 [Simplified Schematic] FIG. 1 is a cross-sectional view showing a conventional integrated circuit package; and FIG. 2A-2G is a view showing the fabrication of an integrated circuit package according to an embodiment of the present invention. Sectional view.
【主要元件符號說明】 1〜積體電路封裝體； 4~感光元件； 8〜保護層； 102〜積體電路晶片； 106〜週邊區域； 108〜接合墊； 110〜感光元件； 1121〜保護層側壁； 116〜第一基板； 120〜開口； 1221〜膠材側壁； 126〜絕緣層； 130〜導電層； 134〜焊料球體； 2〜積體電路晶片； 6〜接合塾； 10〜導電層； 104〜中央區域； 107〜上表面； 109〜下表面； 112〜保護層； 114〜黏著層； 118〜間隙； 122〜膠材； 124〜第二基板； 12 8〜凹槽； 132〜阻焊膜； 140〜積體電路封裝體。 9002-A32786TWF;yungchieh 12[Main component symbol description] 1 to integrated circuit package; 4~ photosensitive element; 8~ protective layer; 102~ integrated circuit chip; 106~ peripheral area; 108~ bonding pad; 110~ photosensitive element; Side wall; 116~first substrate; 120~opening; 1221~glene sidewall; 126~insulating layer; 130~conductive layer; 134~solder sphere; 2~integrated circuit wafer; 6~joining layer; 10~conductive layer; 104~ center area; 107~ upper surface; 109~ lower surface; 112~ protective layer; 114~ adhesive layer; 118~ gap; 122~ glue material; 124~ second substrate; 12 8~ groove; 132~ solder resist Film; 140 ~ integrated circuit package. 9002-A32786TWF; yungchieh 12