CN107154391A - 半导体封装 - Google Patents

半导体封装 Download PDF

Info

Publication number
CN107154391A
CN107154391A CN201610201472.2A CN201610201472A CN107154391A CN 107154391 A CN107154391 A CN 107154391A CN 201610201472 A CN201610201472 A CN 201610201472A CN 107154391 A CN107154391 A CN 107154391A
Authority
CN
China
Prior art keywords
moulding compound
layer
face
semiconductor packages
redistribution layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201610201472.2A
Other languages
English (en)
Other versions
CN107154391B (zh
Inventor
施信益
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of CN107154391A publication Critical patent/CN107154391A/zh
Application granted granted Critical
Publication of CN107154391B publication Critical patent/CN107154391B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

本发明公开了一种半导体封装，包含一重分布层中介层，具有一第一面、相对于所述第一面的一第二面，及延伸于所述第一面与所述第二面之间的一垂直侧壁；至少一半导体晶粒，设置在所述重分布层中介层的所述第一面上；一第一模塑料，设置在所述第一面上，所述第一模塑料包覆所述半导体晶粒；多数个焊锡凸块设置在所述第二面上；以及一第二模塑料，设置在所述第二面上，其中所述第二模塑料包围所述多数个焊锡凸块，并且覆盖所述重分布层中介层的所述垂直侧壁。

Description

半导体封装
技术领域
本发明涉及半导体封装技术领域，特别涉及一种具有双侧模塑结构的半导体封装。
背景技术
半导体技术发展的非常快速，尤其在半导体芯片朝向微型化发展的趋势下，对于半导体芯片的功能则越要求更多样性。也就是说，半导体芯片上会包含更多的输出/输入(I/O)接垫并且被设置在一个更小的区域内，这使得半导体芯片上接合垫的密度迅速增加，导致半导体芯片的封装变得更加困难。
目前，形成封装结构的主要目的在保护晶粒，避免其受到环境的因素破坏。另外，晶粒运作时产生的热，也必须通过封装结构有效率的被传导出去，才能确保晶粒能正常操作。
根据本领域公知技术，晶圆级封装(wafer level package,WLP)是在将晶粒切割分离之前先进行封装。晶圆级封装技术具有一定的优势，例如具有更短的生产周期时间和较低的成本。扇出晶圆级封装(fan-out wafer level package,FOWLP)则是将半导体芯片的接触垫通过基板上的重分布层(re-distribution layer,RDL)再分配到一个较大的面积上的封装技术。重分布层通常形成在一基板上，例如穿硅通孔(through silicon via,TSV)中介基板。
重分布层通常由另外形成在晶圆表面的金属层及介电层所构成，可以将芯片的I/O接垫重新绕线成间距较宽松的布局图案。上述重分布层通常包含形成薄膜聚合物，例如，苯并环丁烯(BCB)、聚酰亚胺(PI)或其它有机聚合物，以及金属化工艺，例如，铝金属或铜金属，如此将接垫重新绕线到一面积阵列组态。
由于制造工艺繁复，包含穿硅通孔的中介基板通常成本较高，因此，使用穿硅通孔中介基板的扇出晶圆级封装也会比较昂贵，并不利于特定的应用场合。
晶圆级封装工艺中，通常会在晶圆及安装在晶圆上的芯片表面覆盖一相对较厚的模塑料。此模塑料不只使封装整体的厚度增加，其与集成电路基底的热膨胀系数(CTE)的差异，容易导致封装翘曲或变形。晶圆翘曲(warpage)一直是本技术领域关注的问题。
晶圆翘曲使得芯片与晶圆之间的接合不易维持，导致“芯片对晶圆接合”(chip towafer,C2W)的组装失败。翘曲问题在大尺寸晶圆上更是明显，特别是对于具有小间距重分布层的晶圆级半导体封装工艺，此问题更是严重。有鉴于此，本领域仍需要一个改良的晶圆级封装及方法，可以解决上述先前技术的问题。
发明内容
本发明主要目的在于提供一种改良的具有双侧模塑结构的半导体封装及其制作方法，可以减轻模塑后翘曲变形的现象，并且可以避免重分布层中介层的裂开或脱层。
根据本发明一实施例，提供一种半导体封装，包含一重分布层中介层，具有一第一面、相对于所述第一面的一第二面，及延伸于所述第一面与所述第二面之间的一垂直侧壁；至少一半导体晶粒，设置在所述重分布层中介层的所述第一面上；一第一模塑料，设置在所述第一面上，所述第一模塑料包覆所述半导体晶粒；多数个焊锡凸块设置在所述第二面上；以及一第二模塑料，设置在所述第二面上，其中所述第二模塑料包围所述多数个焊锡凸块，且覆盖所述重分布层中介层的所述垂直侧壁。
根据本发明实施例，其中所述第一模塑料是直接接触所述第二模塑料。所述第一模塑料与所述第二模塑料具有不同的组成。
根据本发明实施例，其中另包含凸块设置在各所述焊锡凸块上，使得所述凸块突出于所述第二模塑料的一上表面。
毋庸置疑的，本领域的技术人士读完接下来本发明优选实施例的详细说明与附图后，均可了解本发明的目的。
附图说明
图1到图12是根据本发明实施例所绘示的剖面示意图，说明制作具有双侧模塑结构的半导体封装的方法，其中所述双侧模塑结构包封重分布层中介层；以及
图13到图22是根据本发明另一实施例所绘示的剖面示意图，说明以双侧模塑结构包封重分布层中介层的半导体封装的制作方法。
其中，附图标记说明如下：
10 半导体封装
300 载板
301 黏着层
310 钝化层
312 阻焊层
312a 上表面
314 开孔
400 重分布层中介层(RDL interposer)
400a 垂直侧壁
410 重分布层(RDL)
412 介电层
414 金属层
415 凸块垫
416 凸块
417 锡球焊垫
421 接触点
420a、420b 晶粒(芯片)
500 第一模塑料
510 钝化层
520 焊锡凸块
522 凸块
602 切割沟槽
600 第二模塑料
具体实施方式
接下来的详细说明须参考相关附图所示内容，用来说明可根据本发明具体实施的实施例。这些实施例已提供足够的细节，可使本领域技术人员充分了解并具体实施本发明。在不悖离本发明的范围内，仍可做结构上的修改，并应用在其他实施例上。
因此，接下来的详细说明并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具均等意义，也应属本发明涵盖的范围。
本发明实施例所参考的附图是示意图，并未按原比例绘制，且相同或类似的特征通常以相同的附图标记说明。在本说明书中，“晶粒”、“半导体芯片”与“半导体晶粒”具相同含意，可交替使用。
在本说明书中，“晶圆”与“基板”意指任何包含一暴露面，可根据本发明实施例所示在其上沉积材料，制作集成电路结构的结构物，例如重分布层(RDL)。须了解的是“基板”包含半导体晶圆，但并不限于此。"基板"在制造工艺中也意指包含制作于其上的材料层的半导体结构物。
请参考图1到图12。图1到图12是根据本发明实施例所绘示的剖面示意图，说明制作一半导体封装，例如具有被包封(encapsulated)的重分布层中介层(RDL interposer)的晶圆级封装(wafer level package，WLP)的方法。
如图1所示，首先提供一载板300。载板300可以是可卸式晶圆状基板，可以包含一黏着层(图未示)。接着在载板300的上表面形成至少一介电层或一钝化层310。钝化层310可以包含有机材料，例如，聚酰亚胺(polyimide,PI)，或者无机材料，例如，氮化硅、氧化硅等。接着在钝化层310上形成一重分布层(RDL)410。
重分布层410包含至少一介电层412与至少一金属层414。介电层412可包含有机材料，例如，聚酰亚胺(polyimide,PI)，或者无机材料，例如氮化硅、氧化硅等，但不限于此。金属层414可包含铝、铜、钨、钛、氮化钛或类似的材料。根据本发明实施例，金属层414可以包含多数个凸块垫415，从介电层412的一上表面暴露出来。在重分布层410上形成有一钝化层(或一介电层)510。应理解的是，钝化层510可以包含一阻焊层，但不限于此。
如图2所示，在重分布层410上形成多数个凸块416，例如，微凸块，用来进一步连结。凸块416可以分别直接形成在金属层414的凸块垫415上。可以用本领域公知的制造工艺形成所述凸块416。例如，先在钝化层510中形成开孔，暴露出个别的凸块垫415，接着可选择沉积一凸块下金属(under-bump metallurgy，UBM)层，然后以光刻胶定义出凸块416的位置，再以电镀工艺形成金属凸块，接着移除光刻胶，再将未被金属凸块覆盖的凸块下金属层去除。
根据本发明实施例，凸块416可以包含铜，但不限于此。在其它实施例中，凸块416可以是焊锡凸块，后续需要进一步回焊处理。需理解的是，也可以采用其它的凸块材料，并不限于上述举例的材料。在本实施例接下来的说明中，将钝化层310、重分布层410及钝化层510所构成的结构称为是重分布层中介层400。
如图3所示，形成凸块416之后，个别的覆晶芯片或晶粒420a及420b以有源面朝下面对重分布层中介层400的方式，通过凸块416安装到重分布层中介层400上，形成“芯片对晶圆接合”(chip to wafer,C2W)的层叠结构。
这些个别的覆晶芯片或晶粒420a及420b是具有特定功能的有源集成电路芯片，例如绘图处理器(GPU)、中央处理器(CPU)、存储器芯片等等。根据本发明实施例，晶粒420a及420b可以在同一封装内，并且是具有不同特定功能的芯片。
上述步骤完成后，可选择性的在每一晶粒420a及420b下方填充底胶(图未示)。之后，可进行热处理，使凸块416回焊。
如图4所示，完成晶粒接合后，接着在重分布层中介层400上覆盖一第一模塑料500。第一模塑料500覆盖住已经安装好的晶粒420a及420b与钝化层510的顶面。之后，可通过一固化工艺使第一模塑料500固化。根据本发明实施例，第一模塑料500可以例如是环氧树脂与二氧化硅填充剂的混和物，但并不限于此。接着，可选择性的将第一模塑料500的上部抛光移除，暴露出晶粒420a及420b的上表面。
如图5所示，在形成第一模塑料500之后，去除载板300，以暴露出钝化层310的一下表面。上述去除载板300可以利用激光工艺或紫外线(UV)照射工艺，但不限于此。
如图6所示，在去除载板300之后，接着于钝化层310暴露出来的底面上形成一阻焊层312。再利用光刻工艺在阻焊层312及钝化层310中形成开孔314，分别暴露出位于重分布层410的金属层414内的锡球焊垫417。
如图7所示，接着，在锡球焊垫417上分别形成焊锡凸块520。虽然图中未绘示，但应理解的是，可以在焊锡凸块520下方先形成凸块下金属(under bump metal,UBM)层。可以利用本领域公知的制造技术，例如电镀、网版印刷、植球法或其它合适的方法形成焊锡凸块520，因此这里不再特别说明细节。
如图8所示，在形成焊锡凸块520之后，进行一切割工艺，沿着晶圆切割道形成切割沟槽602，其贯穿阻焊层312、重分布层中介层400，并稍微延伸进入到第一模塑料500。上述切割沟槽602不会贯穿第一模塑料500的整个厚度。这时，重分布层中介层400的垂直侧壁400a自切割沟槽602中被暴露出来。根据本发明实施例，切割沟槽602可以利用切割刀或激光形成，但不限于此。
如图9所示，在形成切割沟槽602之后，接着在切割沟槽602中填入第二模塑料600，并且使第二模塑料600包封住焊锡凸块520。第二模塑料600同时覆盖住阻焊层312的上表面312a。之前暴露出来的重分布层中介层400的垂直侧壁400a这时被第二模塑料600覆盖。同样的，可通过一固化工艺使第二模塑料600固化。根据本发明实施例，第二模塑料600可以例如是环氧树脂与二氧化硅填充剂的混和物，但并不限于此。
根据本发明实施例，第二模塑料600与第一模塑料500可以具有不同的组成。例如，上述不同组成使得第二模塑料600可以在不影响到第一模塑料500结构的完整性以及之前形成在重分布层中介层400上的器件的温度下完成固化。
接着，如图10所示，可以继续进行一抛光工艺，例如化学机械抛光(CMP)工艺，用来去除第二模塑料600的上部，直到焊锡凸块520暴露出来。根据本发明实施例，在上述抛光工艺中，焊锡凸块520的部分上部也可能被去除。这时，焊锡凸块520的上表面可以是与第二模塑料600的上表面齐平。
如图11所示，接着在焊锡凸块520暴露出来的表面上形成凸块522，用来作为进一步连结使用。此时，使得凸块522突出于第二模塑料600的上表面。根据本发明实施例，凸块522可以利用本领域公知的方法形成，例如电镀或网版印刷等，但不限于此。
如图12所示，进行一晶圆切割工艺，将个别的半导体封装10彼此分离。需理解的是，在其它实施例中，每个半导体封装10中可以只包括单一晶粒。根据本发明的半导体封装的主要结构特征之一在于具有双侧模塑结构，包括第一模塑料500及第二模塑料600，包封住重分布层中介层400。其中，第一模塑料500是直接接触到第二模塑料600。本发明另一结构特征在于第二模塑料600是直接接触到焊锡凸块520以及重分布层中介层400的垂直侧壁400a。
本发明的特点在于重分布层中介层400的垂直侧壁400a被第二模塑料600包封保护住，因此，可以有效的避免重分布层中介层400的裂开或脱层。根据本发明所制作的晶圆级封装10的可靠度可以明显提升。另外，第二模塑料600还可以抵销第一模塑料500引起的翘曲应力，降低晶圆级封装10的翘曲现象。
图13到图22是根据本发明另一实施例所绘示的剖面示意图，说明以双侧模塑结构包封重分布层中介层的半导体封装的制作方法(或称为RDL后制法)，其中相同的区域、层或元件仍沿用相同的标示符号。
如图13所示，同样的，提供一载板300。载板300可以是可卸式晶圆状基板，可以包含一黏着层301。个别的覆晶芯片或晶粒420a及420b以无源面朝下面对载板300的方位，被安装在黏着层301上。根据本发明实施例，晶粒420a及420b的有源面上分别设有接触点421。
如图14所示，接着形成第一模塑料500。第一模塑料500覆盖住安装好的晶粒420a及420b与黏着层301的顶面。之后，可通过一固化工艺使第一模塑料500固化。根据本发明实施例，第一模塑料500可以例如是环氧树脂与二氧化硅填充剂的混和物，但并不限于此。接着，可选择性的将第一模塑料500的上部抛光移除。
如图15所示，接着在第一模塑料500上形成一重分布层(RDL)410。重分布层410包含至少一介电层412与至少一金属层414。介电层412可包含有机材料，例如，聚酰亚胺(polyimide,PI)，或者无机材料，例如氮化硅、氧化硅等，但不限于此。金属层414可包含铝、铜、钨、钛、氮化钛或类似的材料。根据本发明实施例，金属层414可以包含多数个锡球焊垫417，从介电层412的一上表面暴露出来。在重分布层410上形成有一钝化层(或一介电层)310。在本实施例接下来的说明中，将钝化层310及重分布层410称为是重分布层中介层400。
接着，将载板300及黏着层301去除，暴露出晶粒420a及420b的无源面，以及第一模塑料500的下表面。
如图16所示，去除载板300之后，接着于钝化层310上形成一阻焊层312。再利用光刻工艺，在阻焊层312及钝化层310中形成开孔314，分别暴露出位于重分布层410的金属层414内的锡球焊垫417。
如图17所示，接着，在锡球焊垫417上分别形成焊锡凸块520。虽然图中未绘示，但应理解的是，可以在焊锡凸块520下方先形成凸块下金属(UBM)层。可以利用本领域公知的制造技术，例如电镀、网版印刷、植球法或其它合适的方法形成焊锡凸块520，因此这里不再特别说明细节。
如图18所示，在形成焊锡凸块520之后，进行一切割工艺，沿着晶圆切割道形成切割沟槽602，其贯穿阻焊层312、重分布层中介层400，并且稍微延伸进入到第一模塑料500。上述切割沟槽602不会贯穿第一模塑料500的整个厚度。这时，重分布层中介层400的垂直侧壁400a自切割沟槽602中被暴露出来。根据本发明实施例，切割沟槽602可以利用切割刀或激光形成，但不限于此。
如图19所示，在形成切割沟槽602之后，接着在切割沟槽602中填入第二模塑料600，并且使第二模塑料600包封住焊锡凸块520。第二模塑料600同时覆盖阻焊层312的上表面312a。暴露出来的重分布层中介层400的垂直侧壁400a这时被第二模塑料600覆盖。同样的，可通过一固化工艺使第二模塑料600固化。根据本发明实施例，第二模塑料600可以例如是环氧树脂与二氧化硅填充剂的混和物，但并不限于此。
根据本发明实施例，第二模塑料600与第一模塑料500可以具有不同的组成。例如，上述不同组成使得第二模塑料600可以在不影响到第一模塑料500结构的完整性以及之前形成在重分布层中介层400上的器件的温度下完成固化。
如图20所示，继续进行一抛光工艺，例如化学机械抛光(CMP)工艺，用来去除第二模塑料600的上部，直到焊锡凸块520暴露出来。根据本发明实施例，在上述抛光工艺中，焊锡凸块520的部分上部也可能被去除。这时，焊锡凸块520的上表面可以是与第二模塑料600的上表面齐平。
如图21所示，接着在焊锡凸块520的暴露出来的表面上形成凸块522，用来作为进一步连结使用。此时，凸块522突出于第二模塑料600的上表面。根据本发明实施例，凸块522可以利用本领域公知的方法形成，例如电镀或网版印刷等，但不限于此。
如图22所示，进行一晶圆切割工艺，将个别的半导体封装10彼此分离。根据本发明的半导体封装的主要结构特征之一在于具有双侧模塑结构，包括第一模塑料500及第二模塑料600，包封住重分布层中介层400。第一模塑料500是直接接触到第二模塑料600。本发明另一结构特征在于第二模塑料600是直接接触到焊锡凸块520以及重分布层中介层400的垂直侧壁400a。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (9)

1.一种半导体封装，其特征在于，包含：
一重分布层中介层，具有一第一面、相对于所述第一面的一第二面，以及延伸于所述第一面与所述第二面之间的一垂直侧壁；
至少一半导体晶粒，设置在所述重分布层中介层的所述第一面上；
一第一模塑料，设置在所述第一面上，其中所述第一模塑料包覆所述半导体晶粒；
多数个焊锡凸块，设置在所述第二面上；以及
一第二模塑料，设置在所述第二面上，其中所述第二模塑料包围所述多数个焊锡凸块，且覆盖所述重分布层中介层的所述垂直侧壁。
2.根据权利要求1所述的半导体封装，其特征在于，所述第一模塑料是直接接触所述第二模塑料。
3.根据权利要求1所述的半导体封装，其特征在于，另包含凸块设置在各所述焊锡凸块上，使得所述凸块突出于所述第二模塑料的一上表面。
4.根据权利要求1所述的半导体封装，其特征在于，所述重分布层中介层包含一重分布层，而所述重分布层包含至少一介电层及至少一金属层。
5.根据权利要求4所述的半导体封装，其特征在于，所述介电层包含聚酰亚胺、氮化硅或氧化硅。
6.根据权利要求4所述的半导体封装，其特征在于，所述金属层包含铝、铜、钨、钛或氮化钛。
7.根据权利要求4所述的半导体封装，其特征在于，所述重分布层中介层另包含一钝化层，设置在所述介电层上。
8.根据权利要求1所述的半导体封装，其特征在于，所述第一模塑料与所述第二模塑料具有不同的组成。
9.根据权利要求1所述的半导体封装，其特征在于，所述第一模塑料的一上部是被抛光移除掉，以暴露出所述半导体晶粒的一上表面。
CN201610201472.2A 2016-03-03 2016-03-31 半导体封装 Active CN107154391B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/060,577 2016-03-03
US15/060,577 US9613895B1 (en) 2016-03-03 2016-03-03 Semiconductor package with double side molding

Publications (2)

Publication Number Publication Date
CN107154391A true CN107154391A (zh) 2017-09-12
CN107154391B CN107154391B (zh) 2018-11-02

Family

ID=58419549

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610201472.2A Active CN107154391B (zh) 2016-03-03 2016-03-31 半导体封装

Country Status (3)

Country Link
US (1) US9613895B1 (zh)
CN (1) CN107154391B (zh)
TW (1) TWI651816B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109962038A (zh) * 2017-12-26 2019-07-02 财团法人工业技术研究院 封装结构及其形成方法
CN113078148A (zh) * 2021-03-12 2021-07-06 上海易卜半导体有限公司 半导体封装结构、方法、器件和电子产品

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10522505B2 (en) 2017-04-06 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
US11244918B2 (en) * 2017-08-17 2022-02-08 Semiconductor Components Industries, Llc Molded semiconductor package and related methods
CN112908948A (zh) * 2021-01-18 2021-06-04 上海先方半导体有限公司 一种封装结构及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001293A1 (en) * 2004-08-31 2007-01-04 Tongbi Jiang Semiconductor assemblies including redistribution layers and packages and assemblies formed therefrom
CN101315918A (zh) * 2007-06-01 2008-12-03 松下电器产业株式会社 半导体装置及其制造方法
CN202443962U (zh) * 2011-12-27 2012-09-19 日月光半导体制造股份有限公司 晶圆级半导体封装构造
CN103137583A (zh) * 2011-11-30 2013-06-05 台湾积体电路制造股份有限公司 晶圆上芯片结构及其形成方法
US20140077364A1 (en) * 2012-09-14 2014-03-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Wire Studs as Vertical Interconnect in FO-WLP
US20150014855A1 (en) * 2013-07-15 2015-01-15 Weng Foong Yap Microelectronic packages and methods for the fabrication thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL223414A (en) * 2012-12-04 2017-07-31 Elta Systems Ltd Integrated electronic device and method for creating it

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001293A1 (en) * 2004-08-31 2007-01-04 Tongbi Jiang Semiconductor assemblies including redistribution layers and packages and assemblies formed therefrom
CN101315918A (zh) * 2007-06-01 2008-12-03 松下电器产业株式会社 半导体装置及其制造方法
CN103137583A (zh) * 2011-11-30 2013-06-05 台湾积体电路制造股份有限公司 晶圆上芯片结构及其形成方法
CN202443962U (zh) * 2011-12-27 2012-09-19 日月光半导体制造股份有限公司 晶圆级半导体封装构造
US20140077364A1 (en) * 2012-09-14 2014-03-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Wire Studs as Vertical Interconnect in FO-WLP
US20150014855A1 (en) * 2013-07-15 2015-01-15 Weng Foong Yap Microelectronic packages and methods for the fabrication thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109962038A (zh) * 2017-12-26 2019-07-02 财团法人工业技术研究院 封装结构及其形成方法
CN113078148A (zh) * 2021-03-12 2021-07-06 上海易卜半导体有限公司 半导体封装结构、方法、器件和电子产品
CN113078148B (zh) * 2021-03-12 2024-03-26 上海易卜半导体有限公司 半导体封装结构、方法、器件和电子产品

Also Published As

Publication number Publication date
TW201733040A (zh) 2017-09-16
CN107154391B (zh) 2018-11-02
TWI651816B (zh) 2019-02-21
US9613895B1 (en) 2017-04-04

Similar Documents

Publication Publication Date Title
CN107195594B (zh) 具有侧壁保护重布层中介层的半导体封装及其制造方法
US10867960B2 (en) Device package including molding compound having non-planar top surface around a die and method of forming same
KR101690371B1 (ko) 몰딩 화합물 내에 리세스들을 가진 집적 팬아웃 패키지 구조
KR102258947B1 (ko) 제어 가능한 스탠드오프를 갖는 팬-아웃 패키지
KR101962508B1 (ko) 트렌치 형성을 통한 쏘잉 유도 박리의 제거
CN107154391B (zh) 半导体封装
US9373610B2 (en) Process for forming package-on-package structures
KR102170575B1 (ko) 휨 감소를 위한 인포 패키지 지지
CN107195593A (zh) 半导体封装及其制造方法
US20170213801A1 (en) Method for manufacturing a package-on-package assembly
CN107104053B (zh) 制作晶圆级封装的方法
US20230260899A1 (en) Semiconductor package and manufacturing method thereof
US11756873B2 (en) Semiconductor package and manufacturing method thereof
TWI787753B (zh) 封裝件中的嵌入式應力吸收體及其形成方法
KR100596797B1 (ko) 웨이퍼 레벨 패키지의 제조방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant