TWI651816B - 具有雙側模封結構的半導體封裝 - Google Patents

具有雙側模封結構的半導體封裝 Download PDF

Info

Publication number
TWI651816B
TWI651816B TW105110831A TW105110831A TWI651816B TW I651816 B TWI651816 B TW I651816B TW 105110831 A TW105110831 A TW 105110831A TW 105110831 A TW105110831 A TW 105110831A TW I651816 B TWI651816 B TW I651816B
Authority
TW
Taiwan
Prior art keywords
molding
semiconductor package
layer
molding die
rdl
Prior art date
Application number
TW105110831A
Other languages
English (en)
Other versions
TW201733040A (zh
Inventor
施信益
Original Assignee
美光科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美光科技公司 filed Critical 美光科技公司
Publication of TW201733040A publication Critical patent/TW201733040A/zh
Application granted granted Critical
Publication of TWI651816B publication Critical patent/TWI651816B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29184—Tungsten [W] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

一種半導體封裝，包含一RDL中介層，具有一第一面、相對於該第一面的一第二面，及延伸於該第一面與該第二面之間的一垂直側壁；至少一半導體晶粒，設於該RDL中介層的該第一面上；一第一成型模料，設於該第一面上，該第一成型模料包覆該半導體晶粒；複數個焊錫凸塊設於該第二面上；以及一第二成型模料，設於該第二面上，其中該第二成型模料包圍該複數個焊錫凸塊或錫球，且覆蓋該RDL中介層的該垂直側壁。

Description

具有雙側模封結構的半導體封裝
本發明係有關於半導體封裝技術領域，特別是有關於一種具有雙側模封結構的半導體封裝及其製作方法。
半導體技術發展的非常快速，尤其在半導體晶片朝向微型化發展的趨勢下，對於半導體晶片的功能則越要求更多樣性。也就是說，半導體晶片上勢必會有更多的輸出/輸入（I/O）墊被擠在一個更小的區域，這使得半導體晶片上接合墊的密度迅速增加，導致半導體晶片的封裝變得更加困難。
已知，形成封裝結構的主要目的在保護晶粒，以免其受到外界因子破壞。此外，晶粒產生的熱也必須透過封裝結構有效率的被傳導出去，以確保晶粒能正常操作。
如本領域中公知的，晶圓級封裝（WLP）係在將晶粒切割分離之前先進行封裝。晶圓級封裝技術具有一定的優勢，如更短的生產週期時間和較低的成本。扇出晶圓級封裝（FOWLP）則是將半導體晶片的接觸墊通過基板上的重佈線層（RDL）再分配到一較大的面積上的封裝技術。重佈線層（RDL）通常形成在一基板上，例如穿矽通孔（TSV）中介基板。
重佈線層通常由額外的金屬層及介電層所構成，其形成在晶圓表面，將晶片的I/O墊重新繞線成間距較寬鬆的佈局圖案。上述重分佈通常利用薄膜聚合物，例如，苯並環丁烯（BCB）、聚亞醯胺（PI）或其它有機聚合物，以及金屬化製程，例如，鋁金屬或銅金屬，如此將接合墊重繞線至一面積陣列組態。
由於製程繁複，TSV中介基板通常成本較高，因此，使用TSV中介基板的扇出晶圓級封裝也會比較昂貴，並不利於特定的應用場合。
晶圓級封裝製程中，通常會在晶圓及安裝在晶圓上的晶片表面覆蓋一相對較厚的成型模料。此成型模料與積體電路基底的熱膨脹係數(CTE)差異，容易導致封裝翹曲或變形，也使得封裝整體的厚度增加。晶圓翹曲(warpage)一直是該領域關注的問題。
晶圓翹曲使晶片與晶圓間的接合不易維持，使“晶片對晶圓接合”(chip to wafer)的組裝失敗。翹曲問題在大尺寸晶圓上更是明顯，特別是對於具有小間距重佈線層的晶圓級半導體封裝製程，此問題更為嚴重。因此，業界仍需要一個改良的晶圓級封裝及方法，可以解決上述先前技術的問題。
本發明主要目的在提供一種改良的具有雙側模封結構的半導體封裝及其製作方法，可以減輕模封後翹曲現象，並且避免RDL中介層的裂開或脫層。
根據本發明一實施例，提供一種半導體封裝，包含一重佈線層（RDL）中介層，具有一第一面、相對於該第一面的一第二面，及延伸於該第一面與該第二面之間的一垂直側壁；至少一半導體晶粒，設於該RDL中介層的該第一面上；一第一成型模料，設於該第一面上，該第一成型模料包覆該半導體晶粒；複數個焊錫凸塊設於該第二面上；以及一第二成型模料，設於該第二面上，其中該第二成型模料包圍該複數個焊錫凸塊或錫球，且覆蓋該RDL中介層的該垂直側壁。
根據本發明實施例，其中該第一成型模料係直接接觸該第二成型模料。該第一成型模料與該第二成型模料具有不同的組成。
根據本發明實施例，其中另包含凸塊設於各該焊錫凸塊上，使得該凸塊突出於該第二成型模料的一上表面。
無庸置疑的，該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後，均可了解本發明的目的。
接下來的詳細敘述係參照相關圖式所示內容，用來說明可依據本發明具體實行的實施例。這些實施例已提供足夠的細節，可使本領域技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，仍可做結構上的修改，並應用在其他實施例上。
因此，接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求界定。與本發明權利要求具均等意義者，也應屬本發明涵蓋的範圍。
本發明實施例所參照的附圖為示意圖，並未按原比例繪製，且相同或類似的特徵通常以相同的附圖標記描述。在本說明書中，“晶粒”、“半導體晶片”與“半導體晶粒”具相同含意，可交替使用。
在本說明書中，“晶圓”與“基板”意指任何包含一暴露面，可依據本發明實施例所示在其上沉積材料，製作積體電路結構的結構物，例如重佈線層（RDL）。須了解的是“基板”包含半導體晶圓，但並不限於此。"基板"在製程中也意指包含製作於其上的材料層的半導體結構物。
請參閱第1圖至第12圖。第1圖至第12圖為根據本發明實施例所繪示的示意性剖面圖，例示製作一半導體封裝，如具有包封（encapsulated）重佈線層中介層（RDL interposer）的晶圓級封裝（wafer level package，WLP）的方法。
如第1圖所示，首先提供一載板300。載板300可以是可卸式晶圓狀基板，可以包含一黏著層（圖未示）。在載板300的上表面形成有至少一介電層或一鈍化層310。鈍化層310可以包含有機材料，例如，聚醯亞胺（polyimide, PI），或者無機材料，例如，氮化矽、氧化矽等。接著在鈍化層310上形成一重佈線層（RDL）410。
重佈線層410包含至少一介電層412與至少一金屬層414。介電層412可包含有機材料，例如，聚亞醯胺(polyimide, PI)，或者無機材料，例如氮化矽、氧化矽等，但不限於此。金屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似的材料。根據本發明實施例，金屬層414可以包含複數個凸塊墊415，從介電層412的一上表面顯露出來。在重佈線層410上形成有一鈍化層（或一介電層）510。應理解的是，鈍化層510可以包含一防銲層，但不限於此。
如第2圖所示，在重佈線層410上形成複數個凸塊416，例如，微凸塊，用以進一步連結。凸塊416可以分別直接形成在金屬層414的凸塊墊415上。所述形成凸塊416的方法為周知技藝。例如，先在鈍化層510中形成開孔，顯露出個別的凸塊墊415，接著可選擇沉積一凸塊下金屬（under-bump metallurgy，UBM）層，然後以光阻定義出凸塊416的位置，再以電鍍製程形成金屬凸塊，接著移除光阻，再將未被金屬凸塊覆蓋的UBM層去除。
根據本發明實施例，凸塊416可以包含銅，但不限於此。在其它實施例中，凸塊416可以是焊錫凸塊，後續需要進一步回焊處理。需理解的是，也可以採用其它的凸塊材料，不限於上述所舉。以下，將鈍化層310、重佈線層410及鈍化層510所構成的結構稱為RDL中介層400。
如第3圖所示，形成凸塊416之後，個別的覆晶晶片或晶粒420a及420b以主動面朝下面對RDL中介層400的方式，藉由凸塊416安裝至RDL中介層400上，形成“晶片對晶圓接合”(C2W)的層疊結構。
這些個別的覆晶晶片或晶粒420a及420b為具有特定功能的主動積體電路晶片，例如繪圖處理器(GPU)、中央處理器(CPU)、記憶體晶片等等。根據本發明實施例，晶粒420a及420b可以在同一封裝內，而為具有不同特定功能的晶片。
上述步驟完成後，可選擇性地在每一晶粒420a及420b下方填充底膠（圖未示）。隨後，可進行熱處理，使凸塊416回焊。
如第4圖所示，完成晶粒接合後，接著在RDL中介層400上覆蓋一第一成型模料500。第一成型模料500覆蓋住已安裝好的晶粒420a及420b與鈍化層510的頂面。隨後，第一成型模料500可藉由一固化製程使之固化。根據本發明實施例，第一成型模料500例如為環氧樹脂與二氧化矽填充劑的混和物，但並不限於此。接著，可選擇將第一成型模料500上部磨除，顯露出晶粒420a及420b的上表面。
如第5圖所示，在形成第一成型模料500之後，去除載板300，以顯露出鈍化層310的一下表面。上述去除載板300可以利用雷射製程或紫外線（UV）照射製程，但不限於此。
如第6圖所示，在去除載板300之後，接著於鈍化層310顯露出來的底面上形成一防銲層312。再利用微影製程於防銲層312及鈍化層310中形成開孔314，分別顯露出位於重佈線層410的金屬層414內的錫球焊墊417。
如第7圖所示，接著在錫球焊墊417上分別形成焊錫凸塊520。雖然圖中未繪示，但應理解的是，焊錫凸塊520下方可以先形成凸塊下金屬（UBM）層。所述形成焊錫凸塊520的方法為周知技藝，故其細節不另贅述。例如，焊錫凸塊520可以利用電鍍、網版印刷、植球法或其它合適的方法形成。
如第8圖所示，在形成焊錫凸塊520之後，進行一切割製程，沿著晶圓切割道形成切割溝槽602，其貫穿防銲層312、RDL中介層400，並稍微延伸進入到第一成型模料500。上述切割溝槽602不會貫穿第一成型模料500的整個厚度。此時，RDL中介層400的垂直側壁400a在切割溝槽602中被顯露出來。根據本發明實施例，切割溝槽602可以利用切割刀或雷射形成，但不限於此。
如第9圖所示，在形成切割溝槽602之後，接著於切割溝槽602中填入一第二成型模料600，使第二成型模料600包封住焊錫凸塊520。第二成型模料600同時覆蓋防銲層312的上表面312a。先前顯露出來的RDL中介層400的垂直側壁400a此時被第二成型模料600所覆蓋。同樣的，第二成型模料600可藉由一固化製程使之固化。根據本發明實施例，第二成型模料600例如為環氧樹脂與二氧化矽填充劑的混和物，但並不限於此。
根據本發明實施例，第二成型模料600與第一成型模料500可以具有不同的組成。例如，上述不同組成使得第二成型模料600可以在不影響到第一成型模料500結構完整性及先前形成在RDL中介層400上的元件的溫度下完成固化。
接著，如第10圖所示，可以繼續進行一研磨製程或一拋光製程，例如化學機械研磨（CMP）製程，以去除第二成型模料600的上部，直到防銲層520顯露出來。根據本發明實施例，在上述研磨或拋光製程中，焊錫凸塊520的部分上部也可能被去除。此時，焊錫凸塊520的上表面可以與第二成型模料600的上表面齊平。
如第11圖所示，接著在焊錫凸塊520的顯露出的表面形成凸塊522，用於進一步連結，此時，使得凸塊522突出於第二成型模料600的上表面。根據本發明實施例，凸塊522可以利用習知方法形成，例如電鍍或網版印刷等，但不限於此。
如第12圖所示，進行一晶圓切割製程，將個別的半導體封裝10彼此分離。需理解的是，在其它實施例中，每個半導體封裝10中可以只包括單一晶粒。本發明的主要特徵之一在於具有雙側模封結構，包括第一成型模料500及第二成型模料600，包封住RDL中介層400。第一成型模料500係直接接觸到第二成型模料600。本發明另一結構特徵在於第二成型模料600係直接接觸到焊錫凸塊520以及RDL中介層400的垂直側壁400a。
本發明的優點在於RDL中介層400的垂直側壁400a被第二成型模料600包覆保護住，因此，可以有效的避免RDL中介層400的裂開或脫層。晶圓級封裝10的可靠度可以明顯提升。此外，第二成型模料600可以抵銷第一成型模料500引起的翹曲應力，降低晶圓級封裝10的翹曲現象。
第13圖至第22圖為根據本發明另一實施例所繪示的示意性剖面圖，例示以雙側模封結構包封RDL中介層的半導體封裝的製作方法（或RDL後製法），其中相同的區域、層或元件仍沿用相同的標是符號。
如第13圖所示，同樣提供一載板300。載板300可以是可卸式晶圓狀基板，可以包含一黏著層301。個別的覆晶晶片或晶粒420a及420b以被動面朝下面對載板300的方式，安置在黏著層301上。根據本發明實施例，晶粒420a及420b的主動面上分別設有接觸點421。
如第14圖所示，接著形成一第一成型模料500。第一成型模料500覆蓋住安裝好的晶粒420a及420b與黏著層301的頂面。隨後，第一成型模料500可藉由一固化製程使之固化。根據本發明實施例，第一成型模料500例如為環氧樹脂與二氧化矽填充劑的混和物，但並不限於此。接著，可選擇將第一成型模料500上部磨除。
如第15圖所示，接著在第一成型模料500上形成一重佈線層（RDL）410。重佈線層410包含至少一介電層412與至少一金屬層414。介電層412可包含有機材料，例如，聚亞醯胺(polyimide, PI)，或者無機材料，例如氮化矽、氧化矽等，但不限於此。金屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似的材料。根據本發明實施例，金屬層414可以包含複數個錫球焊墊417，從介電層412的一上表面顯露出來。在重佈線層410上形成有一鈍化層（或一介電層）310。根據此實施例，將鈍化層310及重佈線層410稱為RDL中介層400。
接著，將載板300及黏著層301去除，顯露出晶粒420a及420b的被動面，以及第一成型模料500的下表面。
如第16圖所示，去除載板300之後，接著於鈍化層310上形成一防焊層312。再利用微影製程於防銲層312及鈍化層310中形成開孔314，分別顯露出位於重佈線層410的金屬層414內的錫球焊墊417。
如第17圖所示，接著在錫球焊墊417上分別形成焊錫凸塊520。雖然圖中未繪示，但應理解的是，焊錫凸塊520下方可以先形成凸塊下金屬（UBM）層。所述形成焊錫凸塊520的方法為周知技藝，故其細節不另贅述。例如，焊錫凸塊520可以利用電鍍、網版印刷、植球法或其它合適的方法形成。
如第18圖所示，在形成焊錫凸塊520之後，進行一切割製程，沿著晶圓切割道形成切割溝槽602，其貫穿防銲層312、RDL中介層400，並稍微延伸進入到第一成型模料500。上述切割溝槽602不會貫穿第一成型模料500的整個厚度。此時，RDL中介層400的垂直側壁400a在切割溝槽602中被顯露出來。根據本發明實施例，切割溝槽602可以利用切割刀或雷射形成，但不限於此。
如第19圖所示，在形成切割溝槽602之後，接著於切割溝槽602中填入一第二成型模料600，使第二成型模料600包封住焊錫凸塊520。第二成型模料600同時覆蓋防銲層312的上表面312a。先前顯露出來的RDL中介層400的垂直側壁400a此時被第二成型模料600所覆蓋。同樣的，第二成型模料600可藉由一固化製程使之固化。根據本發明實施例，第二成型模料600例如為環氧樹脂與二氧化矽填充劑的混和物，但並不限於此。
根據本發明實施例，第二成型模料600與第一成型模料500可以具有不同的組成。例如，上述不同組成使得第二成型模料600可以在不影響到第一成型模料500結構完整性及先前形成在RDL中介層400上的元件的溫度下完成固化。
如第20圖所示，繼續進行一研磨製程或一拋光製程，例如化學機械研磨（CMP）製程，以去除第二成型模料600的上部，直到防銲層520顯露出來。根據本發明實施例，在上述研磨或拋光製程中，焊錫凸塊520的部分上部也可能被去除。此時，焊錫凸塊520的上表面可以與第二成型模料600的上表面齊平。
如第21圖所示，接著在焊錫凸塊520的顯露出的表面形成凸塊522，用於進一步連結，此時，凸塊522突出於第二成型模料600的上表面。根據本發明實施例，凸塊522可以利用習知方法形成，例如電鍍或網版印刷等，但不限於此。
如第22圖所示，進行一晶圓切割製程，將個別的半導體封裝10彼此分離。本發明的主要特徵之一在於具有雙側模封結構，包括第一成型模料500及第二成型模料600，包封住RDL中介層400。第一成型模料500係直接接觸到第二成型模料600。本發明另一結構特徵在於第二成型模料600係直接接觸到焊錫凸塊520以及RDL中介層400的垂直側壁400a。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧半導體封裝
300‧‧‧載板
301‧‧‧黏著層
310‧‧‧鈍化層
312‧‧‧防銲層
312a‧‧‧上表面
314‧‧‧開孔
400‧‧‧RDL中介層
400a‧‧‧垂直側壁
410‧‧‧重佈線層（RDL）
412‧‧‧介電層
414‧‧‧金屬層
415‧‧‧凸塊墊
416‧‧‧凸塊
417‧‧‧錫球焊墊
421‧‧‧接觸點
420a、420b‧‧‧晶粒（晶片）
500‧‧‧第一成型模料
510‧‧‧鈍化層
520‧‧‧焊錫凸塊
522‧‧‧凸塊
602‧‧‧切割溝槽
600‧‧‧第二成型模料
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。其中： 第1圖至第12圖為根據本發明實施例所繪示的示意性剖面圖，例示製作具有雙側模封結構的半導體封裝的方法，其中所述雙側模封結構包封RDL中介層；以及 第13圖至第22圖為根據本發明另一實施例所繪示的示意性剖面圖，例示以雙側模封結構包封RDL中介層的半導體封裝的製作方法。

Claims (8)

  1. 一種半導體封裝，包含：一重佈線層(RDL)中介層，其具有一第一面、相對於該第一面的一第二面，及延伸於該第一面與該第二面之間的一垂直側壁；至少一半導體晶粒，其設於該RDL中介層的該第一面上；一第一成型模料，設於該第一面上，該第一成型模料包覆該至少一半導體晶粒；複數個焊錫凸塊，其設於該第二面上；以及一第二成型模料，其設於該第二面上，該第二成型模料包圍該複數個焊錫凸塊，且覆蓋該RDL中介層的該垂直側壁，其中該第一成型模料與該第二成型模料具有不同的組成，其中該第二成型模料包含一外圍部分(peripheral portion)，其延伸至該第一成型模料並夾鉗(clamp)該第一成型模料。
  2. 如申請專利範圍第1項所述的半導體封裝，其中該第一成型模料係直接接觸該第二成型模料。
  3. 如申請專利範圍第1項所述的半導體封裝，其進一步包含多個凸塊，其各自設於該複數個焊錫凸塊上，使得該等凸塊自該第二成型模料的一上表面突出。
  4. 如申請專利範圍第1項所述的半導體封裝，其中該RDL中介層包含一重佈線層，其包含至少一介電層及至少一金屬層。
  5. 如申請專利範圍第4項所述的半導體封裝，其中該介電層包含聚亞醯胺、氮化矽或氧化矽。
  6. 如申請專利範圍第4項所述的半導體封裝，其中該金屬層包含鋁、銅、鎢、鈦或氮化鈦。
  7. 如申請專利範圍第4項所述的半導體封裝，其中該RDL中介層進一步包含一鈍化層，其設於該介電層上。
  8. 如申請專利範圍第1項所述的半導體封裝，其中該第一成型模料係自該半導體晶粒的一上部磨除掉，以顯露出該半導體晶粒的一上表面。
TW105110831A 2016-03-03 2016-04-07 具有雙側模封結構的半導體封裝 TWI651816B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/060,577 US9613895B1 (en) 2016-03-03 2016-03-03 Semiconductor package with double side molding
US15/060,577 2016-03-03

Publications (2)

Publication Number Publication Date
TW201733040A TW201733040A (zh) 2017-09-16
TWI651816B true TWI651816B (zh) 2019-02-21

Family

ID=58419549

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105110831A TWI651816B (zh) 2016-03-03 2016-04-07 具有雙側模封結構的半導體封裝

Country Status (3)

Country Link
US (1) US9613895B1 (zh)
CN (1) CN107154391B (zh)
TW (1) TWI651816B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10522505B2 (en) 2017-04-06 2019-12-31 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method for manufacturing the same
US11244918B2 (en) * 2017-08-17 2022-02-08 Semiconductor Components Industries, Llc Molded semiconductor package and related methods
CN109962038A (zh) * 2017-12-26 2019-07-02 财团法人工业技术研究院 封装结构及其形成方法
CN112908948A (zh) * 2021-01-18 2021-06-04 上海先方半导体有限公司 一种封装结构及其制造方法
CN113078148B (zh) * 2021-03-12 2024-03-26 上海易卜半导体有限公司 半导体封装结构、方法、器件和电子产品

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140077364A1 (en) * 2012-09-14 2014-03-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Wire Studs as Vertical Interconnect in FO-WLP

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7268012B2 (en) * 2004-08-31 2007-09-11 Micron Technology, Inc. Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
JP2009010327A (ja) * 2007-06-01 2009-01-15 Panasonic Corp 半導体装置およびその製造方法
US8643148B2 (en) * 2011-11-30 2014-02-04 Taiwan Semiconductor Manufacturing Company, Ltd. Chip-on-Wafer structures and methods for forming the same
CN202443962U (zh) * 2011-12-27 2012-09-19 日月光半导体制造股份有限公司 晶圆级半导体封装构造
IL223414A (en) * 2012-12-04 2017-07-31 Elta Systems Ltd Integrated electronic device and method for creating it
US9018045B2 (en) * 2013-07-15 2015-04-28 Freescale Semiconductor Inc. Microelectronic packages and methods for the fabrication thereof

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140077364A1 (en) * 2012-09-14 2014-03-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Wire Studs as Vertical Interconnect in FO-WLP

Also Published As

Publication number Publication date
TW201733040A (zh) 2017-09-16
CN107154391A (zh) 2017-09-12
CN107154391B (zh) 2018-11-02
US9613895B1 (en) 2017-04-04

Similar Documents

Publication Publication Date Title
US11710693B2 (en) Wafer level package utilizing molded interposer
TWI587471B (zh) 具有側壁保護重佈線層中介層的半導體封裝及其製作方法
US10446509B2 (en) Methods of forming and operating microelectronic devices including dummy chips
US11069656B2 (en) Three-layer package-on-package structure and method forming same
US9437583B1 (en) Package-on-package assembly and method for manufacturing the same
US9786586B1 (en) Semiconductor package and fabrication method thereof
TWI578481B (zh) 封裝上封裝構件及其製作方法
TWI596681B (zh) 半導體封裝及其製作方法
US9761540B2 (en) Wafer level package and fabrication method thereof
US11764165B2 (en) Supporting InFO packages to reduce warpage
TWI594337B (zh) 製作封裝上封裝構件的方法
TWI651816B (zh) 具有雙側模封結構的半導體封裝
TWI571942B (zh) 晶圓級封裝的製作方法
TWI571985B (zh) 扇出晶圓級封裝及其製作方法
KR20200138636A (ko) Cowos 구조물 및 이의 형성 방법
TWI807618B (zh) 封裝結構及其製造方法
TWI600093B (zh) 製作晶圓級封裝的方法
TW202310265A (zh) 封裝結構及其製造方法