TWI600093B - 製作晶圓級封裝的方法 - Google Patents

製作晶圓級封裝的方法 Download PDF

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TWI600093B
TWI600093B TW105108909A TW105108909A TWI600093B TW I600093 B TWI600093 B TW I600093B TW 105108909 A TW105108909 A TW 105108909A TW 105108909 A TW105108909 A TW 105108909A TW I600093 B TWI600093 B TW I600093B
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layer
redistribution layer
wafer
wafer level
fabricating
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TW105108909A
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TW201730988A (zh
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施信益
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美光科技公司
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Description

製作晶圓級封裝的方法
本發明涉及半導體封裝技術領域。更具體而言，本發明係有關於一種製作晶圓級封裝（wafer level package，WLP）的方法。
半導體技術發展非常快，尤其在半導體晶片朝向微型化發展的趨勢下，對於半導體晶片的功能則越要求更多樣性。這也就是說，半導體晶片上勢必會有更多的輸出/輸入（I/O）墊被擠在一個更小的區域，因此，半導體晶片上的接合墊密度迅速提高。它會導致半導體晶片的封裝變得更加困難。
如本領域中公知的，晶圓級封裝（WLP）係在將晶粒切割分離之前先進行封裝。晶圓級封裝技術具有一定的優勢，如更短的生產週期時間和較低的成本。扇出晶圓級封裝（FOWLP）則是將半導體晶片的接觸墊通過基板上的重佈線層（RDL）再分配到一較大的面積上的封裝技術。重佈線層（RDL）通常形成在一基板上，例如TSV中介層基板。
重佈線層通常由額外的金屬層及介電層所構成，其形成在晶圓表面，將晶片的I/O墊重新繞線成間距較寬鬆的佈局圖案。上述重分佈通常利用薄膜聚合物，例如，苯並環丁烯（BCB）、聚亞醯胺（PI）或其它有機聚合物，以及金屬化製程，例如，鋁金屬或銅金屬，如此將接合墊重繞線至一面積陣列組態。
在常規的晶圓級封裝製程，通常需要進行兩次或三次的臨時載板接合製程，以方便晶圓處理。這些載板在處理晶圓時提供了模封晶圓足夠的機械支持。
本發明的主要目的在提供一種改良的方法，以製作出晶圓級封裝（WLP），可以省去臨時載板接合步驟。
根據本發明一實施例，一種製作晶圓級封裝的方法，包含：提供一載板；於該載板上形成一重佈線層；於該重佈線層上設置半導體晶粒；將該半導體晶粒模封在一成型模料中，如此構成一模封晶圓；進行一研磨製程，磨除該成型模料的一中央部分，如此形成一凹陷區域以及一外圍週邊環形部分，環繞該凹陷區域；去除該載板，顯露出該重佈線層的一底面；以及於該重佈線層的該底面上形成凸塊或錫球。
無庸置疑的，該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後，均可了解本發明的目的。
接下來的詳細敘述係參照相關圖式所示內容，用來說明可依據本發明具體實行的實施例。這些實施例已提供足夠的細節，可使本領域技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，仍可做結構上的修改，並應用在其他實施例上。
因此，接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求界定。與本發明權利要求具均等意義者，也應屬本發明涵蓋的範圍。
本發明實施例所參照的附圖為示意圖，並未按原比例繪製，且相同或類似的特徵通常以相同的附圖標記描述。在本說明書中，“晶粒”、“半導體晶片”與“半導體晶粒”具相同含意，可交替使用。
在本說明書中，“晶圓”與“基板”意指任何包含一暴露面，可依據本發明實施例所示在其上沉積材料，製作積體電路結構的結構物，例如重佈線層（RDL）。須了解的是“基板”包含半導體晶圓，但並不限於此。"基板"在製程中也意指包含製作於其上的材料層的半導體結構物。
請參閱第1圖至第10圖。第1圖至第10圖為根據本發明實施例所繪示的示意性剖面圖，例示製作一晶圓級封裝的方法。如第1圖所示，首先提供一載板300。載板300可以是可卸式晶圓狀基板，可以包含一黏著層(圖未示)。例如，載板300可以是玻璃基板，但不限於此。
如第2圖所示，接著在載板300上形成一重佈線層(RDL)410。重佈線層410包含至少一介電層412與至少一金屬層414。介電層412可包含有機材料，例如，聚亞醯胺(polyimide, PI)，或者無機材料，例如氮化矽、氧化矽等，但不限於此。金屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似的材料。雖然圖中未繪示出來，但應理解在重佈線層410與載板300之間可以另有一鈍化層，例如聚亞醯胺(PI)或氧化矽等。
接著，在重佈線層410上形成複數個凸塊416，例如，微凸塊，用以進一步連結。凸塊416可以分別直接形成在金屬層414的凸塊墊414b上。所述形成凸塊416的方法為周知技藝，故其細節不另贅述。
如第3圖所示，形成凸塊416之後，個別的覆晶晶片或晶粒420以主動面朝下面對重佈線層410的方式，藉由凸塊416安裝至重佈線層410上，形成“晶片對晶圓接合”(C2W)的層疊結構。這些個別的覆晶晶片或晶粒420為具有特定功能的主動積體電路晶片，例如繪圖處理器(GPU)、中央處理器(CPU)、記憶體晶片等等。上述步驟完成後，可選擇性地在每一晶片或晶粒420下方填充底膠（圖未示）。隨後，可進行熱處理，使凸塊416迴焊。
如第4圖所示，晶粒接合完成後，接著在上方覆蓋一成型模料500。成型模料500覆蓋住安裝好的晶片420與重佈線層410的頂面，構成一模封晶圓4。成型模料500隨後可藉由一固化製程使之固化。成型模料500例如為環氧樹脂與二氧化矽填充劑的混和物，但並不限於此。
如第5圖所示，進行一研磨製程，將部分的成型模料500從載板300上的一中央區域去除。研磨製程之後，留下邊緣較厚且具有預定寬度的一外圍週邊環形部分502，薄化中央區域的成型模料500後，原處形成一凹陷區域501。應理解的是，在研磨製程過程中，各個晶粒420的一上部可能會被移除，顯露出各個晶粒420的上表面。
如第6圖所示，在完成研磨製程之後，去除載板300。由於外圍週邊環形部分502已能夠對模封晶圓4提供足夠的機械支撐力，故在去除載板300之前，不需要進行另一臨時載板接合製程。上述去除載板300可以利用雷射製程或紫外線（UV）照射製程，但不限於此。在去除載板300之後，重佈線層410的底面被顯露出來。
如第7圖所示，接著於重佈線層410顯露出來的底面上形成一防銲層510。再於防銲層510中形成開孔510a，分別顯露出位於重佈線層410內的錫球焊墊414a。接著在錫球焊墊414a上分別形成凸塊或錫球520，如第8圖所示。應理解的是，在其它實施例中，凸塊或錫球520下方可以先形成一凸塊下金屬（under-bump metallurgy，UBM）。
如第9圖所示，接著進行一切割製程，沿著凹陷區域501的週邊切穿成型模料500、重佈線層410以及防銲層510，如此將外圍週邊環形部分502從模封晶圓4上分離出來。
最後，如第10圖所示，進行晶圓切割製程，如此分隔出個別的晶圓級封裝10。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
4 模封晶圓 300 載板 410重佈線層(RDL) 412 介電層 414 金屬層 414a 錫球焊墊 414b 凸塊墊 416 凸塊 420 覆晶晶片或晶粒 500 成型模料 501 凹陷區域 502 外圍週邊環形部分 510 防銲層 510a 開孔 520 凸塊或錫球
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。其中：         第1圖至第10圖為根據本發明實施例所繪示的示意性剖面圖，例示製作一晶圓級封裝的方法。
4 模封晶圓 410重佈線層(RDL) 412 介電層 414 金屬層 414a 錫球焊墊 414b 凸塊墊 416 凸塊 420 覆晶晶片或晶粒 500 成型模料 502 外圍週邊環形部分 510 防銲層 520 凸塊或錫球

Claims (5)

  1. 一種製作晶圓級封裝的方法，包含：提供一載板；於該載板上形成一重佈線層；於該重佈線層上設置半導體晶粒；將該半導體晶粒模封在一成型模料中，如此構成一模封晶圓；進行一研磨製程，磨除該成型模料的一中央部分，如此形成一凹陷區域以及一外圍週邊環形部分，環繞該凹陷區域；去除該載板，顯露出該重佈線層的一底面；於該重佈線層的該底面上形成凸塊或錫球；進行一切割製程，將該外圍週邊環形部分從該模封晶圓上分離出來；以及進行一晶圓切割製程，分離出個別的晶圓級封裝。
  2. 如申請專利範圍第1項所述的製作晶圓級封裝的方法，其中在移除該載板之後，該方法另包含有：於該重佈線層的該底面上形成一防銲層；以及於該防銲層中形成開孔，分別顯露出位於該重佈線層內的錫球焊墊。
  3. 如申請專利範圍第2項所述的製作晶圓級封裝的方法，其中該凸塊或錫球係分別形成在該錫球焊墊上。
  4. 如申請專利範圍第1項所述的製作晶圓級封裝的方法，其中在將半導體晶粒設置於該重佈線層上之前，該方法另包含有：於該重佈線層上形成複數個凸塊。
  5. 如申請專利範圍第1項所述的製作晶圓級封裝的方法，其中該重佈線層包含至少一介電層以及至少一金屬層。
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