TWI596681B - 半導體封裝及其製作方法 - Google Patents

半導體封裝及其製作方法 Download PDF

Info

Publication number
TWI596681B
TWI596681B TW105115248A TW105115248A TWI596681B TW I596681 B TWI596681 B TW I596681B TW 105115248 A TW105115248 A TW 105115248A TW 105115248 A TW105115248 A TW 105115248A TW I596681 B TWI596681 B TW I596681B
Authority
TW
Taiwan
Prior art keywords
layer
semiconductor package
passivation layer
fabricating
solder
Prior art date
Application number
TW105115248A
Other languages
English (en)
Other versions
TW201732970A (zh
Inventor
吳鐵將
施信益
Original Assignee
美光科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美光科技公司 filed Critical 美光科技公司
Application granted granted Critical
Publication of TWI596681B publication Critical patent/TWI596681B/zh
Publication of TW201732970A publication Critical patent/TW201732970A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H01L2021/60225—Arrangement of bump connectors prior to mounting
    • H01L2021/60255—Arrangement of bump connectors prior to mounting wherein the bump connectors are provided as prepeg, e.g. are provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

半導體封裝及其製作方法
本發明係有關於半導體封裝技術領域，特別是有關於一種晶圓級封裝及其製作方法。
半導體技術發展的非常快速，尤其在半導體晶片朝向微型化發展的趨勢下，對於半導體晶片的功能則越要求更多樣性。也就是說，半導體晶片上勢必會有更多的輸出/輸入（I/O）墊被擠在一個更小的區域，這使得半導體晶片上接合墊的密度迅速增加，導致半導體晶片的封裝變得更加困難。
如本領域中公知的，晶圓級封裝（WLP）係在將晶粒切割分離之前先進行晶圓層級封裝。晶圓級封裝技術具有一定的優勢，如更短的生產週期時間和較低的成本。扇出晶圓級封裝（FOWLP）則是將半導體晶片的接觸墊通過基板上的重佈線層（RDL）再分配到一較大的面積上的封裝技術。重佈線層（RDL）通常形成在一基板上，例如穿矽通孔（TSV）中介基板。
重佈線層通常由額外的金屬層及介電層所構成，其形成在晶圓表面，將晶片的I/O墊重新繞線成間距較寬鬆的佈局圖案。上述重分佈通常利用薄膜聚合物，例如，苯並環丁烯（BCB）、聚亞醯胺（PI）或其它有機聚合物，以及金屬化製程，例如，鋁金屬或銅金屬，如此將接合墊重繞線至一面積陣列組態。
晶圓級封裝製程中，通常會在晶圓及安裝在晶圓上的晶片表面覆蓋一相對較厚的成型模料。目前的晶圓級封裝製程中，會在成型模封後，再進行熱固化製程。然而，此熱固化製程會造成合格晶片減損（known-good-die loss）的風險增加。
本發明主要目的在提供一種改良的半導體封裝及其製作方法，以解決上述先前技藝的不足與缺點。
根據本發明一實施例，提供一種半導體封裝，包含有一重佈線層(RDL)中介層，具有一第一面及一第二面，該第二面相對於該第一面，其中該RDL中介層包含一第一鈍化層、至少一介電層，位於該第一鈍化層上、一金屬層，位於該介電層中、一第二鈍化層，位於該介電層上，以及複數個焊球墊，位於該第一鈍化層中；至少一半導體晶粒，安裝在該RDL中介層的該第一面上；一成型模料，在該RDL中介層的該第一面上，圍繞該至少一半導體晶粒；一防焊層，覆蓋該第一鈍化層的一下表面，並經由位於該防銲層中的複數個開孔顯露出該複數個焊球墊；一凸塊下金屬(UBM)層，設於各該複數個開孔的底部；以及一焊錫凸塊或錫球，設於各該複數個開孔的底部的該UBM層上。
根據本發明另一實施例，提供一種製作半導體封裝的方法，包含有：提供一載板，其上具有一金屬層；於該金屬層上形成一第一鈍化層；形成一重佈線層於該第一鈍化層上與複數個焊球墊於該第一鈍化層內；於該重佈線層上形成一第二鈍化層；於該第二鈍化層上設置至少一半導體晶粒；將該半導體晶粒模封在一成型模料中；去除該載板，顯露出該金屬層的一下表面；圖案化該金屬層，形成一凸塊下金屬(UBM)層；於該第一鈍化層上形成一防焊層；以及於該焊球墊上形成複數個焊錫凸塊或錫球。
以下詳細敘述係參照相關圖式所示內容，用來說明可依據本發明具體實行的實施例。這些實施例已提供足夠的細節，可使本領域技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，仍可做結構上的修改，並應用在其他實施例上。
因此，接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求界定。與本發明權利要求具均等意義者，也應屬本發明涵蓋的範圍。
本發明實施例所參照的附圖為示意圖，並未按原比例繪製，且相同或類似的特徵通常以相同的附圖標記描述。在本說明書中，“晶粒”、“半導體晶片”與“半導體晶粒”具相同含意，可交替使用。
在本說明書中，“晶圓”與“基板”意指任何包含一暴露面，可依據本發明實施例所示在其上沉積材料，製作積體電路結構的結構物，例如重佈線層（RDL）。須了解的是“基板”包含半導體晶圓，但並不限於此。"基板"在製程中也意指包含製作於其上的材料層的半導體結構物。
請參閱第1圖至第11圖。第1圖至第11圖為根據本發明實施例所繪示製作半導體封裝的方法示意性剖面圖。
如第1圖所示，首先提供一載板300。載板300可以是可卸除的晶圓狀基板，可以包含一黏著層（圖未示）。例如，載板300可以是一玻璃基板，但不限於此。在載板300的上表面形成有一金屬層302。金屬層302可以包含一凸塊下金屬（under-bump metallurgy，UBM）材料或一金屬合金層，包括，但不限於，鎳、金、銅等。金屬層302可以利用黏著層（圖未示）以黏貼方式形成在載板300的上表面，或者，在某些實施例中，可以直接塗佈在載板300的上表面，而不使用黏著層。
如第2圖所示，接著在載板300的上表面形成至少一介電層或一鈍化層310。鈍化層310可以包含有機材料，例如，聚醯亞胺（polyimide，PI），或者無機材料，例如，氮化矽、氧化矽等。
接著，如第3圖所示，在鈍化層310上形成一重佈線層（RDL）410。重佈線層410包含至少一介電層412與至少一金屬層414。介電層412可包含有機材料，例如，聚亞醯胺，或者無機材料，例如氮化矽、氧化矽等，但不限於此。金屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似的材料。
根據本發明實施例，金屬層414可以包含複數個焊球墊414a（例如，銅墊），設置在鈍化層310內。在重佈線層410上形成有另一鈍化層（或一介電層）510。鈍化層510可以包含有機材料，例如，聚醯亞胺或者無機材料，例如，氮化矽、氧化矽等。應理解的是，鈍化層510可以包含一防銲層，但不限於此。
如第4圖所示，在重佈線層410上及鈍化層510中形成複數個凸塊416，例如，微凸塊，用以進一步連結。凸塊416可以分別直接形成在金屬層414的凸塊墊414b上。所述形成凸塊416的方法為周知技藝，不另贅述。以下，將鈍化層310、重佈線層410及鈍化層510所構成的結構稱為RDL中介層400。
形成凸塊416之後，個別的覆晶晶片或晶粒420a及420b以主動面朝下面對RDL中介層400的方式，藉由凸塊416安裝至RDL中介層400上，形成“晶片對晶圓接合”(C2W)的層疊結構。這些個別的覆晶晶片或晶粒420a及420b為具有特定功能的主動積體電路晶片，例如繪圖處理器(GPU)、中央處理器(CPU)、記憶體晶片等等。根據本發明實施例，晶粒420a及420b可以在同一封裝內，而為具有不同特定功能的半導體晶粒。上述步驟完成後，可選擇性地在每一晶粒420a及420b下方填充底膠（圖未示）。隨後，可進行熱處理，使凸塊416回焊。
如第5圖所示，完成晶粒接合後，接著在RDL中介層400上覆蓋一成型模料500。成型模料500覆蓋住安裝好的晶粒420a及420b與鈍化層510的頂面。隨後，成型模料500可藉由一固化製程使之固化。根據本發明實施例，成型模料500例如為環氧樹脂與二氧化矽填充劑的混和物，但並不限於此。接著，可選擇將成型模料500上部磨除。
如第6圖所示，在形成成型模料500之後，去除載板300，以顯露出金屬層302的一下表面。上述去除載板300可以利用雷射製程或紫外線（UV）照射製程，但不限於此。
如第7圖所示，在去除載板300之後，進行一微影製程，於顯露出的金屬層302的下表面形成一光阻層210。光阻層210包括複數個接墊圖案210a，分別對準焊球墊414a。
如第8圖所示，進行一蝕刻製程，蝕刻未被接墊圖案210a覆蓋的金屬層302，如此在各焊球墊414a上形成一凸塊下金屬（UBM）層302a。
如第9圖所示，在各焊球墊414a上形成UBM層302a之後，接著於UBM層302a及顯露出的鈍化層310下表面形成一防焊層610。接著，進行一微影製程，於防焊層610中形成開孔610a，顯露出UBM層302a。
如第10圖所示，形成防焊層610及防焊層610中的開孔610a之後，分別於焊球墊414a上形成焊錫凸塊或錫球520。各焊錫凸塊或錫球520係直接接觸UBM層302a。
如第11圖所示，進行一晶圓切割製程，將個別的半導體封裝10彼此分離。需理解的是，在圖中雖顯示有兩個晶粒，但在其它實施例中，各半導體封裝10中也可以只包括單一晶粒。
本發明半導體封裝10的結構上特徵在於UBM層302a不會向上垂直延伸至開孔610a的側壁上。此外，焊球墊414a係在半導體封裝製程的前段即預先形成在鈍化層310中。
本發明的優點在於成型模料500係在UBM層302a及焊錫凸塊或錫球520完成之後才形成，因此，可以明顯降低合格晶片減損（known-good-die loss）的風險。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧半導體封裝
210‧‧‧光阻層
210a‧‧‧接墊圖案
300‧‧‧載板
302‧‧‧金屬層
302a‧‧‧凸塊下金屬（UBM）層
310‧‧‧鈍化層
400‧‧‧RDL中介層
410‧‧‧重佈線層（RDL）
412‧‧‧介電層
414‧‧‧金屬層
414a‧‧‧焊球墊
414b‧‧‧凸塊墊
416‧‧‧凸塊
420a、420b‧‧‧晶粒
500‧‧‧成型模料
510‧‧‧鈍化層
520‧‧‧焊錫凸塊或錫球
610‧‧‧防焊層
610a‧‧‧開孔
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。其中：   第1圖至第11圖為根據本發明實施例所繪示製作半導體封裝的方法示意性剖面圖。
10‧‧‧半導體封裝
302a‧‧‧凸塊下金屬(UBM)層
310‧‧‧鈍化層
400‧‧‧RDL中介層
410‧‧‧重佈線層(RDL)
412‧‧‧介電層
414‧‧‧金屬層
414a‧‧‧焊球墊
414b‧‧‧凸塊墊
416‧‧‧凸塊
420a、420b‧‧‧晶粒
500‧‧‧成型模料
510‧‧‧鈍化層
520‧‧‧焊錫凸塊或錫球
610‧‧‧防焊層
610a‧‧‧開孔

Claims (9)

  1. 一種製作半導體封裝的方法，包含有：提供一載板，其上具有一金屬層；於該金屬層上形成一第一鈍化層；形成一重佈線層於該第一鈍化層上與複數個焊球墊於該第一鈍化層內；於該重佈線層上形成一第二鈍化層；於該第二鈍化層上設置至少一半導體晶粒；將該半導體晶粒模封在一成型模料中；去除該載板，顯露出該金屬層的一下表面；圖案化該金屬層，形成一凸塊下金屬(UBM)層；於該第一鈍化層上形成一防焊層；以及於該焊球墊上形成複數個焊錫凸塊或錫球。
  2. 如申請專利範圍第1項所述的製作半導體封裝的方法，其中於該重佈線層上形成該第二鈍化層之後，另包含有：於該第二鈍化層中形成複數個凸塊，其中該半導體晶粒係經由該複數個凸塊電連接該重佈線層。
  3. 如申請專利範圍第1項所述的製作半導體封裝的方法，其中防焊層包含複數個開孔，其中各該開孔顯露出該UBM層。
  4. 如申請專利範圍第3項所述的製作半導體封裝的方法，其中各該焊錫凸塊或錫球係直接接觸該UBM層。
  5. 如申請專利範圍第4項所述的製作半導體封裝的方法，其中該UBM層僅形成在各該開孔的底面上。
  6. 如申請專利範圍第4項所述的製作半導體封裝的方法，其中該UBM層不向上延伸至各該開孔的垂直側壁上。
  7. 如申請專利範圍第1項所述的製作半導體封裝的方法，其中該UBM層包含鎳、金或銅。
  8. 如申請專利範圍第1項所述的製作半導體封裝的方法，其中該第一鈍化層包含聚醯亞胺、氮化矽或氧化矽。
  9. 如申請專利範圍第1項所述的製作半導體封裝的方法，其中該第二鈍化層包含聚醯亞胺、氮化矽或氧化矽。
TW105115248A 2016-03-14 2016-05-18 半導體封裝及其製作方法 TWI596681B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US15/069,911 US9704790B1 (en) 2016-03-14 2016-03-14 Method of fabricating a wafer level package

Publications (2)

Publication Number Publication Date
TWI596681B true TWI596681B (zh) 2017-08-21
TW201732970A TW201732970A (zh) 2017-09-16

Family

ID=59257575

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105115248A TWI596681B (zh) 2016-03-14 2016-05-18 半導體封裝及其製作方法

Country Status (3)

Country Link
US (1) US9704790B1 (zh)
CN (1) CN107195593A (zh)
TW (1) TWI596681B (zh)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102039710B1 (ko) * 2017-10-19 2019-11-01 삼성전자주식회사 유기 인터포저를 포함하는 반도체 패키지
CN107768344B (zh) * 2017-10-26 2019-01-11 长鑫存储技术有限公司 半导体封装系统整合装置及其制造方法
KR101901712B1 (ko) * 2017-10-27 2018-09-27 삼성전기 주식회사 팬-아웃 반도체 패키지
US10861814B2 (en) * 2017-11-02 2020-12-08 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated fan-out packages and methods of forming the same
US10535608B1 (en) 2018-07-24 2020-01-14 International Business Machines Corporation Multi-chip package structure having chip interconnection bridge which provides power connections between chip and package substrate
TWI659515B (zh) * 2018-07-26 2019-05-11 欣興電子股份有限公司 封裝結構及其製造方法
KR102450570B1 (ko) 2018-10-02 2022-10-07 삼성전자주식회사 반도체 패키지
KR102179167B1 (ko) * 2018-11-13 2020-11-16 삼성전자주식회사 반도체 패키지
KR102530322B1 (ko) 2018-12-18 2023-05-10 삼성전자주식회사 반도체 패키지
CN113228268B (zh) * 2018-12-29 2023-09-29 华为技术有限公司 芯片封装结构、电子设备、芯片封装方法以及封装设备
US11164817B2 (en) 2019-11-01 2021-11-02 International Business Machines Corporation Multi-chip package structures with discrete redistribution layers
US11094637B2 (en) 2019-11-06 2021-08-17 International Business Machines Corporation Multi-chip package structures having embedded chip interconnect bridges and fan-out redistribution layers

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
TW200917441A (en) * 2007-10-15 2009-04-16 Advanced Chip Eng Tech Inc Inter-connecting structure for semiconductor package and method of the same
US20130087909A1 (en) * 2011-10-10 2013-04-11 Texas Instruments Incorporated Semiconductor device having improved contact structure
TW201533862A (zh) * 2014-02-13 2015-09-01 Taiwan Semiconductor Mfg Co Ltd 封裝的半導體元件、層疊封裝元件以及封裝半導體元件的方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9460951B2 (en) * 2007-12-03 2016-10-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of wafer level package integration
US10074553B2 (en) * 2007-12-03 2018-09-11 STATS ChipPAC Pte. Ltd. Wafer level package integration and method
US8320134B2 (en) * 2010-02-05 2012-11-27 Advanced Semiconductor Engineering, Inc. Embedded component substrate and manufacturing methods thereof
US10043769B2 (en) * 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
US20160365334A1 (en) * 2015-06-09 2016-12-15 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same
US9520333B1 (en) * 2015-06-22 2016-12-13 Inotera Memories, Inc. Wafer level package and fabrication method thereof
US9449935B1 (en) * 2015-07-27 2016-09-20 Inotera Memories, Inc. Wafer level package and fabrication method thereof
US9449953B1 (en) * 2015-10-08 2016-09-20 Inotera Memories, Inc. Package-on-package assembly and method for manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271469B1 (en) * 1999-11-12 2001-08-07 Intel Corporation Direct build-up layer on an encapsulated die package
TW200917441A (en) * 2007-10-15 2009-04-16 Advanced Chip Eng Tech Inc Inter-connecting structure for semiconductor package and method of the same
US20130087909A1 (en) * 2011-10-10 2013-04-11 Texas Instruments Incorporated Semiconductor device having improved contact structure
TW201533862A (zh) * 2014-02-13 2015-09-01 Taiwan Semiconductor Mfg Co Ltd 封裝的半導體元件、層疊封裝元件以及封裝半導體元件的方法

Also Published As

Publication number Publication date
TW201732970A (zh) 2017-09-16
US9704790B1 (en) 2017-07-11
CN107195593A (zh) 2017-09-22

Similar Documents

Publication Publication Date Title
TWI596681B (zh) 半導體封裝及其製作方法
US11710693B2 (en) Wafer level package utilizing molded interposer
US10964667B2 (en) Stacked integrated circuit structure and method of forming
TWI587471B (zh) 具有側壁保護重佈線層中介層的半導體封裝及其製作方法
US10026680B2 (en) Semiconductor package and fabrication method thereof
TWI616957B (zh) 晶圓級封裝及其製作方法
TWI578481B (zh) 封裝上封裝構件及其製作方法
TWI616980B (zh) 堆疊封裝構件及其製作方法
TWI741538B (zh) 半導體元件及其形成方法
KR102170575B1 (ko) 휨 감소를 위한 인포 패키지 지지
TWI594337B (zh) 製作封裝上封裝構件的方法
TWI674655B (zh) 封裝及其形成方法
TWI571942B (zh) 晶圓級封裝的製作方法
TWI651816B (zh) 具有雙側模封結構的半導體封裝
KR20210040341A (ko) Info 구조물 및 그 형성 방법
TWI600093B (zh) 製作晶圓級封裝的方法
TWI840689B (zh) 金屬化結構及封裝結構
US20240234340A1 (en) Integrated circuit packages and methods