TWI578481B - 封裝上封裝構件及其製作方法 - Google Patents

封裝上封裝構件及其製作方法 Download PDF

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Publication number
TWI578481B
TWI578481B TW104140518A TW104140518A TWI578481B TW I578481 B TWI578481 B TW I578481B TW 104140518 A TW104140518 A TW 104140518A TW 104140518 A TW104140518 A TW 104140518A TW I578481 B TWI578481 B TW I578481B
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Taiwan
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package
conductive
wafer
conductive plug
layer
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TW104140518A
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TW201714267A (zh
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施信益
施能泰
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美光科技公司
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Publication of TW201714267A publication Critical patent/TW201714267A/zh

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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Description

封裝上封裝構件及其製作方法
本發明係有關於半導體封裝技術領域，特別是有關於一種封裝上封裝(Package-on-Package, PoP)構件及其製作方法。
隨著半導體製造技術近來的進步，微電子組件變得更小，而這些組件內的電路變得越來越密集。為了使微電子組件的尺寸變得更小，微電子組件中的各個元件的封裝及組裝必須變得更加緊密。
為了滿足更小的空間與更高密度的要求，業界目前已發展出3D堆疊封裝，如封裝上封裝構件。通常，封裝上封裝構件包括一上封裝，其包含一半導體晶片，接合到一個下封裝，該下封裝通常包含另一晶片。在封裝上封裝設計中，上封裝可通過週邊焊球或貫模通孔與下封裝互連。
然而，現有的封裝上封裝技術還不能提供非常緊密間距的堆疊。此外，現有的封裝上封裝技術的外形因子(form factor)偏高並且有翹曲控制問題。因此，該技術領域仍需要一種薄且具有微細間距的封裝上封裝構件及製作方法。
本發明的主要目的在提供一半導體裝置，其具有封裝上封裝之組態。
本發明披露一種封裝上封裝構件，包含有一下晶片封裝，包含有：一中介層，其具有一第一面以及相對該第一面的一第二面；至少一晶片，經由複數個凸塊安置於該第一面的一晶片安裝區域內；一成型模料，設於該第一面，鄰近該至少一晶片；複數個週邊凸塊結構，位於一週邊區域內，且貫穿該成型模料，其中各該週邊凸塊結構包含一埋入在該成型模料內的導電柱體以及一直接堆疊在該導電柱體的部分穿模導孔；複數個錫球，設置於該第二面上；及一上晶片封裝，設置於該下晶片封裝之上，連接該複數個週邊凸塊結構。其中該導電柱體與該部分穿模導孔之間具有一底切結構。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
在以下詳細描述中，請參考附圖，這些附圖構成本揭露書的一部分，其用來輔助說明並例示本發明具體實施方案。這些實施方案被詳細地描述以使本領域的技術人員能夠實踐本發明。當然，其他實施例也可以被利用，且在不脫離本發明的範圍下，可以做出結構上的變化。
因此，以下的詳細描述，不應被視為具有限制意義，並且本發明的範圍應由所附權利要求書所定義，其發明內容應同時考量等效物的全部範圍。
本發明的一個或多個實施方案將參照附圖描述，其中以相同標號來表示相同元件，且其中例示的結構不一定按比例繪製。以下，術語“裸晶”、“晶片”、“半導體晶片”，和“半導體裸晶”在整個說明書中係可互換使用。
請參閱第1圖至第16圖，其為依據本發明實施例所繪製的封裝上封裝構件的製作方法剖面示意圖。
如第1圖所示，首先提供一載板300。載板300可以是一可被卸下或撕除的基板材料，且可以具有一黏著層(圖未示)，但不限於此。接著，在載板300的一上表面可以形成至少一介電層或一鈍化層310。鈍化層310可以包含有有機材料，例如聚醯亞胺(polyimide)，或無機材料，例如氮化矽、氧化矽等等。
如第2圖所示，接著，在鈍化層310上形成一重佈線層(redistribution layer, RDL)410。所述重佈線層410可以包括至少一介電層412以及至少一金屬層414。其中，介電層412可以包括有機材料，例如聚醯亞胺，或無機材料，例如氮化矽、氧化矽等等，但不限於此。金屬層414可以包括鋁、銅、鎢、鈦、氮化鈦等等。
根據本發明實施例，所述金屬層414可以包括複數個第一凸塊墊415a以及第二凸塊墊415b，從介電層412的一上表面顯露出來。第一凸塊墊415a係設置在一晶片安裝區域102內，而虛設的第二凸塊墊415b則設置在晶片安裝區域102外，例如一圍繞晶片安裝區域102的周邊區域104內。接著，可以繼續在所述介電層412上形成一鈍化層413，例如聚醯亞胺或防焊材料。
如第3圖所示，接著可以進行一微影製程以及一蝕刻製程，於鈍化層413中形成複數個開孔413a及開孔413b。其中，開孔413a及開孔413b分別顯露出所述第一凸塊墊415a以及第二凸塊墊415b。接著，在鈍化層413上以及開孔413a、413b內形成一均厚的導電層416，例如凸塊下金屬層(Under Bump Metallurgy, UBM)。舉例來說，所述導電層416可以包括銅或鎳，但不限於此。
如第4圖所示，接著於所述導電層416上塗佈一光阻層510，然後，將所述光阻層510圖案化，例如，利用已知的微影製程，如此分別在開孔413a及開孔413b的正上方形成複數個開孔510a及開孔510b。
如第5圖所示，接著進行一電鍍製程，使開孔413a、510a以及開孔413b、510b內分別被導電栓塞514a以及導電栓塞514b填滿。根據本發明實施例，所述電鍍製程可以包括一銅電鍍製程，但不限於此。所述導電栓塞514a以及導電栓塞514b彼此分離，不相連接。根據本發明實施例，所述導電栓塞514a可以包括銅、鋁、鎢、鈦、氮化鈦等。根據本發明實施例，所述導電栓塞514b可以包括銅、鋁、鎢、鈦、氮化鈦等。
如第6圖所示，接著可以在光阻層510以及導電栓塞514a、514b上塗佈另一光阻層520。然後，將所述光阻層520圖案化，例如，利用已知的微影製程，如此分別在導電栓塞514b的正上方形成複數個開孔520b。此時，導電栓塞514a則是被光阻層520覆蓋住，未被顯露出來。
如第7圖所示，接著進行一電鍍製程，使開孔520b內被導電栓塞524b填滿。根據本發明實施例，所述電鍍製程可以包括一銅電鍍製程，但不限於此。所述導電栓塞524b僅形成在開孔520b內。根據本發明實施例，所述導電栓塞524b可以包括銅、鋁、鎢、鈦、氮化鈦等。
如第8圖所示，隨後完全去除光阻層520以及光阻層510，顯露出導電栓塞514a、514b以及導電栓塞524b。其中，導電栓塞514b以及導電栓塞524b堆疊構成一導電柱體624。接下來，進行一蝕刻製程，選擇性的從鈍化層413的上表面去除部分的導電層416。此時，位於周邊區域104內的各導電柱體624，其包括堆疊的導電栓塞514b及導電栓塞524b，係高於設置在晶片安裝區域102內的導電栓塞514a。
如第9圖所示，接下來，將個別的覆晶晶片或裸晶420a及420b，使其主動面朝下，面對重佈線層410，安裝連接到晶片安裝區域102內的導電栓塞514a上，如此構成一晶片至晶圓(chip-to-wafer, C2W)堆疊結構。所述覆晶晶片或裸晶420a及420b可以分別透過分佈在其主動面上的端點421與導電栓塞514a連接。所述覆晶晶片或裸晶420a及420b可以是主動積體電路晶片，具有特定功能，例如，繪圖處理晶片、中央處理器晶片或記憶體晶片等等。
此外，可以另選擇在各個裸晶420a、420b下方塗佈一底膠(圖未示)。值得注意的是，導電柱體624具有一上表面，其低於各個裸晶420a、420b的上表面。
如第10圖所示，在完成上述晶片安裝接合步驟後，接著形成一成型模料500。所述成型模料500覆蓋已貼設安裝好的晶片420a及420b、凸出的導電柱體624，以及鈍化層413的上表面。所述成型模料500可以經過一固化製程。例如，所述成型模料500可以包括環氧樹脂及矽填充物，但不限於此。
如第11圖所示，可選擇對所述成型模料500的上表面進行一研磨製程，以移除掉成型模料500的一上部。此時，成型模料500的上表面經研磨後可以與晶片420a及420b的上表面齊平。
接著，進行一雷射鑽孔製程，於成型模料500中形成開孔502b，分別透過開孔502b顯露出各個導電柱體624的上表面。需理解的是，所述開孔502b可以透過其他方式形成，例如機械鑽孔或蝕刻。所述開孔502b可以具有向下漸縮的傾斜側壁輪廓。所述開孔502b在成型模料500的上表面處的孔洞尺寸較寬，而在接近導電柱體624的孔洞底部的尺寸較小。
如第12圖所示，接著進行一另一電鍍製程，使所述開孔502b填滿導電材料，如此形成一部分穿模導孔(partial through-mold-via, partial TMV)504b。根據本發明實施例，所述電鍍製程可以包括銅電鍍製程，但不限於此。所述部分穿模導孔504b僅形成在各個開孔502b內。所述導電材料可以包括銅、鋁、鎢、鈦、氮化鈦等。
本發明的優點在於用來形成部分穿模導孔504b的開孔502b具有較小的深寬比(aspect ratio)，因此，製程的良率及產能可以獲得改善，且具有較大的製程餘裕(process window)。
根據本發明實施例，所述部分穿模導孔504b以及導電柱體624共同構成一週邊凸塊結構724，其貫穿成型模料500的整個厚度。所述部分穿模導孔504b具有與開孔502b相符的漸縮輪廓。由於所述部分穿模導孔504b在底部的寬度較小，因此所述部分穿模導孔504b與導電柱體624之間會有一底切結構725。
如第13圖所示，接著，在成型模料500上黏貼一載板600，使所述週邊凸塊結構724的上表面直接接觸到載板600。同樣的，載板600可以是一可被卸下或撕除的基板材料，且可以具有一黏著層(圖未示)，但不限於此。載板600可以提供一臨時性的支撐。接著，將載板300移除，以顯露出鈍化層310的一主表面。重佈線層410以及鈍化層310可作為一中介層400。上述去除載板300的步驟，可以利用雷射或紫外線照射等方式進行，但不限於此。
如第14圖所示，在移除載板300後，可以繼續在鈍化層310中形成開口，分別顯露出錫球焊墊412a，然後，可以在顯露出的錫球焊墊412a上分別形成焊錫凸塊(如C4凸塊)或錫球(如BGA錫球)520。此外，形成錫球520之前，可選擇在鈍化層310上形成一介電層或一防焊層530。
如第15圖所示，接著，將載板600移除，以顯露出所述週邊凸塊結構724的上表面。接著，對圖中的晶圓級封裝進行切割，形成個別的晶片封裝10。例如，在進行切割之前，圖中的晶圓級封裝可以先黏貼一切割膠帶650，使凸塊或錫球520朝下，並接觸切割膠帶650。
如第16圖所示，接著將一晶片封裝(上晶片封裝)20，其包括一經模封的半導體晶片201，安置並連接至晶片封裝(下晶片封裝)10上，如此，構成一封裝上封裝構件1。所述的經模封的半導體晶片201可以包括一動態隨機存取記憶體(DRAM)晶片，但不限於此。所述晶片封裝20可以包括複數個BGA錫球250，其對準並接合所述週邊凸塊結構724。所述晶片封裝20經由週邊凸塊結構724以及重佈線層410與所述晶片封裝10電連接。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1‧‧‧封裝上封裝構件
10、20‧‧‧晶片封裝
102‧‧‧晶片安裝區域
104‧‧‧周邊區域
201‧‧‧經模封的半導體晶片
250‧‧‧BGA錫球
300、600‧‧‧載板
310‧‧‧鈍化層
400‧‧‧中介層
410‧‧‧重佈線層
412‧‧‧介電層
412a‧‧‧錫球焊墊
413‧‧‧鈍化層
413a、413b‧‧‧開孔
414‧‧‧金屬層
415a‧‧‧第一凸塊墊
415b‧‧‧第二凸塊墊
416‧‧‧導電層
420a、420b‧‧‧覆晶晶片或裸晶
421‧‧‧端點
500‧‧‧成型模料
502b‧‧‧開孔
504b‧‧‧部分穿模導孔
510、520‧‧‧光阻層
510a、510b、520b‧‧‧開孔
514a、514b、524b‧‧‧導電栓塞
520‧‧‧焊錫凸塊或錫球
530‧‧‧防焊層
624‧‧‧導電柱體
724‧‧‧週邊凸塊結構
725‧‧‧底切結構
所附圖說係提供本發明更進一步的了解，並納入並構成本說明書的一部分。該附圖說與說明書內容一同闡述之本發明實施例係有助於解釋本發明的原理原則。在圖說中：   第1圖至第16圖為依據本發明實施例所繪製的封裝上封裝構件的製作方法剖面示意圖。   應當注意的是，所有的圖說皆為概略性的。為方便和在圖紙上清晰起見，圖說之相對尺寸和部分零件比例係以誇大或縮小規模呈現。相同的標號一般係用來於不同的實施例中指示相對應或類似的元件。
1‧‧‧封裝上封裝構件
10、20‧‧‧晶片封裝
201‧‧‧經模封的半導體晶片
250‧‧‧BGA錫球
310‧‧‧鈍化層
410‧‧‧重佈線層
412‧‧‧介電層
412a‧‧‧錫球焊墊
413‧‧‧鈍化層
415a‧‧‧第一凸塊墊
415b‧‧‧第二凸塊墊
416‧‧‧導電層
420a、420b‧‧‧覆晶晶片或裸晶
421‧‧‧端點
500‧‧‧成型模料
504b‧‧‧部分穿模導孔
514b、524b‧‧‧導電栓塞
520‧‧‧焊錫凸塊或錫球
530‧‧‧防焊層
624‧‧‧導電柱體
724‧‧‧週邊凸塊結構

Claims (9)

  1. 一種封裝上封裝構件，包含有：一下晶片封裝，包含有：一中介層，其具有一第一面以及相對該第一面的一第二面；至少一晶片，經由複數個凸塊安置於該第一面的一晶片安裝區域內；一成型模料，設於該第一面，鄰近該至少一晶片；複數個週邊凸塊結構，位於一週邊區域內，且貫穿該成型模料，其中各該週邊凸塊結構包含一埋入在該成型模料內的導電柱體以及一直接堆疊在該導電柱體的部分穿模導孔，其中該導電柱體包含一第一導電栓塞以及一堆疊於該第一導電栓塞上的一第二導電栓塞，並且該第一導電栓塞與該等凸塊是以相同製程同時形成；及複數個錫球，設置於該第二面上；及一上晶片封裝，設置於該下晶片封裝之上，連接該複數個週邊凸塊結構。
  2. 如申請專利範圍第1項所述的封裝上封裝構件，其中該中介層包含一重佈線層。
  3. 如申請專利範圍第2項所述的封裝上封裝構件，其中該重佈線層包含至少一介電層以及至少一金屬層。
  4. 如申請專利範圍第1項所述的封裝上封裝構件，其中該上晶片封裝包含至少一經模封的半導體晶片。
  5. 如申請專利範圍第1項所述的封裝上封裝構件，其中該導電柱體的一 上表面係高於該凸塊的上表面。
  6. 如申請專利範圍第1項所述的封裝上封裝構件，其中該導電柱體與該部分穿模導孔之間具有一底切結構。
  7. 如申請專利範圍第1項所述的封裝上封裝構件，其中該第一導電栓塞包含銅、鋁、鎢、鈦，或氮化鈦。
  8. 如申請專利範圍第7項所述的封裝上封裝構件，其中該第二導電栓塞包含銅、鋁、鎢、鈦，或氮化鈦。
  9. 如申請專利範圍第1項所述的封裝上封裝構件，其中該部分穿模導孔包含銅、鋁、鎢、鈦，或氮化鈦。
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