TWI587471B - 具有側壁保護重佈線層中介層的半導體封裝及其製作方法 - Google Patents

具有側壁保護重佈線層中介層的半導體封裝及其製作方法 Download PDF

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TWI587471B
TWI587471B TW105113202A TW105113202A TWI587471B TW I587471 B TWI587471 B TW I587471B TW 105113202 A TW105113202 A TW 105113202A TW 105113202 A TW105113202 A TW 105113202A TW I587471 B TWI587471 B TW I587471B
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semiconductor package
rdl
interposer
layer
semiconductor
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TW105113202A
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TW201733070A (zh
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施信益
吳鐵將
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美光科技公司
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Description

具有側壁保護重佈線層中介層的半導體封裝及其製作方法
本發明係有關於半導體封裝技術領域，特別是有關於一種具有側壁保護（sidewall-protected）重佈線層中介層（RDL interposer）的晶圓級封裝及其製作方法。
半導體技術發展非常快，尤其在半導體晶片朝向微型化發展的趨勢下，對於半導體晶片的功能則越要求更多樣性。這也就是說，半導體晶片上勢必會有更多的輸出/輸入（I/O）墊被擠在一個更小的區域，因此，半導體晶片上的接合墊密度迅速提高，導致半導體晶片的封裝變得更加困難。
封裝的主要目的在保護晶片的內部電路不會受外在因素（例如濕氣或汙染物）破壞。此外，晶片產生的熱可以藉由封裝結構有效的逸散，使得晶片能正常運作。
如本領域中公知的，晶圓級封裝（WLP）係在將晶粒切割分離之前先進行模封。晶圓級封裝技術具有一定的優勢，如更短的生產週期時間和較低的成本。扇出晶圓級封裝（FOWLP）則是將半導體晶片的接觸墊通過基板上的重佈線層（RDL）再分配到一較大的面積上的封裝技術。重佈線層通常形成在一基板上，例如TSV中介層基板。
重佈線層通常由額外的金屬層及介電層所構成，其形成在晶圓表面，將晶片的I/O墊重新繞線成間距較寬鬆的佈局圖案。上述重分佈通常利用薄膜聚合物，例如，苯並環丁烯（BCB）、聚亞醯胺（PI）或其它有機聚合物，以及金屬化製程，例如，鋁金屬或銅金屬，如此將接合墊重繞線至一面積陣列組態。
由於製程繁複，TSV中介基板通常成本較高，因此，使用TSV中介基板的扇出晶圓級封裝也會比較昂貴，並不利於特定的應用場合。
晶圓級封裝製程中，通常會在晶圓及安裝在晶圓上的晶片表面覆蓋一相對較厚的成型模料。此成型模料與積體電路基底的熱膨脹係數(CTE)差異，容易導致封裝翹曲或變形，也使得封裝整體的厚度增加。晶圓翹曲(warpage)一直是該領域關注的問題。
晶圓翹曲使晶片與晶圓間的接合不易維持，使“晶片對晶圓接合”(chip to wafer)的組裝失敗。翹曲問題在大尺寸晶圓上更是明顯，特別是對於具有小間距重佈線層的晶圓級半導體封裝製程，此問題更為嚴重。因此，業界仍需要一個改良的晶圓級封裝及方法，可以解決上述先前技術的問題。
本發明主要目的在提供一種改良的導體封裝及製作方法，可以減輕模封後翹曲現象，並且避免RDL中介層的破裂或脫層。
根據本發明一實施，提供一種半導體封裝，包含一重佈線層（RDL）中介層，具有一第一面、相對於該第一面的一第二面，及延伸於該第一面與該第二面之間的一垂直側壁；至少一半導體晶粒，設於該RDL中介層的該第一面上；一成型模料，設於該第一面上，該型模料包覆該半導體晶粒以及該RDL中介層的該垂直側壁；以及複數個焊錫凸塊設於該第二面上。
根據本發明另一實施，提供一種製作半導體封裝的方法。首先提供一載板；於該載板上形成一重佈線層（RDL）中介層；於該RDL中介層的一第一側上安裝至少一半導體晶粒；進行一切割製程，形成至少一切割溝槽，貫穿該RDL中介層，其中該切割溝槽顯露出該RDL中介層的一垂直側壁；以一成型模料模封該第一側上的該半導體晶粒，其中該成型模料填入該切割溝槽，並覆蓋該RDL中介層的該垂直側壁；去除該載板，顯露出該RDL中介層的一第二側；以及於該第二側上形成複數個焊錫凸塊。
無庸置疑的，該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後，均可了解本發明的目的。
接下來的詳細敘述係參照相關圖式所示內容，用來說明可依據本發明可具體實行的實施例。這些實施例已提供足夠的細節，可使本領域技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，仍可做結構上的修改，並應用在其他實施例上。
因此，接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求界定。與本發明權利要求具均等意義者，也應屬本發明涵蓋的範圍。
本發明實施例所參照的附圖為示意圖，並未按原比例繪製，且相同或類似的特徵通常以相同的附圖標記描述。在本說明書中，“晶粒”、“半導體晶片”與“半導體晶粒”具相同含意，可交替使用。
在本說明書中，“晶圓”與“基板”意指任何包含一暴露面，可依據本發明實施例所示在其上沉積材料，製作積體電路結構的結構物，例如重佈線層（RDL）。須了解的是“基板”包含半導體晶圓，但並不限於此。"基板"在製程中也意指包含製作於其上的材料層的半導體結構物。
請參閱第1圖至第11圖。第1圖至第11圖為根據本發明實施例所繪示的示意性剖面圖，例示製作一具有包封（encapsulated）重佈線層中介層（RDL interposer）的半導體封裝的方法。
如第1圖所示，首先提供一載板300。載板300可以是一可卸式基板，可以包含一黏著層（圖未示）。例如，載板300可以是一矽晶圓基板或一玻璃基板，但不限於此。在載板300的上表面形成有至少一介電層或一鈍化層310。鈍化層310可以包含有機材料，例如，聚醯亞胺（polyimide, PI），或者無機材料，例如，氮化矽、氧化矽等。
接著，如第2圖所示，在鈍化層310上形成一重佈線層（RDL）410。重佈線層410包含至少一介電層412與至少一金屬層414。介電層412可包含有機材料，例如，聚亞醯胺(polyimide, PI)，或者無機材料，例如氮化矽、氧化矽等，但不限於此。金屬層414可包含鋁、銅、鎢、鈦、氮化鈦或類似的材料。
根據本發明實施例，金屬層414可以包含複數個凸塊墊415，從介電層412的一上表面顯露出來。在重佈線層410上形成有一鈍化層（或一介電層）510。應理解的是，鈍化層510可以包含一防銲層，但不限於此。
如第3圖所示，在重佈線層410上形成複數個凸塊416，例如，微凸塊，用以進一步連結。凸塊416可以分別直接形成在金屬層414的凸塊墊415上。
所述形成凸塊416的方法為周知技藝。例如，先在鈍化層510中形成開孔，顯露出個別的凸塊墊415，接著可選擇沉積一凸塊下金屬（under-bump metallurgy，UBM）層，然後以光阻定義出凸塊416的位置，再以電鍍製程形成金屬凸塊，接著移除光阻，再將未被金屬凸塊覆蓋的UBM層去除。
根據本發明實施例，凸塊416可以包含銅，但不限於此。在其它實施例中，凸塊416可以是焊錫凸塊，後續需要進一步回焊處理。以下，將鈍化層310、重佈線層410及鈍化層510所構成的結構稱為RDL中介層400。
如第4圖所示，形成凸塊416之後，個別的覆晶晶片或晶粒420a及420b以主動面朝下面對RDL中介層400的方式，藉由凸塊416安裝至RDL中介層400上，形成“晶片對晶圓接合”(C2W)的層疊結構。
這些個別的覆晶晶片或晶粒420a及420b為具有特定功能的主動積體電路晶片，例如繪圖處理器(GPU)、中央處理器(CPU)、記憶體晶片等等。根據本發明實施例，晶粒420a及420b可以在同一封裝內，而為具有不同特定功能的晶片。
上述步驟完成後，可選擇性地在每一晶粒420a及420b下方填充底膠（圖未示）。隨後，可進行熱處理，使凸塊416回焊
如第5圖所示，進行一切割製程，沿著晶圓切割道形成切割溝槽602，其貫穿RDL中介層400，並稍微延伸進入到載板300。上述切割溝槽602不會貫穿載板300的整個厚度。
此時，RDL中介層400的垂直側壁400a在切割溝槽602中被顯露出來。根據本發明實施例，切割溝槽602可以利用切割刀或雷射形成，但不限於此。
如第6圖所示，接著在RDL中介層400上覆蓋一成型模料500。成型模料500覆蓋已安裝好的晶粒420a及420b與鈍化層510的頂面。成型模料500也覆蓋RDL中介層400的垂直側壁400a。根據本發明實施例，切割溝槽602可以完全被成型模料500填滿。
隨後，成型模料500可藉由一固化製程使之固化。根據本發明實施例，成型模料500例如為環氧樹脂與二氧化矽填充劑的混和物，但並不限於此。接著，可選擇將成型模料500上部磨除，顯露出晶粒420a及420b的上表面。
如第7圖所示，在形成成型模料500之後，去除載板300，以顯露出鈍化層310的一表面。上述去除載板300可以利用雷射製程或紫外線（UV）照射製程，但不限於此。此時，形成凸出結構512。
如第8圖所示，繼續進行一研磨製程，例如化學機械研磨（CMP）製程，以去除凸出結構512。應理解的是，上述凸出結構512也可以利用其他方法去除，例如，蝕刻。此時，成型模料500具有一上表面500a，與鈍化層310的一表面310a齊平。
如第9圖所示，接著於鈍化層310上形成一防銲層312。再利用微影製程及蝕刻製程於防銲層312及鈍化層310中形成開孔314，分別顯露出位於重佈線層410的金屬層414內的錫球焊墊417。
如第10圖所示，接著在錫球焊墊417上分別形成焊錫凸塊520。雖然圖中未繪示，但應理解的是，焊錫凸塊520下方可以先形成凸塊下金屬（UBM）層。所述形成焊錫凸塊520的方法為周知技藝，故其細節不另贅述。例如，焊錫凸塊520可以利用電鍍、網版印刷、植球法或其它合適的方法形成。
如第11圖所示，進行一晶圓切割製程，將個別的半導體封裝10彼此分離。需理解的是，在其它實施例中，每個半導體封裝10中可以只包括單一晶粒。本發明的主要特徵之一在於成型模料500係直接接觸到RDL中介層400的垂直側壁400a。本發明的優點在於RDL中介層400的垂直側壁400a被成型模料500包覆保護住，因此，可以有效的避免RDL中介層400的破裂或脫層。此外，成型模料500係直接接觸到防焊層312，但是成型模料500未覆蓋防焊層312的側壁。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
10‧‧‧半導體封裝
300‧‧‧載板
310‧‧‧鈍化層
310a‧‧‧表面
312‧‧‧防銲層
314‧‧‧開孔
400‧‧‧RDL中介層
400a‧‧‧垂直側壁
410‧‧‧重佈線層（RDL）
412‧‧‧介電層
414‧‧‧金屬層
415‧‧‧凸塊墊
416‧‧‧凸塊
417‧‧‧錫球焊墊
420a、420b‧‧‧晶粒(晶片)
500‧‧‧成型模料
500a‧‧‧上表面
510‧‧‧鈍化層
512‧‧‧凸出結構
520‧‧‧焊錫凸塊
602‧‧‧切割溝槽
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。其中          第1圖至第11圖為根據本發明實施例所繪示的示意性剖面圖，例示製作一有側壁保護（sidewall-protected）重佈線層中介層（RDL interposer）的半導體封裝的方法。
10‧‧‧半導體封裝
310‧‧‧鈍化層
310a‧‧‧表面
312‧‧‧防銲層
400‧‧‧RDL中介層
410‧‧‧重佈線層(RDL)
412‧‧‧介電層
414‧‧‧金屬層
420a、420b‧‧‧晶粒(晶片)
500‧‧‧成型模料
510‧‧‧鈍化層
520‧‧‧焊錫凸塊

Claims (12)

  1. 一種半導體封裝，包含：一重佈線層(RDL)中介層，具有一第一面、相對於該第一面的一第二面，及延伸於該第一面與該第二面之間的一垂直側壁；至少一半導體晶粒，設於該RDL中介層的該第一面上；一成型模料，設於該第一面上，該成型模料包覆該半導體晶粒以及該RDL中介層的該垂直側壁，其中該成型模料具有一水平表面與該鈍化層的一表面齊平；以及複數個焊錫凸塊設於該第二面上。
  2. 如申請專利範圍第1項所述的半導體封裝，其中該成型模料直接接觸該RDL中介層的該垂直側壁。
  3. 如申請專利範圍第1項所述的半導體封裝，其中該RDL中介層包含一重佈線層，而該重佈線層包含至少一介電層及至少一金屬層。
  4. 如申請專利範圍第3項所述的半導體封裝，其中該介電層包含聚亞醯胺、氮化矽或氧化矽。
  5. 如申請專利範圍3項所述的半導體封裝，其中該金屬層包含鋁、銅、鎢、鈦或氮化鈦。
  6. 如申請專利範圍第3項所述的半導體封裝，其中該RDL中介層另包含一鈍化層，設於該介電層上。
  7. 如申請專利範圍第1項所述的半導體封裝，其中該第二側上設有一防焊層，其中該防焊層直接接觸該成型模料。
  8. 一種製作半導體封裝的方法，包含：提供一載板；於該載板上形成一重佈線層(RDL)中介層；於該RDL中介層的一第一側上安裝至少一半導體晶粒；進行一切割製程，形成至少一切割溝槽，貫穿該RDL中介層，其中該切割溝槽顯露出該RDL中介層的一垂直側壁；以一成型模料模封該第一側上的該半導體晶粒，其中該成型模料填入該切割溝槽，並覆蓋該RDL中介層的該垂直側壁；去除該載板，顯露出該RDL中介層的一第二側；以及於該第二側上形成複數個焊錫凸塊。
  9. 如申請專利範圍第8項所述的製作半導體封裝的方法，其中該切割溝槽係沿著晶圓切割道切割出來的。
  10. 如申請專利範圍第8項所述的製作半導體封裝的方法，其中去除該載板之後，至少形成一凸出結構，其中該凸出結構從該第二側的一表面上凸起。
  11. 如申請專利範圍第10項所述的製作半導體封裝的方法，其中另包含：進行一平坦化製程，去除該凸出結構。
  12. 如申請專利範圍第8項所述的製作半導體封裝的方法，其中另包含：進行一晶圓切割製程，將個別的半導體封裝彼此分離。
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