CN107195594A - 具有侧壁保护重布层中介层的半导体封装及其制造方法 - Google Patents

具有侧壁保护重布层中介层的半导体封装及其制造方法 Download PDF

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CN107195594A
CN107195594A CN201610649629.8A CN201610649629A CN107195594A CN 107195594 A CN107195594 A CN 107195594A CN 201610649629 A CN201610649629 A CN 201610649629A CN 107195594 A CN107195594 A CN 107195594A
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semiconductor packages
redistribution layer
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intermediary
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CN107195594B (zh
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施信益
吴铁将
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Micron Technology Inc
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Micron Technology Inc
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Abstract

具有侧壁保护重布层中介层的半导体封装及其制造方法，本发明公开了一种半导体封装，包含一重布层中介层，具有一第一面、相对于第一面的一第二面，及延伸于第一面与第二面之间的一垂直侧壁；至少一半导体晶粒，设在重布层中介层的第一面上；一模塑料，设在第一面上，模塑料包覆半导体晶粒以及重布层中介层的垂直侧壁；以及多个焊锡凸块设在第二面上。

Description

具有侧壁保护重布层中介层的半导体封装及其制造方法
技术领域
本发明涉及半导体封装技术领域，特别是涉及一种具有侧壁保护(sidewall-protected)重布层中介层(RDL interposer)的晶圆级封装及其制造方法。
背景技术
半导体技术发展非常快，尤其在半导体芯片朝向微型化发展的趋势下，对于半导体芯片的功能则越要求更多样性。这也就是说，半导体芯片上势必会有更多的输出/输入(I/O)垫被挤在一个更小的区域，因此，半导体芯片上的接合垫密度迅速提高，导致半导体芯片的封装变得更加困难。
封装的主要目的在保护芯片的内部电路不会受外在因素(例如湿气或污染物)破坏。此外，芯片产生的热可以借由封装结构有效的逸散，使得芯片能正常运作。
如本领域中公知的，晶圆级封装(WLP)是在将晶粒切割分离之前先进行模封。晶圆级封装技术具有一定的优势，如更短的生产周期时间和较低的成本。扇出晶圆级封装(FOWLP)则是将半导体芯片的接触垫通过衬底上的重布层(RDL)再分配到一较大的面积上的封装技术。重布层通常形成在一衬底上，例如TSV中介层衬底。
重布层通常由额外的金属层及介电层所构成，其形成在晶圆表面，将芯片的I/O垫重新绕线成间距较宽松的布局图案。上述重分布通常利用薄膜聚合物，例如，苯并环丁烯(BCB)、聚亚酰胺(PI)或其它有机聚合物，以及金属化工艺，例如，铝金属或铜金属，如此将接合垫重绕线至一面积数组组态。
由于工艺繁复，TSV中介衬底通常成本较高，因此，使用TSV中介衬底的扇出晶圆级封装也会比较昂贵，并不利于特定的应用场合。
晶圆级封装工艺中，通常会在晶圆及安装在晶圆上的芯片表面覆盖一相对较厚的模塑料。此模塑料与集成电路基底的热膨胀系数(CTE)差异，容易导致封装翘曲或变形，也使得封装整体的厚度增加。晶圆翘曲(warpage)一直是该领域关注的问题。
晶圆翘曲使芯片与晶圆间的接合不易维持，使“芯片对晶圆接合”(chip towafer)的组装失败。翘曲问题在大尺寸晶圆上更是明显，特别是对于具有小间距重布层的晶圆级半导体封装工艺，此问题更为严重。因此，业界仍需要一个改良的晶圆级封装及方法，可以解决上述先前技术的问题。
发明内容
本发明主要目的在提供一种改良的导体封装及制造方法，可以减轻模封后翘曲现象，并且避免RDL中介层的破裂或脱层。
根据本发明一实施，提供一种半导体封装，包含一重布层(RDL)中介层，具有一第一面、相对于第一面的一第二面，及延伸于第一面与第二面之间的一垂直侧壁；至少一半导体晶粒，设在RDL中介层的第一面上；一模塑料，设在第一面上，模塑料包覆半导体晶粒以及RDL中介层的垂直侧壁；以及多个焊锡凸块设在第二面上。
根据本发明另一实施，提供一种制造半导体封装的方法。首先提供一载板；在载板上形成一重布层(RDL)中介层；在RDL中介层的一第一侧上安装至少一半导体晶粒；进行一切割工艺，形成至少一切割沟槽，贯穿RDL中介层，其中切割沟槽显露出RDL中介层的一垂直侧壁；以一模塑料模封第一侧上的半导体晶粒，其中模塑料填入切割沟槽，并覆盖RDL中介层的垂直侧壁；去除载板，显露出RDL中介层的一第二侧；以及在第二侧上形成多个焊锡凸块。
无庸置疑的，本领域的技术人员读完接下来本发明较佳实施例的详细描述与附图后，均可了解本发明的目的。
附图说明
附图提供对于此实施例更深入的了解，并纳入此说明书成为其中一部分。这些附图与描述，用来说明一些实施例的原理。其中
图1至图11为根据本发明实施例所绘示的示意性剖面图，例示制造一有侧壁保护(sidewall-protected)重布层中介层(RDL interposer)的半导体封装的方法。
其中，附图标记说明如下：
10 半导体封装
300 载板
310 钝化层
310a 表面
312 防焊层
314 开孔
400 重布层(RDL)中介层
400a 垂直侧壁
410 重布层(RDL)
412 介电层
414 金属层
415 凸块垫
416 凸块
417 锡球焊垫
420a、420b 晶粒(芯片)
500 模塑料
500a 上表面
510 钝化层
512 凸出结构
520 焊锡凸块
602 切割沟槽
具体实施方式
接下来的详细叙述是参照相关附图所示内容，用来说明可依据本发明可具体实行的实施例。这些实施例已提供足够的细节，可使本领域技术人员充分了解并具体实行本发明。在不悖离本发明的范围内，仍可做结构上的修改，并应用在其他实施例上。
因此，接下来的详细描述并非用来对本发明加以限制。本发明涵盖的范围由其权利要求界定。与本发明权利要求具均等意义的，也应属本发明涵盖的范围。
本发明实施例所参照的附图为示意图，并未按原比例绘制，且相同或类似的特征通常以相同的附图标记描述。在本说明书中，“晶粒”、“半导体芯片”与“半导体晶粒”具相同含意，可交替使用。
在本说明书中，“晶圆”与“衬底”意指任何包含一暴露面，可依据本发明实施例所示在其上沉积材料，制造集成电路结构的结构物，例如重布层(RDL)。须了解的是“衬底”包含半导体晶圆，但并不限于此。"衬底"在工艺中也意指包含制造于其上的材料层的半导体结构物。
请参阅图1至图11。图1至图11为根据本发明实施例所绘示的示意性剖面图，例示制造一具有包封(encapsulated)重布层中介层(RDL interposer)的半导体封装的方法。
如图1所示，首先提供一载板300。载板300可以是一可卸式衬底，可以包含一黏着层(图未示)。例如，载板300可以是一硅晶圆衬底或一玻璃衬底，但不限于此。在载板300的上表面形成有至少一介电层或一钝化层310。钝化层310可以包含有机材料，例如，聚酰亚胺(polyimide,PI)，或者无机材料，例如，氮化硅、氧化硅等。
接着，如图2所示，在钝化层310上形成一重布层(RDL)410。重布层410包含至少一介电层412与至少一金属层414。介电层412可包含有机材料，例如，聚亚酰胺(polyimide,PI)，或者无机材料，例如氮化硅、氧化硅等，但不限于此。金属层414可包含铝、铜、钨、钛、氮化钛或类似的材料。
根据本发明实施例，金属层414可以包含多个凸块垫415，从介电层412的一上表面显露出来。在重布层410上形成有一钝化层(或一介电层)510。应理解的是，钝化层510可以包含一防焊层，但不限于此。
如图3所示，在重布层410上形成多个凸块416，例如，微凸块，用以进一步连结。凸块416可以分别直接形成在金属层414的凸块垫415上。
所述形成凸块416的方法为公知技艺。例如，先在钝化层510中形成开孔，显露出个别的凸块垫415，接着可选择沉积一凸块下金属(under-bump metallurgy，UBM)层，然后以光刻胶层定义出凸块416的位置，再以电镀工艺形成金属凸块，接着移除光刻胶层，再将未被金属凸块覆盖的UBM层去除。
根据本发明实施例，凸块416可以包含铜，但不限于此。在其它实施例中，凸块416可以是焊锡凸块，后续需要进一步回流焊处理。以下，将钝化层310、重布层410及钝化层510所构成的结构称为RDL中介层400。
如图4所示，形成凸块416之后，个别的覆晶芯片或晶粒420a及420b以有源面朝下面对RDL中介层400的方式，借由凸块416安装到RDL中介层400上，形成“芯片对晶圆接合”(C2W)的层叠结构。
这些个别的覆晶芯片或晶粒420a及420b是具有特定功能的有源集成电路芯片，例如绘图处理器(GPU)、中央处理器(CPU)、内存芯片等等。根据本发明实施例，晶粒420a及420b可以在同一封装内，而具有不同特定功能的芯片。
上述步骤完成后，可选择性地在每一晶粒420a及420b下方填充底胶(图未示)。随后，可进行热处理，使凸块416回流焊。
如图5所示，进行一切割工艺，沿着晶圆切割道形成切割沟槽602，其贯穿RDL中介层400，并稍微延伸进入到载板300。上述切割沟槽602不会贯穿载板300的整个厚度。
此时，RDL中介层400的垂直侧壁400a在切割沟槽602中被显露出来。根据本发明实施例，切割沟槽602可以利用切割刀或激光形成，但不限于此。
如图6所示，接着在RDL中介层400上覆盖一模塑料500。模塑料500覆盖已安装好的晶粒420a及420b与钝化层510的顶面。模塑料500也覆盖RDL中介层400的垂直侧壁400a。根据本发明实施例，切割沟槽602可以完全被模塑料500填满。
随后，模塑料500可借由一固化工艺使其固化。根据本发明实施例，模塑料500例如为环氧树脂与二氧化硅填充剂的混和物，但并不限于此。接着，可选择将模塑料500上部磨除，显露出晶粒420a及420b的上表面。
如图7所示，在形成模塑料500之后，去除载板300，以显露出钝化层310的一表面。上述去除载板300可以利用激光工艺或紫外线(UV)照射工艺，但不限于此。此时，形成凸出结构512。
如图8所示，继续进行一平坦化工艺，例如化学机械抛光(CMP)工艺，以去除凸出结构512。应理解的是，上述凸出结构512也可以利用其他方法去除，例如，蚀刻。此时，模塑料500具有一上表面500a，与钝化层310的一表面310a齐平。
如图9所示，接着在钝化层310上形成一防焊层312。再利用光刻工艺及蚀刻工艺在防焊层312及钝化层310中形成开孔314，分别显露出位在重布层410的金属层414内的锡球焊垫417。
如图10所示，接着在锡球焊垫417上分别形成焊锡凸块520。虽然图中未绘示，但应理解的是，焊锡凸块520下方可以先形成凸块下金属(UBM)层。所述形成焊锡凸块520的方法为公知技艺，故其细节不另赘述。例如，焊锡凸块520可以利用电镀、网版印刷、植球法或其它合适的方法形成。
如图11所示，进行一晶圆切割工艺，将个别的半导体封装10彼此分离。需理解的是，在其它实施例中，每个半导体封装10中可以只包括单一晶粒。本发明的主要特征之一在于模塑料500是直接接触到RDL中介层400的垂直侧壁400a。本发明的优点在于RDL中介层400的垂直侧壁400a被模塑料500包覆保护住，因此，可以有效的避免RDL中介层400的破裂或脱层。此外，模塑料500是直接接触到防焊层312，但是模塑料500未覆盖防焊层312的侧壁。
以上所述仅为本发明的优选实施例而已，并不用于限制本发明，对于本领域的技术人员来说，本发明可以有各种更改和变化。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (13)

1.一种半导体封装，其特征在于，包含：
一重布层中介层，具有一第一面、相对于所述第一面的一第二面，及延伸于所述第一面与所述第二面之间的一垂直侧壁；
至少一半导体晶粒，设在所述重布层中介层的所述第一面上；
一模塑料，设在所述第一面上，所述模塑料包覆所述半导体晶粒以及所述重布层中介层的所述垂直侧壁；以及
多个焊锡凸块设在所述第二面上。
2.根据权利要求1所述的半导体封装，其特征在于，所述模塑料直接接触所述重布层中介层的所述垂直侧壁。
3.根据权利要求1所述的半导体封装，其特征在于，所述重布层中介层包含一重布层，而所述重布层包含至少一介电层及至少一金属层。
4.根据权利要求3所述的半导体封装，其特征在于，所述介电层包含聚亚酰胺、氮化硅或氧化硅。
5.根据权利要求3所述的半导体封装，其特征在于，所述金属层包含铝、铜、钨、钛或氮化钛。
6.根据权利要求3所述的半导体封装，其特征在于，所述重布层中介层另包含一钝化层，设在所述介电层上。
7.根据权利要求6所述的半导体封装，其特征在于，所述模塑料具有一表面与所述钝化层的一表面齐平。
8.根据权利要求1所述的半导体封装，其特征在于，所述第二侧上设有一防焊层，其中所述防焊层直接接触所述模塑料。
9.一种制造半导体封装的方法，其特征在于，包含：
提供一载板；
在所述载板上形成一重布层中介层；
在所述重布层中介层的一第一侧上安装至少一半导体晶粒；
进行一切割工艺，形成至少一切割沟槽，贯穿所述重布层中介层，其中所述切割沟槽显露出所述重布层中介层的一垂直侧壁；
以一模塑料模封所述第一侧上的所述半导体晶粒，其中所述模塑料填入所述切割沟槽，并覆盖所述重布层中介层的所述垂直侧壁；
去除所述载板，显露出所述重布层中介层的一第二侧；以及
在所述第二侧上形成多个焊锡凸块。
10.根据权利要求9所述的制造半导体封装的方法，其特征在于，所述切割沟槽是沿着晶圆切割道切割出来的。
11.根据权利要求9所述的制造半导体封装的方法，其特征在于，去除所述载板之后，至少形成一凸出结构，其中所述凸出结构从所述第二侧的一表面上凸起。
12.根据权利要求11所述的制造半导体封装的方法，其特征在于，另包含：
进行一平坦化工艺，去除所述凸出结构。
13.根据权利要求9所述的制造半导体封装的方法，其特征在于，另包含：
进行一晶圆切割工艺，将个别的半导体封装彼此分离。
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109860125A (zh) * 2018-12-29 2019-06-07 华进半导体封装先导技术研发中心有限公司 芯片封装结构和封装方法
CN111554641A (zh) * 2020-05-11 2020-08-18 上海天马微电子有限公司 半导体封装件及其制作方法
CN111627867A (zh) * 2019-02-28 2020-09-04 富泰华工业（深圳）有限公司 芯片封装结构及其制作方法
CN111952198A (zh) * 2020-08-25 2020-11-17 济南南知信息科技有限公司 一种半导体封装及其制备方法
CN112018027A (zh) * 2019-05-31 2020-12-01 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法、晶圆切割方法
CN115332215A (zh) * 2022-10-14 2022-11-11 北京华封集芯电子有限公司 一种用于芯片封装的中介层及制作方法

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20190067145A1 (en) * 2017-08-22 2019-02-28 Micron Technology, Inc. Semiconductor device
TWI660473B (zh) * 2017-12-26 2019-05-21 Industrial Technology Research Institute 封裝結構及其形成方法
KR20210023021A (ko) 2019-08-21 2021-03-04 삼성전자주식회사 반도체 패키지
CN110676240A (zh) * 2019-10-16 2020-01-10 上海先方半导体有限公司 一种2.5d封装结构及其制造方法
CN111430313A (zh) * 2020-05-11 2020-07-17 上海天马微电子有限公司 半导体封装及其制作方法
US11264362B2 (en) * 2020-05-28 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and method of fabricating the same
CN112435996A (zh) * 2020-10-09 2021-03-02 日月光半导体制造股份有限公司 半导体封装装置及其制造方法
CN112908948A (zh) * 2021-01-18 2021-06-04 上海先方半导体有限公司 一种封装结构及其制造方法
CN112908947A (zh) * 2021-01-18 2021-06-04 上海先方半导体有限公司 一种塑封封装结构及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001293A1 (en) * 2004-08-31 2007-01-04 Tongbi Jiang Semiconductor assemblies including redistribution layers and packages and assemblies formed therefrom
CN103094244A (zh) * 2011-10-31 2013-05-08 欣兴电子股份有限公司 嵌埋穿孔中介层的封装基板及其制法
US20150014855A1 (en) * 2013-07-15 2015-01-15 Weng Foong Yap Microelectronic packages and methods for the fabrication thereof
CN104425395A (zh) * 2013-08-20 2015-03-18 日月光半导体制造股份有限公司 半导体封装件及其制造方法
US20150187608A1 (en) * 2013-12-26 2015-07-02 Sanka Ganesan Die package architecture with embedded die and simplified redistribution layer
CN106206527A (zh) * 2015-05-25 2016-12-07 华亚科技股份有限公司 半导体组件及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8115292B2 (en) * 2008-10-23 2012-02-14 United Test And Assembly Center Ltd. Interposer for semiconductor package
KR20100096879A (ko) * 2009-02-25 2010-09-02 삼성전자주식회사 구리 패드를 포함하는 반도체 소자, 그 적층 구조 및 그 제조 방법
US9385095B2 (en) * 2010-02-26 2016-07-05 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8519537B2 (en) * 2010-02-26 2013-08-27 Taiwan Semiconductor Manufacturing Company, Ltd. 3D semiconductor package interposer with die cavity
US8338945B2 (en) * 2010-10-26 2012-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Molded chip interposer structure and methods
KR101419600B1 (ko) * 2012-11-20 2014-07-17 앰코 테크놀로지 코리아 주식회사 지문인식센서 패키지 및 그 제조 방법
KR20140083657A (ko) * 2012-12-26 2014-07-04 하나 마이크론(주) 인터포저가 임베디드 되는 전자 모듈 및 그 제조방법
TWI496270B (zh) * 2013-03-12 2015-08-11 矽品精密工業股份有限公司 半導體封裝件及其製法
TWI555098B (zh) * 2015-02-13 2016-10-21 矽品精密工業股份有限公司 電子封裝件及其製法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070001293A1 (en) * 2004-08-31 2007-01-04 Tongbi Jiang Semiconductor assemblies including redistribution layers and packages and assemblies formed therefrom
CN103094244A (zh) * 2011-10-31 2013-05-08 欣兴电子股份有限公司 嵌埋穿孔中介层的封装基板及其制法
US20150014855A1 (en) * 2013-07-15 2015-01-15 Weng Foong Yap Microelectronic packages and methods for the fabrication thereof
CN104425395A (zh) * 2013-08-20 2015-03-18 日月光半导体制造股份有限公司 半导体封装件及其制造方法
US20150187608A1 (en) * 2013-12-26 2015-07-02 Sanka Ganesan Die package architecture with embedded die and simplified redistribution layer
CN106206527A (zh) * 2015-05-25 2016-12-07 华亚科技股份有限公司 半导体组件及其制造方法

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109860125A (zh) * 2018-12-29 2019-06-07 华进半导体封装先导技术研发中心有限公司 芯片封装结构和封装方法
CN111627867A (zh) * 2019-02-28 2020-09-04 富泰华工业（深圳）有限公司 芯片封装结构及其制作方法
CN112018027A (zh) * 2019-05-31 2020-12-01 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法、晶圆切割方法
CN111554641A (zh) * 2020-05-11 2020-08-18 上海天马微电子有限公司 半导体封装件及其制作方法
US11581196B2 (en) 2020-05-11 2023-02-14 Shanghai Tianma Micro-electronics Co., Ltd. Semiconductor package having semiconductor element with pins and formation method thereof
CN111952198A (zh) * 2020-08-25 2020-11-17 济南南知信息科技有限公司 一种半导体封装及其制备方法
CN111952198B (zh) * 2020-08-25 2022-09-13 嘉兴启创科技咨询有限公司 一种半导体封装及其制备方法
CN115332215A (zh) * 2022-10-14 2022-11-11 北京华封集芯电子有限公司 一种用于芯片封装的中介层及制作方法
CN115332215B (zh) * 2022-10-14 2023-03-24 北京华封集芯电子有限公司 一种用于芯片封装的中介层及制作方法

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