TWI571942B - 晶圓級封裝的製作方法 - Google Patents

晶圓級封裝的製作方法 Download PDF

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Publication number
TWI571942B
TWI571942B TW104133156A TW104133156A TWI571942B TW I571942 B TWI571942 B TW I571942B TW 104133156 A TW104133156 A TW 104133156A TW 104133156 A TW104133156 A TW 104133156A TW I571942 B TWI571942 B TW I571942B
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Taiwan
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layer
substrate
forming
wafer level
wafer
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TW104133156A
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TW201709357A (zh
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吳鐵將
施信益
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華亞科技股份有限公司
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Publication of TW201709357A publication Critical patent/TW201709357A/zh

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    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2924/30—Technical effects
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Description

晶圓級封裝的製作方法
本發明係有關於半導體封裝技術領域，特別是有關於一種晶圓級封裝(wafer level package, WLP)堆疊封裝構件及其製作方法。
隨著半導體製造技術的進步，微電子元件的尺寸變得更小，元件中的電路也變得更密集。為了得到更小尺寸的微電子元件，其封裝與安裝至電路板上的結構都必須變得更緊密。
習知的CoWoS (Chip on Wafer on Substrate)製程係利用穿矽通孔(Through Silicon Via, TSV)技術將多顆晶片整合成2.5D或3D積體電路裝置，此架構能提供較高的內連結線密度、降低整體內連結線長度，並減輕RC負載，因此除了能達到較小的形狀因子(form factor)，還能提升效能並減少耗電。其中，晶片可以透過形成在矽中介層(silicon interposer)或TSV中介層上的重佈線層(redistribution layer, RDL)互連。上述TSV中介層由於製程較為複雜，故成本通常較高。
重佈線層是在晶圓表面上形成介電層與金屬導線的疊層，將晶片原本的輸入/輸出(I/O)接墊重新佈線分配至一個間距較寬鬆的佈局範圍。上述重佈線的製作通常使用薄膜聚合物，例如苯併環丁稀(Benzocyclobutene, BCB)、聚亞醯胺(polyimind, PI)，或其他有機聚合物作為介電層材料，再以金屬化製程，例如鋁或銅，形成金屬導線，將晶片周圍的接墊重新佈線分配成陣列狀連接墊。
晶圓級封裝製程中，通常會在晶圓及安裝在晶圓上的晶片表面覆蓋一相對較厚的成型模料。此成型模料與積體電路基底的熱膨脹係數(CTE)差異，容易導致封裝翹曲或變形，也使得封裝整體的厚度增加。晶圓翹曲(warpage)一直是該領域關注的問題。
晶圓翹曲使晶片與晶圓間的接合不易維持，使“晶片對晶圓接合”(chip to wafer)的組裝失敗。翹曲問題在大尺寸晶圓上更是明顯，特別是對於具有小間距重佈線層的晶圓級半導體封裝製，問題更為嚴重。因此，業界仍需要一個改良的晶圓級封裝方法，可以解決上述先前技術的問題。
本發明的主旨在於提供一種改良的晶圓級封裝的製作方法，其中在晶片接合以及晶圓級模塑成型後，才進行穿矽通孔(或穿板通孔(through substrate via))的製作，如此可降低成本並減輕模塑成型後的翹曲情形。
根據本發明一實施例，本發明提供一種晶圓級封裝的製作方法，包含有：提供一基板，具有一上表面以及一下表面；於該上表面形成一第一介電層；於該第一介電層上形成一重佈線層，其中該包含至少一第二介電層與至少一金屬層；於該重佈線層上形成一第一鈍化層；於該第一鈍化層中形成凸塊；將一晶片安置於該重佈線層上，其中該晶片係透過該凸塊電連接該重佈線層中的該金屬層；於該第一鈍化層上及該晶片旁形成一成型模料；研磨該基板的該下表面，直到達到該基板的一預定剩餘厚度；以及於該基板中形成複數個穿板通孔。其中該基板的該預定剩餘厚度係根據該晶圓級封裝的翹曲程度及尺寸來決定。
無庸置疑的，該領域的技術人士讀完接下來本發明較佳實施例的詳細描述與圖式後，均可了解本發明的目的。
接下來的詳細敘述須參照相關圖式所示內容，用來說明可依據本發明具體實行的實施例。這些實施例提供足夠的細節，可使此領域中的技術人員充分了解並具體實行本發明。在不悖離本發明的範圍內，仍可稍做修改，應用在其他實施例上。
因此，接下來的詳細描述並非用來對本發明加以限制。本發明涵蓋的範圍由其權利要求界定。與本發明權利要求具同等意義者，也應屬本發明涵蓋的範圍。本發實施例所參照的附圖為示意圖，並未按比例繪製，且相同或類似的特徵通常以相同的附圖標記描述。
本發明係披露一種穿矽通孔後製(TSV-last)的晶圓級封裝製程，利用此製程，可以彈性的設計基板的剩餘厚度，以有效控制封裝翹曲。前述穿矽通孔(或穿板通孔)係在晶片接合以及晶圓級模塑成型後，才開始製作。
請參照第1圖至第10圖。第1圖至第10圖為根據本發明一實施例的示意性剖面圖，例示製作一晶圓級封裝的方法。如第1圖所示，首先提供一基板100，例如，基板100可以包含矽基板，但不限於此。在基板100的上表面100a上，形成有至少一介電層110。其中，介電層110可以包含氧化矽，但不限於此。
如第2圖所示，接著在介電層110上形成重佈線層(RDL)200。重佈線層200包含至少一介電層210與至少一金屬層212。介電層210可包含例如氮化矽、氧化矽或類似的材料，但不限於此。金屬層212可包含鋁、銅、鎢、鈦、氮化鈦或類似的材料。根據所述實施例，金屬層212可包含複數個凸塊墊212a，自介電層212的頂面暴露出來。凸塊墊212a設置於一晶片接合區域內。
如第3圖所示，接著在重佈線層200上方設置一鈍化層(或介電層)310。然後，可在重佈線層200上形成複數個凸塊312，例如微凸塊，作為後續連接使用。凸塊312可分別直接形成在金屬層212的凸塊墊212a上。
如第4圖所示，形成凸塊312後，個別的覆晶晶片或晶粒420以主動面朝下面對重佈線層200的方式，藉由凸塊312安裝至重佈線層200上，形成“晶片對晶圓接合”(C2W)的層疊結構。這些個別的覆晶晶片或晶粒420為具有特定功能的主動積體電路晶片，例如繪圖處理器(GPU)、中央處理器(CPU)、記憶體晶片等等。上述步驟完成後，可選擇性地在每一晶片或晶粒420下方填充底膠。隨後，可進行熱處理，使凸塊312迴焊。
晶粒接合完成後，接著在上方覆蓋一成型模料500。成型模料500覆蓋住安裝好的晶片420與重佈線層200的頂面。成型模料500隨後會藉由一固化製程使之固化。成型模料500例如為環氧樹脂與二氧化矽填充劑的混和物，但並不限於此。可選擇性地研磨移除部分成型模料500的上部，使晶片420的頂面暴露出來。
如第5圖所示，在完成上述模塑成型(molding)製程後，繼續進行一研磨製程，以研磨基板100的一下表面100b，藉此減少基板100的厚度。基板100的剩餘厚度t可以視設計需求而定，例如，視翹曲程度而定。舉例來說，基板100的剩餘厚度t可以介於0至120微米左右。本發明的優點在於可以根據晶片封裝的尺寸及所欲控制的翹曲程度，而彈性調整基板100的剩餘厚度t，達到最佳翹曲控制結果。
如第6圖所示，接著在基板100的下表面100b上沉積一介電層520，例如，矽氧層。
如第7圖及第8圖所示，接著進行一穿矽通孔(或穿板通孔)製程。首先，於基板100中形成複數個穿孔101。例如，穿孔101可以利用習知的微影及蝕刻製程來完成。接著，於穿孔101的側壁上形成一氧化襯墊層102，如第7圖所示。隨後，將穿孔101以導電材料填滿，例如，金屬，然後，將穿孔101外的多餘金屬研磨去除，如此形成穿矽通孔(或穿板通孔)610，如第8圖所示。
如第9圖所示，接著在基板100的下表面100b上形成一鈍化層710。例如，鈍化層710可包含氮化矽、氧化矽、氮氧化矽等無機材料，或例如聚亞醯胺(polyimide, PI)等有機材料。接著，可繼續於穿矽通孔610上分別形成焊接錫球712。例如，可利用習知的微影及蝕刻製程在鈍化層710中形成開口，再將錫球置於各開口內，然後迴焊。
熟習該項技藝者應理解第9圖中的基板100下表面100b所繪示結構僅為例示。例如，焊接錫球712不一定是直接形成在各個穿矽通孔610的底端。在其它實施例中，還可以在鈍化層710上形成背面重佈線層，以用於進一步連結。上述鈍化層710上的背面重佈線層可以包含至少一金屬層或多層金屬層，而焊接錫球712可以設置在該金屬層所定義的金屬墊上。此外，所述背面重佈線層也可以與穿矽通孔610同步以銅鑲嵌製程來形成。
如第10圖所示，進行切割製程，分隔出個別的晶圓級封裝10。例如，進行切割前，可先使用切割膠帶20作為載體。   以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
20‧‧‧切割膠帶
100‧‧‧基板
100a‧‧‧上表面
100b‧‧‧下表面
101‧‧‧穿孔
102‧‧‧氧化襯墊層
110‧‧‧介電層
200‧‧‧重佈線層
210‧‧‧介電層
212‧‧‧金屬層
212a‧‧‧凸塊墊
310‧‧‧鈍化層
312‧‧‧凸塊
420‧‧‧晶片(晶粒)
500‧‧‧成型模料
520‧‧‧介電層
610‧‧‧穿矽通孔(穿板通孔)
710‧‧‧鈍化層
712‧‧‧焊接錫球
t‧‧‧剩餘厚度
所附圖式提供對於此實施例更深入的了解，並納入此說明書成為其中一部分。這些圖式與描述，用來說明一些實施例的原理。   第1圖至第10圖為根據本發明一實施例的示意性剖面圖，例示製作一晶圓級封裝的方法。
100‧‧‧基板
100a‧‧‧上表面
100b‧‧‧下表面
110‧‧‧介電層
200‧‧‧重佈線層
210‧‧‧介電層
212‧‧‧金屬層
212a‧‧‧凸塊墊
310‧‧‧鈍化層
312‧‧‧凸塊
420‧‧‧晶片(晶粒)
500‧‧‧成型模料
t‧‧‧剩餘厚度

Claims (6)

  1. 一種晶圓級封裝的製作方法，包含有：提供一基板，具有一上表面以及一下表面；於該上表面形成一第一介電層；於該第一介電層上形成一重佈線層，其中該包含至少一第二介電層與至少一金屬層；於該重佈線層上形成一第一鈍化層；於該第一鈍化層中形成凸塊；將一晶片安置於該重佈線層上，其中該晶片係透過該凸塊電連接該重佈線層中的該金屬層；於該第一鈍化層上及該晶片旁形成一成型模料；形成該成型模料後，研磨該基板的該下表面，直到達到該基板的一預定剩餘厚度，其中該預定剩餘厚度係根據該晶圓級封裝的翹曲程度及尺寸來決定；以及於具有該預定剩餘厚度的該基板中形成複數個穿板通孔。
  2. 如申請專利範圍第1項所述的晶圓級封裝的製作方法，其中該基板係為一矽基板。
  3. 如申請專利範圍第1項所述的晶圓級封裝的製作方法，其中該第一介電層包含氧化矽。
  4. 如申請專利範圍第1項所述的晶圓級封裝的製作方法，其中該第二介 電層包含氮化矽或氧化矽。
  5. 如申請專利範圍第1項所述的晶圓級封裝的製作方法，其中於該基板中形成該複數個穿板通孔的步驟包含有：於該基板的該下表面形成一第三介電層；於該基板及該第三介電層中形成穿孔；於該穿孔的側壁上形成一氧化襯墊層；於該穿孔內填入一導電材料；以及研磨該導電材料。
  6. 如申請專利範圍第1項所述的晶圓級封裝的製作方法，其中另包含有：於該基板的該下表面形成一第二鈍化層；以及於該第二鈍化層中形成焊接錫球，電連接該穿板通孔。
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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI670841B (zh) * 2017-04-07 2019-09-01 南韓商三星電子股份有限公司 扇出型感測器封裝以及包含該封裝的光學指紋感測器模組
US10644046B2 (en) 2017-04-07 2020-05-05 Samsung Electronics Co., Ltd. Fan-out sensor package and optical fingerprint sensor module including the same
CN111490004A (zh) * 2019-01-28 2020-08-04 中芯长电半导体（江阴）有限公司 重新布线层的制备方法及半导体结构

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6858939B2 (ja) * 2017-04-28 2021-04-14 東北マイクロテック株式会社 外部接続機構、半導体装置及び積層パッケージ
US10461034B2 (en) * 2017-07-26 2019-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and manufacturing method thereof
US10515888B2 (en) * 2017-09-18 2019-12-24 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method for manufacturing the same
US20200036081A1 (en) * 2018-07-30 2020-01-30 Innolux Corporation Package structure and antenna device using the same
KR102662860B1 (ko) * 2019-05-29 2024-05-03 삼성전기주식회사 인쇄회로기판

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201135820A (en) * 2009-12-01 2011-10-16 Fujitsu Semiconductor Ltd Semiconductor device and method for making the same
TW201230281A (en) * 2010-11-29 2012-07-16 Samsung Electronics Co Ltd Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device
US20140360067A1 (en) * 2010-03-02 2014-12-11 Gredo Kahng Method and apparatus for influencing grocery shoppers to make healthy food purchase decisions

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100652395B1 (ko) * 2005-01-12 2006-12-01 삼성전자주식회사 다이-휨이 억제된 반도체 소자 및 그 제조방법
CN1941338A (zh) * 2005-09-30 2007-04-04 日月光半导体制造股份有限公司 芯片结构与晶片结构
US20130026609A1 (en) * 2010-01-18 2013-01-31 Marvell World Trade Ltd. Package assembly including a semiconductor substrate with stress relief structure
US8748999B2 (en) * 2012-04-20 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitive sensors and methods for forming the same
US8946884B2 (en) * 2013-03-08 2015-02-03 Xilinx, Inc. Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product
KR102077153B1 (ko) * 2013-06-21 2020-02-14 삼성전자주식회사 관통전극을 갖는 반도체 패키지 및 그 제조방법
KR102094924B1 (ko) * 2013-06-27 2020-03-30 삼성전자주식회사 관통전극을 갖는 반도체 패키지 및 그 제조방법
US9368458B2 (en) * 2013-07-10 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Die-on-interposer assembly with dam structure and method of manufacturing the same
US9412662B2 (en) * 2014-01-28 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and approach to prevent thin wafer crack
US9337154B2 (en) * 2014-08-28 2016-05-10 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method of manufacturing the same
US9520333B1 (en) * 2015-06-22 2016-12-13 Inotera Memories, Inc. Wafer level package and fabrication method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201135820A (en) * 2009-12-01 2011-10-16 Fujitsu Semiconductor Ltd Semiconductor device and method for making the same
US20140360067A1 (en) * 2010-03-02 2014-12-11 Gredo Kahng Method and apparatus for influencing grocery shoppers to make healthy food purchase decisions
TW201230281A (en) * 2010-11-29 2012-07-16 Samsung Electronics Co Ltd Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI670841B (zh) * 2017-04-07 2019-09-01 南韓商三星電子股份有限公司 扇出型感測器封裝以及包含該封裝的光學指紋感測器模組
US10644046B2 (en) 2017-04-07 2020-05-05 Samsung Electronics Co., Ltd. Fan-out sensor package and optical fingerprint sensor module including the same
US11037971B2 (en) 2017-04-07 2021-06-15 Samsung Electronics Co., Ltd. Fan-out sensor package and optical fingerprint sensor module including the same
CN111490004A (zh) * 2019-01-28 2020-08-04 中芯长电半导体（江阴）有限公司 重新布线层的制备方法及半导体结构

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