TWI747404B - 半導體封裝方法及封裝結構 - Google Patents

半導體封裝方法及封裝結構 Download PDF

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TWI747404B
TWI747404B TW109125687A TW109125687A TWI747404B TW I747404 B TWI747404 B TW I747404B TW 109125687 A TW109125687 A TW 109125687A TW 109125687 A TW109125687 A TW 109125687A TW I747404 B TWI747404 B TW I747404B
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Taiwan
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sealing body
carrier
groove
semiconductor
circuit layer
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TW109125687A
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English (en)
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TW202205452A (zh
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郭志明
何榮華
徐佑銘
吳非艱
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頎邦科技股份有限公司
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Priority to TW109125687A priority Critical patent/TWI747404B/zh
Priority to CN202110070598.1A priority patent/CN114068440A/zh
Priority to US17/161,818 priority patent/US11651974B2/en
Priority to KR1020210028732A priority patent/KR20220014800A/ko
Priority to JP2021069248A priority patent/JP7181336B2/ja
Application granted granted Critical
Publication of TWI747404B publication Critical patent/TWI747404B/zh
Publication of TW202205452A publication Critical patent/TW202205452A/zh
Priority to US17/856,039 priority patent/US20220336233A1/en

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Abstract

一種半導體封裝方法包含：設置複數個半導體裝置於一載體上；形成一密封體於該載體上，且該密封體包覆該些半導體裝置，該密封體具有一凹槽，其中該凹槽具有一加強部及一凹部，該加強部凸出於該凹部，且該加強部圍繞該凹部；以及移除該密封體之該凹槽之該加強部。

Description

半導體封裝方法及封裝結構
本發明是關於一種半導體封裝方法，特別是關於一種於半導體之密封體形成凹槽之半導體封裝方法。
半導體封裝(Semiconductor package)是將半導體裝置以環氧樹脂成型材料(Epoxy Molding Compound, EMC)包覆後，再將環氧樹脂成型材料固化為密封體，密封體可用以避免半導體裝置受到外界環境之衝擊、潮濕或靜電之影響。電子裝置目前朝向輕、薄的方向發展，因此以環氧樹脂成型材料固化之密封體會儘量成型為較薄之厚度，但也因為密封體過薄可能導致半導體封裝的強度不足，導致在搬運或是後續製程中產生翹曲(Warpage)。例如，在扇出型晶圓級封裝(Fan-out wafer level packaging)中，藉由重分佈線路(Redistribution layer)將晶片之輸出端點延伸至晶片以外之區域，以增加單一個晶片可輸出之接腳數，但由於薄化之半導體封裝的強度不足，使得重分佈線路與晶片之導接墊之間的對位不易，或是需要晶圓支撐系統承載才可進行加工製程，令製作成本增加。
本發明的主要目的是在密封體上形成凹槽，可在薄化密封體時藉由凹槽之環型加強部維持半導體封裝的強度及平整性，避免半導體封裝結構在後續製程中產生翹曲。
本發明之一種半導體封裝方法包含：設置複數個半導體裝置於一載體上；形成一密封體於該載體上，且該密封體包覆該些半導體裝置，該密封體具有一凹槽，其中該凹槽具有一加強部及一凹部，該加強部凸出於該凹部，且該加強部圍繞該凹部；以及移除該密封體之該凹槽之該加強部。
本發明之一種半導體封裝結構包含一載體、複數個半導體裝置及一密封體，該些半導體裝置設置於該載體上，該密封體設置於該載體上，且該密封體包覆該些半導體裝置，該密封體具有一凹槽，其中該凹槽具有一加強部及一凹部，該加強部凸出於該凹部，且該加強部圍繞該凹部。
本發明藉由於該密封體形成該凹槽，以藉由該凹槽之該加強部維持該密封體的強度及平整性以避免翹曲，此外，透過該加強部提供支撐除了能讓該密封體之該凹部更加薄化外，在後續製程中也不須另外使用晶圓支撐系統，可大幅簡化半導體封裝製程的複雜度。
請參閱第1A至1F圖，為本發明之一第一實施例，一種半導體封裝方法的流程圖，請參閱第1A圖，提供一載體110並以取放製程(pick and place)將複數個半導體裝置120設置於該載體110上，在本實施例中，各該半導體裝置120為一晶片121，該晶片121具有一主動面121a及一背面121b，該主動面121a上具有複數個導接墊121c，該載體110上設置有具有黏性之一黏著層111，使該些晶片121以該主動面121a接觸該載體110時，該些晶片121能夠穩固地黏貼於該載體110上，其中該黏著層111可為暫時接著膠 (Temporary bonding material, TBM)。
請參閱第1B圖，形成一密封體130於該載體110上，該密封體130包覆該些半導體裝置120。在本實施例中，形成該密封體130的製造方法是先提供一模具200，該模具200具有一上模具210及一下模具220；將該載體110及一密封膠設置於該下模組220上，或是分別將該載體110及該密封膠設置於該上模具210及該下模具220上；接著，將該上模具210及該下模具220閉模而形成一模穴230，該模穴230擠壓該密封膠令該密封膠成為該模穴230的形狀並使該密封膠包覆該些半導體裝置120；最後，高溫固化該密封膠而形成該密封體130，其中該上模具210或該下模具220是以圖式中的位置定義，並非實際製程中的上下模。在本實施例中，透過該上模具210或該下模具220的形狀設計，令該模穴230的形狀成為一凹字形而可直接透過上述製程形成具有一凹槽131之該密封體130。或在其他實施例中，可藉由一離型膜(release film)或是設置於該離型膜上的墊片(spacer)改變該模穴230的形狀，其中該離型膜是在該載體110設置於該下模組220前預先鋪設於該上模具210及該下模組220上，以利該密封體130於該模具200開模時脫模，因此，能夠藉由中心厚度較外環圈厚度厚之該離型膜或是設置於該離型膜中心的墊片使該模穴230的形狀為該凹字形，而在該密封膠固化後形成具有該凹槽131之該密封體130。但並非所有的封裝製程皆需要設置該離型膜，因此在另一實施例中，若該密封膠與該墊片之間不會產生反應時，也可以單純設置該墊片於該上模具210或下模具220的中心而改變該膜穴230的形狀為該凹字型。
請參閱第1C圖，接著，將該上模具210及該下模具220開模後即可取出具有該凹槽131之一半導體封裝結構P，該凹槽131具有一加強部131a及一凹部131b，該加強部131a凸出於該凹部131b，且該加強部131a圍繞該凹部131b，該凹部131b具有一槽底面131c。較佳的，該凹部131b之該槽底面131c與該密封體130之一下表面132之間具有一第一間距D1，該第一間距D1小於500 um，以達成該半導體封裝結構P薄化之目的，在本實施例中，該第一間距D1為400 um或500 um，但本發明不在此限。該加強部131a具有一頂面131d，其中該加強部131a之該頂面131d與該下表面132之間具有一第二間距D2，該第二間距D2大於600 um而有著較該凹部131b高之強度，且由於該加強部131a是圍繞整個該凹部131b，可以提供整體結構足夠之強度及平整度，因此在後續製程中能夠不需要另外設置支撐系統而直接對該半導體封裝結構P進行加工，在本實施例中，該第二間距D2為600 um或700 um，但本發明不在此限。
請參閱第6A圖，該半導體封裝結構P可為圓形之晶圓級半導體封裝(wafer level package)，或者，請參閱第6B圖，該半導體封裝結構P可為矩形之面板級封裝(panel level package)，兩種形狀皆可藉由該凹槽131之該凹部131b薄化封裝結構，並藉由該凹槽131之該加強部131a維持封裝結構之強度。
較佳的，請參閱第7圖，透過該模具200之該模穴230形狀的設計，能令該凹槽131之該槽底面131c凸設有複數個加強肋131e，可再進一步地提高該半導體封裝結構P的強度，該些加強肋131e可為任意之形狀或沿著切割道設置。在其他實施例中，亦能夠以二次封裝的方式於該凹槽131之該槽底面131c形成該些加強肋131e。
請參閱第1D圖，接著，將該載體110移除以顯露該些晶片121之該些導接墊121c，並將一重分佈線路層140(redistribution layer)設置於該些晶片121之該主動面121a，該重分佈線路層140電性連接該些導接墊121c。其中，該重分佈線路層140可為透過圖案化光阻層及金屬電鍍製程形成於該些晶片121之該主動面121a上之多層絕緣層及金屬層，其用以將該些晶片121之該些導接墊121c延伸至其他位置，以利於後續之複數個導接元件150的導接。
請參閱第1E圖，將該些導接元件150設置於該重分佈線路層140上，且各該導接元件150經由該重分佈線路層140電性連接各該導接墊121c，在本實施例中，該些導接元件150為銲球(solder ball)，或在其他實施例中，該些導接元件150亦可為凸塊(bump)，本發明並不在此限。
請參閱第1F圖，將該密封體130貼附於一切割膠帶160(dicing tape)上並切割該密封體130以形成複數個半導體封裝元件。較佳的，若使用雷射切割(laser dicing)或晶圓切割鋸(wafer saw blade)進行切割，該密封體130之該加強部131a能夠同時在此步驟中切除，此外，若該凹槽131之該槽底面131c有形成該些加強肋131e，且該些加強肋131e是沿著切割道設置時，該些加強肋131e也能在該密封體130切割的同時被移除，但若該些加強肋131e為任意之圖案時，則需先將該些加強肋131e以研磨工具磨除再進行該密封體130的切割，以避免影響切割時的平整度。
請參閱第2A至2C圖，為本發明之一第二實施例的流程圖，其與第一實施例的差異在於本實施例是以一研磨製程形成該密封體130之該凹槽131，請參閱第2A圖，以取放製程(pick and place)將該些半導體裝置120設置於該載體110之該黏著層111上。接著，請參閱第2B圖，將該載體110設置於該模具200之該模穴230中，並形成該密封體130於該載體110上，該密封體130包覆該些半導體裝置120。請參閱第2C圖，以一研磨工具G對該密封體130進行研磨且避開邊緣的部分，使該密封體130形成該凹槽131之該加強部131a及該凹部131b，由於該加強部131a圍繞該凹部131b，而能夠提供該凹部131b支撐以避免翹曲，並提高該凹部131b之強度及平整性。本實施例後續之製程與第一實施例相同，因此不再贅述。
請參閱第3A至3F圖，為本發明之一第三實施例的流程圖，其與第一實施例的差異在於各該半導體裝置120是以該些晶片121之該背面121b接觸該載體110，該主動面121a具有該些導接凸塊121d，各該導接凸塊121d電性連接各該導接墊121c，此外，本實施例是以一研磨製程形成該密封體130之該凹槽131。
請參閱第3A圖，首先以取放製程(pick and place)將該些半導體裝置120放置於該載體110上，使該些晶片121以該背面121b黏貼於該載體110之該黏著層111上。接著，請參閱第3B圖，將設置有該些半導體裝置120之該載體110設置於該模具200之該模穴230並置入該密封膠於該模穴230中，加溫固化該密封膠以形成該密封體130。請參閱第3C圖，以該研磨工具G對該密封體130進行研磨且避開邊緣的部分，使該密封體130形成該凹槽131之該加強部131a及該凹部131b，由於該加強部131a圍繞該凹部131b，而能夠提供該凹部131b支撐以避免翹曲，並提高該凹部131b之強度及平整性。在本實施例中，該研磨工具G必須研磨至該些晶片121之該些導接凸塊121d顯露於該凹槽131之該槽底面131c。
請參閱第3D圖，將該重分佈線路層140設置於該凹槽131之該槽底面131c，且該重分佈線路層140電性連接該些導接凸塊121d，該重分佈線路層140可為透過圖案化光阻層及金屬電鍍製程形成於該槽底面131c上之多層絕緣層及金屬層。請參閱第3E圖，將該些導接元件150設置於該重分佈線路層140上，各該導接元件150經由該重分佈線路層140電性連接各該導接凸塊121d，在本實施例中，該些導接元件150為銲球，或在其他實施例中，該些導接元件150亦可為凸塊，本發明並不在此限。最後，請參閱第3F圖，將該載體110移除、將該密封體130貼附於該切割膠帶160上並切割該密封體130以形成該些半導體封裝元件。
請參閱第4A至4E圖，為本發明之一第四實施例的流程圖，其與第一實施例的差異在於各該半導體裝置120為該晶片121及該重分佈線路層140，請參閱第4A圖，設置該重分佈線路層140於該載體110上，且該重分佈線路層140之一第一表面141接觸該載體110，該重分佈線路層140可為透過圖案化光阻層及金屬電鍍製程形成於該載體110上之多層絕緣層及金屬層。請參閱第4B圖，將該些晶片121設置於該重分佈線路層140之一第二表面142，該晶片121具有該主動面121a及該背面121b，該主動面121a具有該些導接墊121c及該些導接凸塊121d，該些導接凸塊121d電性連接該些導接墊121c及該重分佈線路層140，使得各該導接墊121c經由各該導接凸塊121d電性連接該重分佈線路層140。
請參閱第4C圖，將設置有該些半導體裝置120之該載體110設置於該模具200之該模穴230並置入該密封膠於該模穴230中，加溫固化該密封膠以形成該密封體130。在本實施例中，透過該上模具210或該下模具220的形狀設計，使得該模穴230的形狀成為一凹字形而可直接注膠及固化形成具有該凹槽131之該密封體130。請參閱第4D圖，移除該載體110並將該些導接元件150設置於重分佈線路層140之該第一表面141，且各該導接元件150經由該重分佈線路層140電性連接各該導接凸塊121d，在本實施例中，該些導接元件150為銲球，或在其他實施例中，該些導接元件150亦可為凸塊，本發明並不在此限。最後，請參閱第4E圖，將該密封體130貼附於該切割膠帶160上並切割該密封體130以形成該些半導體封裝元件。
請參閱第5A至5D圖，為本發明之一第五實施例的流程圖，其與第四實施例的差異在於本實施例是利用研磨製程形成該密封體130之該凹槽131。請參閱第5A圖，相同地，透過圖案化光阻層及金屬電鍍製程形成該重分佈線路層140於該載體110上。接著，請參閱第5B圖，將該晶片121設置於該重分佈線路層140之該第二表面142，該晶片121之該些導接凸塊121d電性連接該些導接墊121c及該重分佈線路層140，使得各該導接墊121c經由各該導接凸塊121d電性連接該重分佈線路層140。接著，請參閱第5C圖，將該載體110設置於該模具200之該模穴230中，並形成該密封體130於該載體110上，且該密封體130包覆該些半導體裝置120。請參閱第5D圖，取出該密封體130並以該研磨工具G對該密封體130進行研磨且避開邊緣的部分，使該密封體130形成該凹槽131之該加強部131a及該凹部131b，由於該加強部131a圍繞該凹部131b而能夠提供該凹部131b支撐以避免翹曲，並提高該凹部131b之強度及平整性。本實施例後續之製程與第四實施例相同，因此不再贅述。
本發明藉由於該密封體130形成該凹槽131，藉由該凹槽131之該加強部131a維持該密封體130的強度及平整性以避免翹曲，以該加強部131a提供支撐除了能讓該密封體130之該凹部131b更加薄化外，在後續製程中也不須另外使用晶圓支撐系統，可大幅簡化半導體封裝製程的複雜度。
本發明之保護範圍當視後附之申請專利範圍所界定者為準，任何熟知此項技藝者，在不脫離本發明之精神和範圍內所作之任何變化與修改，均屬於本發明之保護範圍。
110:載體 111:黏著層 120:半導體裝置 121:晶片 121a:主動面 121b:背面 121c:導接墊 121d:導接凸塊 130:密封體 131:凹槽 131a:加強部 131b:凹部 131c:槽底面 131d:頂面 131e:加強肋 132:下表面 140:重分佈線路層 141:第一表面 142:第二表面 150:導接元件 160:切割膠帶 200:模具 210:上模具 220:下模具 230:模穴 D1:第一間距 D2:第二間距 G:研磨工具 P:半導體封裝結構
第1A-1F圖：依據本發明之一第一實施例，一種半導體封裝方法的流程圖。 第2A-2C圖：依據本發明之一第二實施例，一種半導體封裝方法的流程圖。 第3A-3F圖：依據本發明之一第三實施例，一種半導體封裝方法的流程圖。 第4A-4E圖：依據本發明之一第四實施例，一種半導體封裝方法的流程圖。 第5A-5D圖：依據本發明之一第五實施例，一種半導體封裝方法的流程圖。 第6A、6B圖：依據本發明之一實施例，一半導體封裝結構的立體示意圖。 第7圖：依據本發明之一實施例，一半導體封裝結構的剖視圖。
P:半導體封裝結構
110:載體
111:黏著層
121:晶片
121a:主動面
121c:導接墊
130:密封體
131:凹槽
131a:加強部
131b:凹部
131c:槽底面
131d:頂面
132:下表面
D1:第一間距
D2:第二間距

Claims (16)

  1. 一種半導體封裝方法，其包含：設置複數個半導體裝置於一載體上；形成一密封體於該載體上，且該密封體包覆該些半導體裝置，該密封體具有一凹槽，其中該凹槽具有一加強部及一凹部，該加強部凸出於該凹部，且該加強部圍繞該凹部，其中該凹槽之該加強部及該凹部為同一材料一體製成；以及移除該密封體之該凹槽之該加強部。
  2. 如請求項1之半導體封裝方法，其中該些半導體裝置被包覆於該凹槽之該凹部中。
  3. 如請求項2之半導體封裝方法，其中該加強部中並未包覆有該半導體裝置。
  4. 如請求項1之半導體封裝方法，其中該密封體具有一下表面，該凹部具有一槽底面，其中該凹部之該槽底面與該下表面之間具有一第一間距，該第一間距小於500um，該加強部具有一頂面，其中該加強部之該頂面與該下表面之間具有一第二間距，該第二間距大於600um。
  5. 如請求項1之半導體封裝方法，其中該凹槽之一槽底面凸設有複數個加強肋。
  6. 如請求項1之半導體封裝方法，其包含將該載體移除、將該密封體貼附於一切割膠帶上以及切割該密封體以形成複數個半導體封裝元件。
  7. 如請求項1之半導體封裝方法，其中各該半導體裝置具有一晶片，該晶片具有一主動面及一背面，該主動面接觸該載體，該主動面具有複數個導接墊，該背面被該密封體包覆；形成該密封體於該載體後，移除該載體並將一重分 佈線路層設置於該主動面，且該重分佈線路層電性連接該些導接墊，接著將複數個導接元件設置於該重分佈線路層上，各該導接元件經由該重分佈線路層電性連接各該導接墊。
  8. 如請求項1或7之半導體封裝方法，其中形成該密封體於該載體上包含：提供一模具，該模具具有一模穴；將設置有複數半導體裝置之該載體設置於該模具之該模穴中；置入一密封膠於該模穴中；固化該密封膠以形成該密封體，其中該模穴的形狀為一凹字型而可直接形成具有該凹槽之該密封體。
  9. 如請求項1之半導體封裝方法，其中各該半導體裝置具有一晶片，該晶片具有一主動面及一背面，該背面接觸該載體，該主動面具有複數個導接凸塊，各該導接凸塊電性連接各該導接墊；形成該密封體於該載體後，研磨該密封體之一下表面，使該些導接凸塊顯露於該下表面；接著將一重分佈線路層設置於該下表面，且該重分佈線路層電性連接該些導接凸塊；以及將複數個導接元件設置於該重分佈線路層上，各該導接元件經由該重分佈線路層電性連接各該導接凸塊。
  10. 如請求項1之半導體封裝方法，其中各該半導體裝置具有一晶片及一重分佈線路層，該重分佈線路層之一第一表面接觸該載體，該晶片設置於該重分佈線路層之一第二表面，該晶片具有一主動面及一背面，該主動面具有複數個導接墊及複數個導接凸塊，該些導接凸塊電性連接該些導接墊及該重分佈線路層，各該導接墊經由各該導接凸塊電性連接該重分佈線路層；形成該密封體於該載體後，移除該載體並將複數個導接元件設置於重分佈線路層之該第一表面，且各該導接元件經由該重分佈線路層電性連接各該導接凸塊。
  11. 如請求項1或10之半導體封裝方法，其中形成該密封體於該載體 上包含：提供一模具，該模具具有一模穴；將設置有該些半導體裝置之該載體設置於該模具之該模穴中；置入一密封膠於該模穴中；固化該密封膠以形成該密封體；以及以一研磨製程於該密封體形成該凹槽。
  12. 一種半導體封裝結構，其包含：一載體；複數個半導體裝置，設置於該載體上；以及一密封體，設置於該載體上，且該密封體包覆該些半導體裝置，該密封體具有一凹槽，其中該凹槽具有一加強部及一凹部，該加強部凸出於該凹部，且該加強部圍繞該凹部，其中該凹槽之該加強部及該凹部為同一材料一體製成。
  13. 如請求項12之半導體封裝結構，該些半導體裝置被包覆於該凹槽之該凹部中。
  14. 如請求項13之半導體封裝結構，其中該加強部中並未包覆有該半導體裝置。
  15. 如請求項12之半導體封裝結構，其中該密封體具有一下表面，該凹部具有一槽底面，其中該凹部之該槽底面與該下表面之間具有一第一間距，該第一間距小於500um，該加強部具有一頂面，其中該加強部之該頂面與該下表面之間具有一第二間距，該第二間距大於600um。
  16. 如請求項12之半導體封裝結構，其中該凹槽之一槽底面凸設有複數個加強肋。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150021754A1 (en) * 2009-11-25 2015-01-22 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Thermal Lid for Balancing Warpage and Thermal Management
US20160276238A1 (en) * 2012-09-28 2016-09-22 STATS ChipPAC Pte. Ltd. Semiconductor Device and Method of Forming Supporting Layer Over Semiconductor Die in Thin Fan-Out Wafer Level Chip Scale Package
CN106409699A (zh) * 2015-07-30 2017-02-15 商升特公司 形成小z半导体封装的方法和半导体器件
TW202011539A (zh) * 2018-09-14 2020-03-16 聯發科技股份有限公司 半導體封裝結構及其形成方法
TW202011554A (zh) * 2018-09-11 2020-03-16 台灣積體電路製造股份有限公司 封裝結構

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8610286B2 (en) * 2011-12-08 2013-12-17 Stats Chippac, Ltd. Semiconductor device and method of forming thick encapsulant for stiffness with recesses for stress relief in Fo-WLCSP
US9230894B2 (en) * 2012-05-02 2016-01-05 Infineon Technologies Ag Methods for manufacturing a chip package
JP5998792B2 (ja) * 2012-09-21 2016-09-28 Tdk株式会社 半導体ｉｃ内蔵基板及びその製造方法
US9362191B2 (en) * 2013-08-29 2016-06-07 Infineon Technologies Austria Ag Encapsulated semiconductor device
JP6413935B2 (ja) 2015-06-05 2018-10-31 株式会社デンソー 半導体装置およびその製造方法
US9576931B1 (en) 2016-02-19 2017-02-21 Inotera Memories, Inc. Method for fabricating wafer level package

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150021754A1 (en) * 2009-11-25 2015-01-22 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Thermal Lid for Balancing Warpage and Thermal Management
US20160276238A1 (en) * 2012-09-28 2016-09-22 STATS ChipPAC Pte. Ltd. Semiconductor Device and Method of Forming Supporting Layer Over Semiconductor Die in Thin Fan-Out Wafer Level Chip Scale Package
CN106409699A (zh) * 2015-07-30 2017-02-15 商升特公司 形成小z半导体封装的方法和半导体器件
TW202011554A (zh) * 2018-09-11 2020-03-16 台灣積體電路製造股份有限公司 封裝結構
TW202011539A (zh) * 2018-09-14 2020-03-16 聯發科技股份有限公司 半導體封裝結構及其形成方法

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