US20220336233A1 - Semiconductor package and method of fabricating the same - Google Patents
Semiconductor package and method of fabricating the same Download PDFInfo
- Publication number
- US20220336233A1 US20220336233A1 US17/856,039 US202217856039A US2022336233A1 US 20220336233 A1 US20220336233 A1 US 20220336233A1 US 202217856039 A US202217856039 A US 202217856039A US 2022336233 A1 US2022336233 A1 US 2022336233A1
- Authority
- US
- United States
- Prior art keywords
- encapsulation
- recession
- semiconductor package
- carrier
- recessed portion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 61
- 238000004519 manufacturing process Methods 0.000 title abstract description 15
- 238000005538 encapsulation Methods 0.000 claims abstract description 54
- 238000005728 strengthening Methods 0.000 claims abstract description 29
- 239000000463 material Substances 0.000 description 12
- 239000010410 layer Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 239000002184 metal Substances 0.000 description 6
- 239000012790 adhesive layer Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 229920006336 epoxy molding compound Polymers 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000009517 secondary packaging Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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Definitions
- This invention relates to a method of fabricating a semiconductor package, and more particularly to a method of fabricating a semiconductor package having a recessed encapsulation.
- RDLs redistribution layers
- One object of the present invention is to form a recession on an encapsulation to reduce semiconductor package thickness, and a strengthening portion rimmed the recession enables the thinned semiconductor package to remain enough strength and flatness and mitigate the risk of warpage during subsequent processing procedures.
- a method of fabricating semiconductor package of the present invention includes the steps of: disposing a plurality of semiconductor devices on a carrier; forming an encapsulation on the carrier, the encapsulation is configured to cover the semiconductor devices and includes a recession which includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.
- a semiconductor package of the present invention includes a carrier, a plurality of semiconductor devices and an encapsulation.
- the semiconductor devices are disposed on the carrier.
- the encapsulation is formed on the carrier to cover the semiconductor package.
- the strengthening portion of the recession formed on the encapsulation can make the semiconductor package have sufficient strength and flatness to prevent the occurrence of warpage.
- the recessed portion of the encapsulation can be thinner and a conventional wafer support system is not required during subsequent processing. Thus, the complexity of semiconductor package fabrication can be reduced substantially.
- FIGS. 1A to 1F are diagrams illustrating a method of fabricating a semiconductor package in accordance with a first embodiment of the present invention.
- FIGS. 2A to 2C are diagrams illustrating a method of fabricating a semiconductor package in accordance with a second embodiment of the present invention.
- FIGS. 3A to 3F are diagrams illustrating a method of fabricating a semiconductor package in accordance with a third embodiment of the present invention.
- FIGS. 4A to 4E are diagrams illustrating a method of fabricating a semiconductor package in accordance with a fourth embodiment of the present invention.
- FIGS. 5A to 5D are diagrams illustrating a method of fabricating a semiconductor package in accordance with a fifth embodiment of the present invention.
- FIGS. 6A and 6B are perspective diagrams illustrating semiconductor packages in accordance with different embodiments of the present invention respectively.
- FIG. 7 is a cross-section view diagram illustrating a semiconductor package in accordance with one embodiment of the present invention.
- FIGS. 1A to 1F Processes of fabricating a semiconductor package in accordance with a first embodiment of the present invention are presented in FIGS. 1A to 1F .
- semiconductor devices 120 are picked and placed on a carrier 110
- the semiconductor devices 120 in the first embodiment are chips 121 each having an active surface 121 a and a back surface 121 b , and there are pads 121 c disposed on the active surface 121 a .
- An adhesive layer 111 is applied on the carrier 110 and provided to adhere the chips 121 to the carrier 110 as the active surface 121 a of each of the chips 121 contact with the carrier 110 .
- the adhesive layer 111 is, but not limit to, made of a temporary bonding material (TBM).
- TBM temporary bonding material
- an encapsulation 130 is formed on the carrier 110 to cover the semiconductor devices 120 .
- the encapsulation 130 of the first embodiment is formed by the steps of a) providing a mold 200 which includes a upper mold 210 and a lower mold 220 , b) placing the carrier 110 and an encapsulating material on the lower mold 220 or placing the carrier 110 and the encapsulating material on the upper mold 210 and the lower mold 220 respectively, c) closing the mold 200 to form a mold cavity 230 , the walls of the mold cavity 230 compress and shape the encapsulating material to allow the encapsulating material to cover the semiconductor devices 120 , and d) high-temperature curing the encapsulating material to form the encapsulation 130 .
- the upper mold 210 and the lower mold 220 are the molds located at upper and lower positions in the drawing respectively, not upper movable mold half and lower fixed mold half used in practical production.
- the mold cavity 230 is a U-shaped cavity formed by the profile of the upper mold 210 or the lower mold 220 , thus the encapsulating material is shaped and cured to become the encapsulation 130 having a recession 131 directly.
- a release film or a spacer located on the release film are provided to change the shape of the mold cavity 230 .
- the release film is laid on the upper mold 210 and the lower mold 220 to help release the encapsulation 130 from the mold 200 .
- a release film having a central projection or a flat release film having a spacer at middle enable the mold cavity 230 to have a concave shape such that the encapsulating material is shaped and cured to become the encapsulation 130 having the recession 131 .
- the release film is optional and the spacer can be placed on center of the upper mold 210 or the lower mold 220 to make the mold cavity 230 have a concave shape.
- a semiconductor package P having the recession 131 is separated from the upper mold 210 and the lower mold 220 .
- the recession 131 includes a strengthening portion 131 a and a recessed portion 131 b , the strengthening portion 131 a protrudes from and fringes the recessed portion 131 b , and the recessed portion 131 b has a recession bottom 131 c .
- a first distance D 1 from the recession bottom 131 c of the recessed portion 131 b to a bottom surface 132 of the encapsulation 130 is preferably less than or equal to 500 ⁇ m for thickness reduction of the semiconductor package P.
- the first distance D 1 is, but not limit to, 400 ⁇ m or 500 ⁇ m.
- a second distance D 2 from a top surface 131 d of the strengthening portion 131 a to the bottom surface 132 of the encapsulation 130 is more than or equal to 600 ⁇ m, consequently, the strengthening portion 131 a has a higher strength than the recessed portion 131 b .
- the strengthening portion 131 a surrounding the recessed portion 131 b can offer sufficient strength and flatness so additional support system is not required during subsequent processing procedures of the semiconductor package P.
- the second distance D 2 is, but not limit to, 600 ⁇ m or 700 ⁇ m in the first embodiment.
- the semiconductor package P may be a wafer level package having a circular shape or a panel level package having a rectangular shape. Both of the wafer level package and the panel level package have a reduced thickness due to the formation of the recessed portion 131 b of the recession 131 , and both have a sufficient strength with the help of the strengthening portion 131 a of the recession 131 .
- stiffening ribs 131 e arranged on the recession bottom 131 c of the recession 131 to further enhance the strength of the semiconductor package P, and they may have any shape or be arranged along dicing streets. In other embodiment, the stiffening ribs 131 e are formed on the recession bottom 131 c of the recession 131 during secondary packaging.
- the carrier 110 is removed to expose the pads 121 c of the chips 121 and a redistribution layer (RDL) 140 is disposed on the active surface 121 a of each of the chips 121 to be electrically connected to the pads 121 c .
- the RDL 140 on the active surface 121 a of each of the chips 121 is a multi-layer which includes passive layers and metal layers formed by patterned photoresist and metal plating process.
- the RDL 140 is provided to extend the pads 121 c to other positions for connecting with connectors 150 .
- the connectors 150 are disposed on the RDL 140 to be electrically connected to the pads 121 c via the RDL 140 .
- the connectors 150 are solder balls in the first embodiment, and they may be bumps in other embodiment.
- the encapsulation 130 is adhered to a dicing tape 160 and diced into multiple semiconductor package elements.
- the strengthening portion 131 a of the encapsulation 130 can be removed together while the encapsulation 130 is cut by laser or wafer saw blade.
- the stiffening ribs 131 e formed on the recession bottom 131 c of the recession 131 and arranged along the dicing streets, also can be removed when dicing the encapsulation 130 .
- the stiffening ribs 131 e having any shape and not arranged along the dicing streets need to be grinded and removed before dicing the encapsulation 130 because they may make the flatness of the encapsulation 130 too low to be cut.
- FIGS. 2A to 2C present a method of fabricating a semiconductor package in accordance with a second embodiment of the present invention.
- the encapsulation 130 is grinded to form the recession 131 in the second embodiment.
- the semiconductor devices 120 are picked and placed on the adhesive layer 111 of the carrier 110 .
- the carrier 110 is placed in the mold cavity 230 of the mold 200 and the encapsulation 130 is formed on the carrier 110 to cover the semiconductor devices 120 . As shown in FIG.
- a grinder G is provided to grind the surface of the encapsulation 130 except the rim such that the encapsulation 130 is shaped to generate the recession 131 having the strengthening portion 131 a and the recessed portion 131 b .
- the strengthening portion 131 a surrounding the recessed portion 131 b is provided to support and protect the recessed portion 131 b from warpage and increase the strength and flatness of the recessed portion 131 b .
- the subsequent processes are not repeated here because they are the same as those of the first embodiment.
- the semiconductor devices 120 different from that in the first embodiment, contact with the carrier 110 by the back surface 121 b of each of the chips 121 , and there are bumps 121 d which are disposed on the active surface 121 a of each of the chips 121 and electrically connected to the pads 121 c .
- the recession 131 of the encapsulation 130 is formed by grinding process in the third embodiment.
- the semiconductor devices 120 are picked and placed on the carrier 110 to attach the back surface 121 b of each of the chips 121 to the adhesive layer 111 of the carrier 110 .
- the carrier 110 with the semiconductor devices 120 is placed in the mold cavity 230 of the mold 200 , the encapsulating material is injected into the mold cavity 230 and heated to be cured to thereby form the encapsulation 130 .
- the surface, but not the rim, of the encapsulation 130 is grinded by the grinder G to form the recession 131 having the strengthening portion 131 a and the recessed portion 131 b .
- the recessed portion 131 b is fringed with and supported by the strengthening portion 131 a so as to avoid warpage issue and enhance strength and flatness.
- the grinder G is provided to grind the encapsulation 130 until the bumps 121 d of the chips 121 are exposed on the recession bottom 131 c of the recession 131 .
- the RDL 140 is disposed on the recession bottom 131 c of the recession 131 and electrically connected to the bumps 121 d .
- the RDL 140 on the recession bottom 131 c is a multi-layer comprising passive layers and metal layers fabricated by patterned photoresist and metal plating process.
- the connectors 150 are arranged on the RDL 140 and electrically connected to the bumps 121 d via the RDL 140 .
- the connectors 150 are solder balls in the third embodiment, but they may be bumps in other embodiment.
- the carrier 110 is removed, the encapsulation 130 is adhered to the dicing tape 160 and diced into the semiconductor package elements.
- FIGS. 4A to 4E show a fourth embodiment of the present invention that differs from the first embodiment by the chips 121 of the semiconductor devices 120 and the RDL 140 .
- the RDL 140 which may be made of multiple insulation layers and metal layers by metal-plating using patterned photoresist as mask, is disposed on the carrier 10 and contacts with the carrier 110 by its first surface 141 .
- the chips 121 having the active surface 121 a and the back surface 121 b are mounted on a second surface 142 of the RDL 140 , the pads 121 c and the bumps 121 d are located on the active surface 121 a , the bumps 121 d are electrically connected to the pads 121 c and the RDL 140 such that the pads 121 c are electrically connected to the RDL 140 via the bumps 121 d.
- the carrier 110 and the semiconductor devices 120 thereon are placed in the mold cavity 230 of the mold 200 , and the encapsulating material is injected into the mold cavity 230 and heated to become the encapsulation 130 .
- the mold cavity 230 has a concave shape generated by the profile of the upper mold 210 or the lower mold 220 so that the encapsulation material injected into the mold cavity 230 is cured to become the encapsulation 130 having the recession 131 directly.
- the connectors 150 are disposed on the first surface 141 of the RDL 140 after removing the carrier 110 and are electrically connected to the bumps 121 d via the RDL 140 .
- the connectors 150 may be solder balls (this embodiment) or bumps (other embodiment).
- the encapsulation 130 is attached on the dicing tape 160 to be cut into the semiconductor package elements.
- the recession 131 of the encapsulation 130 is formed by grinding in a fifth embodiment of the present invention presented in FIGS. 5A to 5D .
- the RDL 140 shown in FIG. 5A is also formed on the carrier 110 by metal plating using patterned photoresist mask.
- the chips 121 are mounted on the second surface 142 of the RDL 140 , the bumps 121 d of the chips 121 are electrically connected to the pads 121 c and the RDL 140 , thus the pads 121 c are electrically connected to the RDL 140 via the bumps 121 d.
- the carrier 110 is placed in the mold cavity 230 of the mold 200 , and the encapsulation 130 is formed on the carrier 110 to cover the semiconductor devices 120 .
- the encapsulation 130 is taken out to be grinded by the grinder G, but the rim is not grinded.
- the recession 131 having the strengthening portion 131 a and the recessed portion 131 b is formed on the encapsulation 130 .
- the strengthening portion 131 a surrounding the recessed portion 131 b can support the recessed portion 131 b to reduce the risk of warpage and improve the strength and flatness of the recessed portion 131 b .
- the subsequent processes are identical to the fourth embodiment and not mentioned again here.
- the strengthening portion 131 a of the recession 131 is formed to protect the encapsulation 130 from warpage caused by insufficient strength and flatness and support the recessed portion 131 b . Consequently, the recessed portion 131 b of the encapsulation 130 can be thinned more and not require additional wafer support system.
- the present invention enables a significant simplification of semiconductor package fabrication.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
A method of fabricating a semiconductor package includes the steps of: disposing semiconductor devices on a carrier; forming an encapsulation on the carrier to cover the semiconductor devices, a recession of the encapsulation includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.
Description
- This application is a divisional application of U.S. patent application Ser. No. 17/161,818filed on Jan. 29, 2021, which claims priority under 35 U.S.C. § 119(a) to Patent Application No. 109125687, filed in Taiwan, Republic of China on Jul. 29, 2020, the entire contents of which are hereby incorporated by reference.
- This invention relates to a method of fabricating a semiconductor package, and more particularly to a method of fabricating a semiconductor package having a recessed encapsulation.
- In conventional semiconductor package fabrication, semiconductor devices are embedded in epoxy molding compound (EMC), and the EMC is cured to form an encapsulation which is provided to protect the semiconductor devices from external impact, moisture or static electricity. Electronic devices are getting thinner and lighter so thickness reduction of the encapsulation is necessary. However, a semiconductor package with a too thin encapsulation may have problems of insufficient strength and warpage during delivery or in the subsequent processes. For example, redistribution layers (RDLs) are provided to extend chip's outputs outward to increase output density in fanout wafer level packaging, but bonding of RDLs with chip's pads is not easy if semiconductor package is reduced in thickness with insufficient strength, or a conventional wafer support system is required for subsequent processing following increased costs.
- One object of the present invention is to form a recession on an encapsulation to reduce semiconductor package thickness, and a strengthening portion rimmed the recession enables the thinned semiconductor package to remain enough strength and flatness and mitigate the risk of warpage during subsequent processing procedures.
- A method of fabricating semiconductor package of the present invention includes the steps of: disposing a plurality of semiconductor devices on a carrier; forming an encapsulation on the carrier, the encapsulation is configured to cover the semiconductor devices and includes a recession which includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion; and removing the strengthening portion of the recession of the encapsulation.
- A semiconductor package of the present invention includes a carrier, a plurality of semiconductor devices and an encapsulation. The semiconductor devices are disposed on the carrier. The encapsulation is formed on the carrier to cover the semiconductor package. There is a recession on the encapsulation, and the recession includes a strengthening portion and a recessed portion. The strengthening protrudes from the recessed portion and surrounds the recessed portion.
- The strengthening portion of the recession formed on the encapsulation can make the semiconductor package have sufficient strength and flatness to prevent the occurrence of warpage. In addition, because of the existence of the strengthening portion, the recessed portion of the encapsulation can be thinner and a conventional wafer support system is not required during subsequent processing. Thus, the complexity of semiconductor package fabrication can be reduced substantially.
-
FIGS. 1A to 1F are diagrams illustrating a method of fabricating a semiconductor package in accordance with a first embodiment of the present invention. -
FIGS. 2A to 2C are diagrams illustrating a method of fabricating a semiconductor package in accordance with a second embodiment of the present invention. -
FIGS. 3A to 3F are diagrams illustrating a method of fabricating a semiconductor package in accordance with a third embodiment of the present invention. -
FIGS. 4A to 4E are diagrams illustrating a method of fabricating a semiconductor package in accordance with a fourth embodiment of the present invention. -
FIGS. 5A to 5D are diagrams illustrating a method of fabricating a semiconductor package in accordance with a fifth embodiment of the present invention. -
FIGS. 6A and 6B are perspective diagrams illustrating semiconductor packages in accordance with different embodiments of the present invention respectively. -
FIG. 7 is a cross-section view diagram illustrating a semiconductor package in accordance with one embodiment of the present invention. - Processes of fabricating a semiconductor package in accordance with a first embodiment of the present invention are presented in
FIGS. 1A to 1F . With reference toFIG. 1A ,semiconductor devices 120 are picked and placed on acarrier 110, thesemiconductor devices 120 in the first embodiment arechips 121 each having anactive surface 121 a and aback surface 121 b, and there arepads 121 c disposed on theactive surface 121 a. Anadhesive layer 111 is applied on thecarrier 110 and provided to adhere thechips 121 to thecarrier 110 as theactive surface 121 a of each of thechips 121 contact with thecarrier 110. Theadhesive layer 111 is, but not limit to, made of a temporary bonding material (TBM). - With reference to
FIG. 1B , anencapsulation 130 is formed on thecarrier 110 to cover thesemiconductor devices 120. Theencapsulation 130 of the first embodiment is formed by the steps of a) providing amold 200 which includes aupper mold 210 and alower mold 220, b) placing thecarrier 110 and an encapsulating material on thelower mold 220 or placing thecarrier 110 and the encapsulating material on theupper mold 210 and thelower mold 220 respectively, c) closing themold 200 to form amold cavity 230, the walls of themold cavity 230 compress and shape the encapsulating material to allow the encapsulating material to cover thesemiconductor devices 120, and d) high-temperature curing the encapsulating material to form theencapsulation 130. Please note that theupper mold 210 and thelower mold 220 are the molds located at upper and lower positions in the drawing respectively, not upper movable mold half and lower fixed mold half used in practical production. In the first embodiment, themold cavity 230 is a U-shaped cavity formed by the profile of theupper mold 210 or thelower mold 220, thus the encapsulating material is shaped and cured to become theencapsulation 130 having arecession 131 directly. In other embodiment, a release film or a spacer located on the release film are provided to change the shape of themold cavity 230. Before placing thecarrier 110 on thelower mold 220, the release film is laid on theupper mold 210 and thelower mold 220 to help release theencapsulation 130 from themold 200. Preferably, a release film having a central projection or a flat release film having a spacer at middle enable themold cavity 230 to have a concave shape such that the encapsulating material is shaped and cured to become theencapsulation 130 having therecession 131. If the spacer is not reactive with the encapsulating material, the release film is optional and the spacer can be placed on center of theupper mold 210 or thelower mold 220 to make themold cavity 230 have a concave shape. - With reference to
FIG. 1C , a semiconductor package P having therecession 131 is separated from theupper mold 210 and thelower mold 220. Therecession 131 includes a strengtheningportion 131 a and arecessed portion 131 b, the strengtheningportion 131 a protrudes from and fringes therecessed portion 131 b, and therecessed portion 131 b has arecession bottom 131 c. A first distance D1 from therecession bottom 131 c of therecessed portion 131 b to abottom surface 132 of theencapsulation 130 is preferably less than or equal to 500 μm for thickness reduction of the semiconductor package P. In this embodiment, the first distance D1 is, but not limit to, 400 μm or 500 μm. A second distance D2 from atop surface 131 d of the strengtheningportion 131 a to thebottom surface 132 of theencapsulation 130 is more than or equal to 600 μm, consequently, the strengtheningportion 131 a has a higher strength than the recessedportion 131 b. The strengtheningportion 131 a surrounding therecessed portion 131 b can offer sufficient strength and flatness so additional support system is not required during subsequent processing procedures of the semiconductor package P. The second distance D2 is, but not limit to, 600 μm or 700 μm in the first embodiment. - With reference to
FIGS. 6A and 6B , the semiconductor package P may be a wafer level package having a circular shape or a panel level package having a rectangular shape. Both of the wafer level package and the panel level package have a reduced thickness due to the formation of therecessed portion 131 b of therecession 131, and both have a sufficient strength with the help of the strengtheningportion 131 a of therecession 131. - As shown in
FIG. 7 , there arestiffening ribs 131 e arranged on therecession bottom 131 c of therecession 131 to further enhance the strength of the semiconductor package P, and they may have any shape or be arranged along dicing streets. In other embodiment, thestiffening ribs 131 e are formed on therecession bottom 131 c of therecession 131 during secondary packaging. - With reference to
FIG. 1D , thecarrier 110 is removed to expose thepads 121 c of thechips 121 and a redistribution layer (RDL) 140 is disposed on theactive surface 121 a of each of thechips 121 to be electrically connected to thepads 121 c. TheRDL 140 on theactive surface 121 a of each of thechips 121 is a multi-layer which includes passive layers and metal layers formed by patterned photoresist and metal plating process. TheRDL 140 is provided to extend thepads 121 c to other positions for connecting withconnectors 150. - With reference to
FIG. 1E , theconnectors 150 are disposed on theRDL 140 to be electrically connected to thepads 121 c via theRDL 140. Theconnectors 150 are solder balls in the first embodiment, and they may be bumps in other embodiment. - With reference to
FIG. 1F , theencapsulation 130 is adhered to adicing tape 160 and diced into multiple semiconductor package elements. The strengtheningportion 131 a of theencapsulation 130 can be removed together while theencapsulation 130 is cut by laser or wafer saw blade. Thestiffening ribs 131e, formed on therecession bottom 131 c of therecession 131 and arranged along the dicing streets, also can be removed when dicing theencapsulation 130. On the other hand, the stiffeningribs 131 e having any shape and not arranged along the dicing streets need to be grinded and removed before dicing theencapsulation 130 because they may make the flatness of theencapsulation 130 too low to be cut. -
FIGS. 2A to 2C present a method of fabricating a semiconductor package in accordance with a second embodiment of the present invention. Different to the first embodiment, theencapsulation 130 is grinded to form therecession 131 in the second embodiment. With reference toFIG. 2A , thesemiconductor devices 120 are picked and placed on theadhesive layer 111 of thecarrier 110. Subsequently, with reference toFIG. 2B , thecarrier 110 is placed in themold cavity 230 of themold 200 and theencapsulation 130 is formed on thecarrier 110 to cover thesemiconductor devices 120. As shown inFIG. 2C , a grinder G is provided to grind the surface of theencapsulation 130 except the rim such that theencapsulation 130 is shaped to generate therecession 131 having the strengtheningportion 131 a and the recessedportion 131 b. The strengtheningportion 131 a surrounding the recessedportion 131 b is provided to support and protect the recessedportion 131 b from warpage and increase the strength and flatness of the recessedportion 131 b. The subsequent processes are not repeated here because they are the same as those of the first embodiment. - In a third embodiment of the present invention as shown in
FIGS. 3A to 3F , thesemiconductor devices 120, different from that in the first embodiment, contact with thecarrier 110 by theback surface 121 b of each of thechips 121, and there arebumps 121 d which are disposed on theactive surface 121 a of each of thechips 121 and electrically connected to thepads 121 c. Additionally, therecession 131 of theencapsulation 130 is formed by grinding process in the third embodiment. - With reference to
FIG. 3A , thesemiconductor devices 120 are picked and placed on thecarrier 110 to attach theback surface 121 b of each of thechips 121 to theadhesive layer 111 of thecarrier 110. With reference toFIG. 3B , thecarrier 110 with thesemiconductor devices 120 is placed in themold cavity 230 of themold 200, the encapsulating material is injected into themold cavity 230 and heated to be cured to thereby form theencapsulation 130. With reference toFIG. 3C , the surface, but not the rim, of theencapsulation 130 is grinded by the grinder G to form therecession 131 having the strengtheningportion 131 a and the recessedportion 131 b. The recessedportion 131 b is fringed with and supported by the strengtheningportion 131 a so as to avoid warpage issue and enhance strength and flatness. In the third embodiment, the grinder G is provided to grind theencapsulation 130 until thebumps 121 d of thechips 121 are exposed on therecession bottom 131 c of therecession 131. - With reference to
FIG. 3D , theRDL 140 is disposed on therecession bottom 131 c of therecession 131 and electrically connected to thebumps 121 d. TheRDL 140 on therecession bottom 131 c is a multi-layer comprising passive layers and metal layers fabricated by patterned photoresist and metal plating process. With reference toFIG. 3E , theconnectors 150 are arranged on theRDL 140 and electrically connected to thebumps 121 d via theRDL 140. Theconnectors 150 are solder balls in the third embodiment, but they may be bumps in other embodiment. Finally, with reference toFIG. 3F , thecarrier 110 is removed, theencapsulation 130 is adhered to the dicingtape 160 and diced into the semiconductor package elements. -
FIGS. 4A to 4E show a fourth embodiment of the present invention that differs from the first embodiment by thechips 121 of thesemiconductor devices 120 and theRDL 140. With reference toFIG. 4A , theRDL 140, which may be made of multiple insulation layers and metal layers by metal-plating using patterned photoresist as mask, is disposed on the carrier 10 and contacts with thecarrier 110 by itsfirst surface 141. With reference toFIG. 4B , thechips 121 having theactive surface 121 a and theback surface 121 b are mounted on asecond surface 142 of theRDL 140, thepads 121 c and thebumps 121 d are located on theactive surface 121 a, thebumps 121 d are electrically connected to thepads 121 c and theRDL 140 such that thepads 121 c are electrically connected to theRDL 140 via thebumps 121d. - With reference to
FIG. 4C , thecarrier 110 and thesemiconductor devices 120 thereon are placed in themold cavity 230 of themold 200, and the encapsulating material is injected into themold cavity 230 and heated to become theencapsulation 130. In the fourth embodiment, themold cavity 230 has a concave shape generated by the profile of theupper mold 210 or thelower mold 220 so that the encapsulation material injected into themold cavity 230 is cured to become theencapsulation 130 having therecession 131 directly. With reference toFIG. 4D , theconnectors 150 are disposed on thefirst surface 141 of theRDL 140 after removing thecarrier 110 and are electrically connected to thebumps 121 d via theRDL 140. Theconnectors 150 may be solder balls (this embodiment) or bumps (other embodiment). With reference toFIG. 4E , theencapsulation 130 is attached on the dicingtape 160 to be cut into the semiconductor package elements. - Different to the fourth embodiment, the
recession 131 of theencapsulation 130 is formed by grinding in a fifth embodiment of the present invention presented inFIGS. 5A to 5D . TheRDL 140 shown inFIG. 5A is also formed on thecarrier 110 by metal plating using patterned photoresist mask. With reference toFIG. 5B , thechips 121 are mounted on thesecond surface 142 of theRDL 140, thebumps 121 d of thechips 121 are electrically connected to thepads 121 c and theRDL 140, thus thepads 121 c are electrically connected to theRDL 140 via thebumps 121d. Next, with reference toFIG. 5C , thecarrier 110 is placed in themold cavity 230 of themold 200, and theencapsulation 130 is formed on thecarrier 110 to cover thesemiconductor devices 120. With reference toFIG. 5D , theencapsulation 130 is taken out to be grinded by the grinder G, but the rim is not grinded. As a result, therecession 131 having the strengtheningportion 131 a and the recessedportion 131 b is formed on theencapsulation 130. The strengtheningportion 131 a surrounding the recessedportion 131 b can support the recessedportion 131 b to reduce the risk of warpage and improve the strength and flatness of the recessedportion 131 b. The subsequent processes are identical to the fourth embodiment and not mentioned again here. - Because of the
recession 131 on theencapsulation 130, the strengtheningportion 131 a of therecession 131 is formed to protect theencapsulation 130 from warpage caused by insufficient strength and flatness and support the recessedportion 131 b. Consequently, the recessedportion 131 b of theencapsulation 130 can be thinned more and not require additional wafer support system. The present invention enables a significant simplification of semiconductor package fabrication. - While this invention has been particularly illustrated and described in detail with respect to the preferred embodiments thereof, it will be clearly understood by those skilled in the art that is not limited to the specific features shown and described and various modified and changed in form and details may be made without departing from the scope of the claims.
Claims (5)
1. A semiconductor package comprising:
a carrier;
a plurality of semiconductor devices disposed on the carrier; and
an encapsulation disposed on the carrier and configured to cover the plurality of semiconductor devices, the encapsulation includes a recession, wherein the recession includes a strengthening portion and a recessed portion, the strengthening portion protrudes from the recessed portion and surrounds the recessed portion.
2. The semiconductor package in accordance with claim 1 , wherein the plurality of semiconductor devices are embedded in the recessed portion of the recession.
3. The semiconductor package in accordance with claim 2 , wherein the plurality of the semiconductor devices are not embedded in the strengthening portion.
4. The semiconductor package in accordance with claim 1 , wherein a first distance exists between a recession bottom of the recessed portion and a bottom surface of the encapsulation and is less than or equal to 500 μm, and a second distance exists between a top surface of the strengthening portion and the bottom surface of the encapsulation and is more than or equal to 600 μm.
5. The semiconductor package in accordance with claim 1 , wherein a plurality of stiffening ribs are disposed on a recession bottom of the recession.
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US17/856,039 US20220336233A1 (en) | 2020-07-29 | 2022-07-01 | Semiconductor package and method of fabricating the same |
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US20140061944A1 (en) * | 2011-12-08 | 2014-03-06 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP |
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US9202769B2 (en) * | 2009-11-25 | 2015-12-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming thermal lid for balancing warpage and thermal management |
US9230894B2 (en) * | 2012-05-02 | 2016-01-05 | Infineon Technologies Ag | Methods for manufacturing a chip package |
JP5998792B2 (en) * | 2012-09-21 | 2016-09-28 | Tdk株式会社 | Semiconductor IC-embedded substrate and manufacturing method thereof |
US9385102B2 (en) * | 2012-09-28 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming supporting layer over semiconductor die in thin fan-out wafer level chip scale package |
US9362191B2 (en) * | 2013-08-29 | 2016-06-07 | Infineon Technologies Austria Ag | Encapsulated semiconductor device |
JP6413935B2 (en) | 2015-06-05 | 2018-10-31 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
US9899285B2 (en) * | 2015-07-30 | 2018-02-20 | Semtech Corporation | Semiconductor device and method of forming small Z semiconductor package |
US9576931B1 (en) * | 2016-02-19 | 2017-02-21 | Inotera Memories, Inc. | Method for fabricating wafer level package |
US11164839B2 (en) * | 2018-09-11 | 2021-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of manufacturing the same |
US11450606B2 (en) * | 2018-09-14 | 2022-09-20 | Mediatek Inc. | Chip scale package structure and method of forming the same |
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US20140061944A1 (en) * | 2011-12-08 | 2014-03-06 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in FO-WLCSP |
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TW202205452A (en) | 2022-02-01 |
TWI747404B (en) | 2021-11-21 |
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