KR20140137535A - Integrated circuit package and method for manufacturing the same - Google Patents

Integrated circuit package and method for manufacturing the same Download PDF

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KR20140137535A
KR20140137535A KR1020130058079A KR20130058079A KR20140137535A KR 20140137535 A KR20140137535 A KR 20140137535A KR 1020130058079 A KR1020130058079 A KR 1020130058079A KR 20130058079 A KR20130058079 A KR 20130058079A KR 20140137535 A KR20140137535 A KR 20140137535A
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semiconductor chip
substrate
dividing
semiconductor
forming
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KR1020130058079A
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Korean (ko)
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최대식
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에스티에스반도체통신 주식회사
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Priority to KR1020130058079A priority Critical patent/KR20140137535A/en
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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Abstract

본 발명은 집적회로 패키지 제조방법에 관한 것이다.
본 발명에 따른 집적회로 패키지 제조방법은 (A) 기판의 제1면에 복수의 반도체 칩을 탑재하는 과정과; (B) 상기 반도체 칩 전체를 밀봉하도록 상기 기판의 제1면 상에 보호층을 형성하는 과정과; (C) 상기 복수의 반도체 칩 사이에 상기 기판을 관통하고, 상기 보호층이 부분적으로 제거되도록 분할홈을 형성하되, 이후 상기 반도체 칩의 두께 조절을 위한 공정시 상기 분할홈에 의해 개별 다이로 분할될 수 있는 깊이로 상기 분할홈을 형성하는 과정과; (D) 상기 기판의 제2면 상에 보호필름을 부착하는 과정과; (E) 상기 반도체 칩의 배면 및 상기 보호층의 일부를 제거하되, 적어도 상기 분할홈의 깊이까지 제거하여 상기 반도체 칩의 두께를 조절하는 과정; 및 (F) 상기 보호필름을 제거하는 과정을 포함하는 것을 특징으로 한다. The present invention relates to a method of manufacturing an integrated circuit package.
A method of manufacturing an integrated circuit package according to the present invention includes the steps of: (A) mounting a plurality of semiconductor chips on a first surface of a substrate; (B) forming a protective layer on the first surface of the substrate to seal the entire semiconductor chip; (C) dividing grooves formed through the substrate between the plurality of semiconductor chips so as to partially remove the protective layer, and dividing the semiconductor chip into individual dies by the dividing grooves in a process for adjusting the thickness of the semiconductor chip, Forming the dividing groove at a depth to which the dividing groove can be formed; (D) attaching a protective film on the second side of the substrate; (E) adjusting a thickness of the semiconductor chip by removing at least a depth of the dividing groove by removing a back surface of the semiconductor chip and a portion of the protective layer; And (F) removing the protective film.

Description

집적회로 패키지 제조방법{INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MANUFACTURING THE SAME} [0001] INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MANUFACTURING THE SAME [0002]

본 발명은 집적회로 패키지 제조방법에 관한 것으로, 특히 집적회로 패키지 제조시 발생하는 워페이지(warpage)를 감소시킬 수 있는 집적회로 패키지 제조방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing an integrated circuit package, and more particularly, to a method of manufacturing an integrated circuit package capable of reducing warpage occurring in manufacturing an integrated circuit package.

근래, 전자 기기의 고기능화 및 경박단소화의 요구에 따라, 전자 부품의 고밀도 집적화 및 고밀도 실장화가 진행되고 있고, 이들 전자 기기에 사용되는 반도체 패키지는 점점 더 소형화가 진행되고 있다.2. Description of the Related Art In recent years, as electronic devices have become more sophisticated and slimmer and thinner, electronic components have been increasingly integrated with higher density and higher density mounting. Semiconductor packages used in these electronic devices have become more and more miniaturized.

이러한 상황 아래, 반도체 패키지 분야에서는, 기존의 리드 프레임을 사용한 형태의 패키지에서는 소형화에 한계가 있기 때문에, 최근에는 회로 기판상에 칩을 실장한 볼 그리드 어레이(BGA), 칩 스케일 패키지(CSP)와 같은 에어리어 실장형 패키지 방식이 제안되어 있다. 이들 반도체 패키지에 있어서, BGA에 탑재되는 반도체 칩을 기판에 접속하는 방식에는, 와이어 본딩 방식이나 TAB(Tape Automated Bonding) 방식, 또한 플립 칩(FC) 방식 등이 알려져 있지만, 최근에는, 반도체 패키지의 소형화에 유리한 플립칩 접속 방식을 이용한 BGA나 CSP의 구조가 활발히 제안되고 있다.Under such circumstances, in the semiconductor package field, there is a limit to miniaturization in a package using a conventional lead frame. Recently, a ball grid array (BGA), a chip scale package (CSP) And the same area mounting type package method is proposed. In these semiconductor packages, a wire bonding method, a TAB (Tape Automated Bonding) method, a flip chip (FC) method, or the like is known as a method of connecting a semiconductor chip mounted on a BGA to a substrate. A structure of a BGA or a CSP using a flip chip connection method which is advantageous for miniaturization has been actively proposed.

한편, 기판상에 반도체 칩을 실장한 반도체 패키지가 사용되고 있다. 이러한 반도체 패키지에 사용되는 기판으로서는, 코어층과, 빌드업층을 구비하는 것이 사용되고 있다.On the other hand, a semiconductor package in which a semiconductor chip is mounted on a substrate is used. As a substrate used in such a semiconductor package, a core layer and a buildup layer are used.

기판과 반도체 칩은, 일반적으로 선팽창 계수가 다르다. 기판은 유기 수지를 포함하는 재료에 의해 구성되어 있고, 반도체 칩보다 큰 선팽창계수를 가진다. 이 때문에, 기판 상에 반도체 칩을 실장한 구조의 반도체 패키지가 열이력을 받으면 양자의 선팽창 계수 차이로 인해 기판이 휘게 되는 워페이지(warpage)가 발생한다. 이러한 워페이지 발생으로 인해 반도체 칩이나, 반도체 칩과 범프의 계면, 범프와 기판의 계면 등에, 크랙이나 박리가 발생할 뿐만 아니라 솔더볼(solder ball)을 정확한 위치에 안착하기 어렵게 하는 등 반도체 패키지를 형성하기 위한 후속 공정의 진행을 어렵게 하여 반도체 패키지의 양산성 및 작업성을 확보하기 힘들게 하는 문제점이 있다. The substrate and the semiconductor chip generally have different coefficients of linear expansion. The substrate is made of a material containing an organic resin and has a linear expansion coefficient larger than that of the semiconductor chip. Therefore, when a semiconductor package having a structure in which a semiconductor chip is mounted on a substrate receives a thermal history, a warpage occurs in which the substrate is warped due to a difference in coefficient of linear expansion between the two. Such warpage may cause cracks or peeling at the interface between the semiconductor chip and the semiconductor chip and the bump, the interface between the bump and the substrate, and the like, and it may be difficult to form the semiconductor package, Which makes it difficult to secure the mass productivity and workability of the semiconductor package.

따라서, 집적회로 패키지의 워페이지를 감소시키기 위해 다양한 해결책이 제안되고 있는데, 대한민국 공개특허 10-2009-0092786에 개시된 바와 같이 대부분 기판의 재료나 몰딩 재료를 변경하는 등 재료(material)적인 관점에서 해결책을 모색하고 있어 제조비용이 많이 소요될 뿐만 아니라 워페이지 감소에 한계가 따르는 문제점이 있다.
Accordingly, various solutions have been proposed to reduce the warpage of an integrated circuit package. As disclosed in Korean Patent Laid-Open No. 10-2009-0092786, in many cases, a solution from a material point of view, So that not only the manufacturing cost is high but also there is a limitation in reducing the warpage.

대한민국 공개특허 10-2009-0092786Korean Patent Publication No. 10-2009-0092786

따라서, 본 발명은 상기와 같은 종래기술의 문제점을 해결하기 위하여 안출된 것으로, 본 발명의 일반적인 목적은 종래 기술에서의 한계와 단점에 의해 발생되는 다양한 문제점을 실질적으로 보완할 수 있는 집적회로 패키지 제조방법을 제공하기 위한 것이다. SUMMARY OF THE INVENTION Accordingly, it is a general object of the present invention to provide an integrated circuit package which can substantially complement various problems caused by limitations and disadvantages of the prior art. Method.

본 발명의 보다 구체적인 다른 목적은 집적회로 패키지 제조시 비용을 증가시키지 않으면서 워패이지(warpage)를 개선할 수 있는 집적회로 패키지 제조방법을 제공하기 위한 것이다.It is yet another specific object of the present invention to provide a method of manufacturing an integrated circuit package capable of improving warpage without increasing the cost in manufacturing an integrated circuit package.

본 발명의 보다 구체적인 다른 목적은 웨이퍼 레벨 패키지 제조시 워패이지(warpage)를 개선할 수 있는 집적회로 패키지 제조방법을 제공하기 위한 것이다.
A further specific object of the present invention is to provide a method of manufacturing an integrated circuit package capable of improving warpage in manufacturing a wafer level package.

이를 위해 본 발명의 일 실시예에 따른 집적회로 패키지 제조방법은 (A) 기판의 제1면에 복수의 반도체 칩을 탑재하는 과정과; (B) 상기 반도체 칩 전체를 밀봉하도록 상기 기판의 제1면 상에 보호층을 형성하는 과정과; (C) 상기 복수의 반도체 칩 사이에 상기 기판을 관통하고, 상기 보호층이 부분적으로 제거되도록 분할홈을 형성하되, 이후 상기 반도체 칩의 두께 조절을 위한 공정시 상기 분할홈에 의해 개별 다이로 분할될 수 있는 깊이로 상기 분할홈을 형성하는 과정과; (D) 상기 기판의 제2면 상에 보호필름을 부착하는 과정과; (E) 상기 반도체 칩의 배면 및 상기 보호층의 일부를 제거하되, 적어도 상기 분할홈의 깊이까지 제거하여 상기 반도체 칩의 두께를 조절하는 과정; 및 (F) 상기 보호필름을 제거하는 과정을 포함하는 것을 특징으로 한다. To this end, an integrated circuit package manufacturing method according to an embodiment of the present invention includes the steps of (A) mounting a plurality of semiconductor chips on a first surface of a substrate; (B) forming a protective layer on the first surface of the substrate to seal the entire semiconductor chip; (C) dividing grooves formed through the substrate between the plurality of semiconductor chips so as to partially remove the protective layer, and dividing the semiconductor chip into individual dies by the dividing grooves in a process for adjusting the thickness of the semiconductor chip, Forming the dividing groove at a depth to which the dividing groove can be formed; (D) attaching a protective film on the second side of the substrate; (E) adjusting a thickness of the semiconductor chip by removing at least a depth of the dividing groove by removing a back surface of the semiconductor chip and a portion of the protective layer; And (F) removing the protective film.

본 발명의 일 실시예에 따른 집적회로 패키지 제조방법은, 상기 (B) 과정과 상기 (C) 과정 사이에 (G) 상기 기판의 제2면에 솔더볼을 형성하는 과정을 더 포함할 수 있다. The method of manufacturing an integrated circuit package according to an embodiment of the present invention may further include forming a solder ball on the second surface of the substrate between the step (B) and the step (C).

본 발명의 일 실시예에 따른 집적회로 패키지 제조방법에서, 상기 (E) 과정은 백그라인딩 공정에 의해 이루어질 수 있다. In the method of manufacturing an integrated circuit package according to an embodiment of the present invention, the step (E) may be performed by a backgrinding process.

본 발명의 일 실시예에 따른 집적회로 패키지 제조방법에서, 상기 복수의 반도체 칩은 플립칩 공정에 의해 상기 기판의 제1면에 탑재될 수 있다. In the method of manufacturing an integrated circuit package according to an embodiment of the present invention, the plurality of semiconductor chips may be mounted on the first surface of the substrate by a flip chip process.

본 발명의 일 실시예에 따른 집적회로 패키지 제조방법에서, 상기 기판은In an integrated circuit package manufacturing method according to an embodiment of the present invention,

인쇄회로기판일 수 있다. May be a printed circuit board.

또한, 본 발명의 다른 실시예에 따른 집적회로 패키지 제조방법은, (a) 캐리어 상에 복수의 반도체 칩을 배열하는 과정과; (b) 상기 반도체 칩 전체를 밀봉하도록 상기 캐리어의 제1면 상에 보호층을 형성하는 과정과; (c) 상기 캐리어를 제거한 다음 상기 반도체 칩 상에 빌드업층(build-up layers)을 적층하는 과정과; (d) 상기 복수의 반도체 칩 사이에 상기 빌드업층을 관통하고, 상기 보호층이 부분적으로 제거되도록 분할홈을 형성하되, 이후 상기 반도체 칩의 두께 조절을 위한 공정시 상기 분할홈에 의해 개별 다이로 분할될 수 있는 깊이로 상기 분할홈을 형성하는 과정과; (e) 상기 빌드업층의 배면에 보호필름을 부착하는 과정과; (f) 상기 반도체 칩의 배면 및 상기 보호층의 일부를 제거하되, 적어도 상기 분할홈의 깊이까지 제거하여 상기 반도체 칩의 두께를 조절하는 과정; 및 (g) 상기 보호필름을 제거하는 과정을 포함하는 것을 특징으로 한다. According to another aspect of the present invention, there is provided a method of manufacturing an integrated circuit package including the steps of: (a) arranging a plurality of semiconductor chips on a carrier; (b) forming a protective layer on the first surface of the carrier to seal the entire semiconductor chip; (c) stacking build-up layers on the semiconductor chip after removing the carrier; (d) forming dividing grooves through the build-up layer between the plurality of semiconductor chips so that the protective layer is partially removed, and then dividing the semiconductor die by dividing grooves into separate dies Forming the dividing groove at a depth that can be divided; (e) attaching a protective film to the back surface of the build-up layer; (f) adjusting a thickness of the semiconductor chip by removing at least a depth of the dividing groove by removing a back surface of the semiconductor chip and a part of the protective layer; And (g) removing the protective film.

본 발명의 다른 실시예에 따른 집적회로 패키지 제조방법은, 상기 (c) 과정과 상기 (d) 과정 사이에 (h) 상기 빌드업층의 배면에 솔더볼을 형성하는 과정을 더 포함할 수 있다. The method of fabricating an integrated circuit package according to another embodiment of the present invention may further include the step of (h) forming a solder ball on the backside of the buildup layer between the step (c) and the step (d).

본 발명의 다른 실시예에서, 상기 (f) 과정은 백그라인딩 공정에 의해 이루어질 수 있다.
In another embodiment of the present invention, the step (f) may be performed by a backgrinding process.

본 발명에 따른 집적회로 패키지 제조방법에 의하면, 개별 칩을 연마하기 전에 패키지를 개별 다이로 분리하기 위한 분할홈을 부분적으로 형성한 다음 그라인딩(연마) 하여 개별 다이로 분리함으로써 종래에 비해 두꺼운 다이와 몰드를 사용할 수 있어 취급이 용이할 뿐만 아니라 워페이지를 크게 감소시킬 수 있다. According to the method of manufacturing an integrated circuit package according to the present invention, the dividing grooves for separating the package into individual dies are partially formed before grinding individual chips, and then the individual grooves are separated by grinding (polishing) It is easy to handle and the warpage can be greatly reduced.

또한, 본 발명에 따른 집적회로 패키지 제조방법에 의하면, 워페이지 현상이 방지됨으로써 반도체 패키지를 형성하기 위한 후속 공정의 진행을 용이하게 수행할 수 있어 반도체 패키지의 양산성 및 작업성을 확보할 수 있다.In addition, according to the method of manufacturing an integrated circuit package according to the present invention, since the warpage phenomenon is prevented, the subsequent process for forming the semiconductor package can be easily performed, thereby ensuring mass production and operability of the semiconductor package .

또한, 본 발명에 따른 집적회로 패키지 제조방법에 의하면, 저렴한 비용으로 워페이지 현상을 개선할 수 있어 반도체 패키지 제조비용을 절감할 수 있다.In addition, according to the method of manufacturing an integrated circuit package according to the present invention, the warpage phenomenon can be improved at a low cost and the manufacturing cost of the semiconductor package can be reduced.

또한, 본 발명에 따른 집적회로 패키지 제조방법에 의하면, 배면 그라인딩 공정에 의해 반도체 칩이 몰드 외부로 노출되므로 방열특성을 개선하고, 반도체 칩을 외부로 노출시키기 위한 필름 어시스트 몰드(FAM)가 필요하지 않아 제조비용을 절감할 수 있다.
Further, according to the method of manufacturing an integrated circuit package according to the present invention, since the semiconductor chip is exposed to the outside of the mold by the back grinding process, a film assist mold (FAM) for exposing the semiconductor chip to the outside is required So that the manufacturing cost can be reduced.

도 1a 내지 도 1f는 본 발명의 일 실시예에 따른 집적회로 패키지 제조과정을 나타낸 단면도이다.
도 2a 내지 도 2g는 본 발명의 다른 실시예에 따른 집적회로 패키지 제조과정을 나타낸 단면도이다.1A to 1F are cross-sectional views illustrating an integrated circuit package manufacturing process according to an exemplary embodiment of the present invention.
2A to 2G are cross-sectional views illustrating an integrated circuit package manufacturing process according to another embodiment of the present invention.

이하, 첨부 도면을 참조하여 본 발명의 실시 예를 상세히 설명하면 다음과 같다. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

본 발명을 설명함에 있어서, 관련된 공지기능 혹은 구성에 대한 구체적인 설명이 본 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우 그 상세한 설명은 생략한다. 또한, 후술되는 용어들은 본 발명에서의 기능을 고려하여 정의된 용어들로서 이는 사용자의 의도 또는 판례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다. In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. In addition, the terms described below are defined in consideration of the functions of the present invention, and these may vary depending on the intention or precedent of the user. Therefore, the definition should be based on the contents throughout this specification.

도 1a 내지 도 1f는 본 발명의 일 실시예에 따른 집적회로 패키지 제조과정을 나타낸 단면도이다. 1A to 1F are cross-sectional views illustrating an integrated circuit package manufacturing process according to an exemplary embodiment of the present invention.

먼저, 도 1a에 도시된 바와 같이 기판(100) 상면에 반도체 칩(110)을 플립칩 본딩한다. 상기 기판(100)은 배선 단자(101), 외부 단자(102) 및 배선 단자(101)와 외부 단자(102)를 전기적으로 연결하는 비아콘택(103)을 구비하는 인쇄회로기판이 될 수 있다. 또한, 상기 반도체 칩(110)은 회로패턴(미도시)이 아래쪽을 향하도록 페이스-다운(face down) 형태로 도전성 범프(111)를 통해 인쇄회로기판의 배선단자(101)와 플립칩 본딩될 수 있다. First, as shown in FIG. 1A, a semiconductor chip 110 is flip-chip bonded to an upper surface of a substrate 100. The substrate 100 may be a printed circuit board having a via contact 103 for electrically connecting the wiring terminal 101, the external terminal 102 and the wiring terminal 101 to the external terminal 102. The semiconductor chip 110 is flip-chip bonded to the wiring terminal 101 of the printed circuit board through the conductive bumps 111 in a face-down manner such that a circuit pattern (not shown) .

다음으로, 도 1b에 도시된 바와 같이 인캡슐레이션(encapsulation) 공정을 통해 기판(100)의 상면 및 반도체 칩(110)에 전체적으로 보호층(120)을 형성한다. 상기 보호층(120)은 기판(100) 및 반도체 칩(110)을 외부환경으로부터 보호하기 위한 것으로, 인캡슐레이션 공정에 의해 형성되므로 별도의 언더필 공정을 진행하지 않고도 기판(100)과 반도체 칩(110) 사이를 봉지재로 밀봉할 수 있다. 여기서, 봉지재는 예를 들면, 인캡슐런트(encapsulant), 에폭시 몰딩 컴파운드(Epoxy Molding Compound: EMC) 또는 그 등가물로 구성될 수 있다. Next, as shown in FIG. 1B, a passivation layer 120 is formed on the upper surface of the substrate 100 and the semiconductor chip 110 as a whole through an encapsulation process. The protective layer 120 protects the substrate 100 and the semiconductor chip 110 from the external environment and is formed by an encapsulation process so that the substrate 100 and the semiconductor chip 110 110 can be sealed with an encapsulating material. Here, the sealing material may be composed of, for example, an encapsulant, an epoxy molding compound (EMC), or the like.

다음으로, 도 1c에 도시된 바와 같이 기판(100) 배면에 솔더볼(130)을 부착한다. 상기 솔더볼(130)은 기판(100)을 마더보드 등의 외부회로(미도시)와 전기적으로 연결하기 위한 것이다.Next, a solder ball 130 is attached to the back surface of the substrate 100 as shown in FIG. The solder ball 130 is for electrically connecting the substrate 100 to an external circuit (not shown) such as a mother board.

다음으로, 도 1d에 도시된 바와 같이 각 반도체 칩(110) 사이의 기판(100) 및 보호층(120)을 부분적으로 제거하여 분할홈(140)을 형성한다. 여기서, 기판(100) 및 보호층(120)의 제거는 예를 들면, 블레이드(blade)를 사용하여 이루어질 수 있으며, 분할홈(140)의 깊이는 이후 반도체 칩(110) 두께를 감소시키기 위한 백그라인딩 공정시 개개의 다이로 분리(분할)될 수 있을 정도의 깊이가 되도록 한다. 즉, 백그라인딩 공정시 반도체 칩(110)이 'C선'까지 제거되는 경우 보호층(120)은 적어도 'C선'보다 아래쪽 깊이까지 제거되며, 분할홈(140)의 바닥이 'C선' 보다 아래쪽에 위치하도록 분할홈(140)이 형성된다. Next, as shown in FIG. 1D, the substrate 100 and the protective layer 120 between the semiconductor chips 110 are partially removed to form the dividing grooves 140. Here, the substrate 100 and the protective layer 120 may be removed by using, for example, a blade, and the depth of the dividing groove 140 may be reduced by a thickness of the semiconductor chip 110, So that it is deep enough to be separated (divided) by individual dies during the grinding process. That is, when the semiconductor chip 110 is removed to the 'C line' during the back grinding process, the protective layer 120 is removed to a depth lower than at least the 'C line', and the bottom of the split groove 140 ' The dividing groove 140 is formed so as to be located at a lower position.

다음으로, 도 1e에 도시된 바와 같이 반도체 칩(110)의 배면 및 보호층(120)을 그라인딩 하여 원하는 두께의 반도체 칩(110)을 형성한다. 이때, 솔더볼(130)이 형성된 면의 기판(100) 상에 기판(100) 및 솔더볼(130)을 보호하기 위한 보호필름(150)을 부착한 다음 그라인드 휠(grind wheel) 등을 이용하여 반도체 칩(110) 배면을 그라인딩 한다. Next, as shown in FIG. 1E, the back surface of the semiconductor chip 110 and the protective layer 120 are ground to form a semiconductor chip 110 having a desired thickness. At this time, a protective film 150 for protecting the substrate 100 and the solder ball 130 is attached on the substrate 100 on the side where the solder ball 130 is formed, and then the semiconductor chip 100 is ground using a grind wheel, (110).

다음으로, 도 1f에 도시된 바와 같이 보호필름(150)을 제거하여 개별 다이(200a, 200b, 200c)로 분리(singulation)한다.Next, as shown in FIG. 1F, the protective film 150 is removed and singulated by the individual dies 200a, 200b, and 200c.

이와 같이, 본 실시예에서는 반도체 패키지 제조시 기판 배면에 분할홈을 형성하여 부분적으로 분리한 후 백그라인딩을 진행하여 개별 다이로 분리함으로써 패키지의 워페이지를 감소시킬 수 있다. 즉, 선다이싱(Dicing Before Grinding: DBG) 공정과 유사하게 패키지를 개별 다이로 분리하기 전에 분할홈을형성하여 부분적으로 분할한 후 백그라인딩 공정을 진행함으로써 기존에 비해 두꺼운 다이와 몰드를 사용할 수 있어 취급이 용이할 뿐만 아니라 공정진행 중의 워페이지를 감소시킬 수 있다. 참고로, 선다이싱법(DBG : Dicing Before Grinding)은 웨이퍼를 보다 얇은 다이로 분할하는 분할기술로서, 반도체 웨이퍼의 상면으로부터 분할 예정 라인을 따라 정해진 깊이(다이의 마무리 두께에 상당하는 깊이)의 분할홈을 형성하고, 그 후, 표면에 분할홈이 형성된 반도체 웨이퍼의 배면을 그라인딩 해서 개개의 다이로 분할하는 기술이다. 선다이싱법에 의하면 다이의 두께를 100 ㎛ 이하로 가공할 수 있다. As described above, in the present embodiment, the dividing grooves are formed on the back surface of the substrate during the manufacturing of the semiconductor package, and the divided grooves are partially separated, and then the back grinding is performed and separated into individual dies. In other words, similar to the Dicing Before Grinding (DBG) process, the dividing grooves are formed before the package is separated into individual dies, and the divided dies and molds can be used And it is possible to reduce the number of warp pages during the process. For reference, Dicing Before Grinding (DBG) is a dividing technique for dividing a wafer into thinner dies. The dividing technique divides a predetermined depth (a depth corresponding to the finishing thickness of the die) along the line to be divided from the upper surface of the semiconductor wafer A groove is formed and then the back surface of the semiconductor wafer having the dividing grooves formed on its surface is grinded and divided into individual dies. According to the die dicing method, the thickness of the die can be reduced to 100 占 퐉 or less.

또한, 본 실시예에 의하면 배면 그라인딩 공정에 의해 반도체 칩이 몰드 외부로 노출되므로 방열특성 개선 및 반도체 칩을 외부로 노출시키기 위한 필름 어시스트 몰드(FAM)가 필요하지 않아 비용 절감의 효과를 얻을 수 있다.According to the present embodiment, since the semiconductor chip is exposed to the outside of the mold by the back grinding process, the film assist mold (FAM) for improving the heat dissipation characteristics and exposing the semiconductor chip to the outside is not required, .

한편, 워페이지는 인쇄회로기판을 이용한 패키지 제조시보다 박막 패키지(thin PKG) 또는 웨이퍼 레벨 패키지(wafer level PKG) 제조시에 더 심각한 문제로 대두되며, 본 발명은 이러한 초박막 패키지 제조시에도 유용하게 적용될 수 있다. On the other hand, the warp page becomes a more serious problem in manufacturing a thin PKG or a wafer level PKG than in the case of manufacturing a package using a printed circuit board, and the present invention is also useful for manufacturing such an ultra-thin package Can be applied.

도 2a 내지 도 2g는 본 발명의 다른 실시예에 따른 집적회로 패키지 제조과정을 나타낸 단면도로서, 본 실시예는 웨이퍼 레벨 패키지 제조시에 적용된 예를 설명하기 위한 것이다.FIGS. 2A to 2G are cross-sectional views illustrating an integrated circuit package manufacturing process according to another embodiment of the present invention, which is an example applied in manufacturing a wafer level package.

먼저, 도 2a에 도시된 바와 같이 캐리어(310)에 다수의 반도체 칩(320)을 배열한다. 여기서, 캐리어(310)는 다수의 반도체 칩(320)을 지지하기 위한 지지부재로서, 이후 캐리어(310) 제거(remove)가 용이하도록 이형층(315)을 구비할 수 있다. First, a plurality of semiconductor chips 320 are arranged on a carrier 310 as shown in FIG. 2A. Here, the carrier 310 is a support member for supporting a plurality of semiconductor chips 320, and may be provided with a release layer 315 to facilitate removal of the carrier 310 thereafter.

다음으로, 도 2b에 도시된 바와 같이 인캡슐레이션(encapsulation) 공정을 통해 반도체 칩(320) 전체를 덮도록 보호층(330)을 형성한다. 상기 보호층(330)은 반도체 칩(320)을 고정 및 외부환경으로부터 보호하기 위해 봉지재로 밀봉한 것이다. 여기서, 봉지재는 예를 들면, 인캡슐런트(encapsulant), 에폭시 몰딩 컴파운드(EMC) 또는 그 등가물로 이루어질 수 있다. Next, as shown in FIG. 2B, a passivation layer 330 is formed to cover the entire semiconductor chip 320 through an encapsulation process. The protection layer 330 is encapsulated with an encapsulating material to secure the semiconductor chip 320 and protect it from the external environment. Here, the encapsulant may comprise, for example, an encapsulant, an epoxy molding compound (EMC), or the like.

다음으로, 도 2c에 도시된 바와 같이 캐리어(310)와 이형지(315)를 제거한 다음 반도체 칩(320) 상에 빌드업층(build-up layers)(340)을 적층한다. 여기서, 빌드업층(340)은 유기 유전체 및 패턴화된 도전층을 PWB 라미네이팅된 코어의 한족 또는 양쪽에 추가함으로써 형성되는 층들이 될 수 있다. Next, as shown in FIG. 2C, the carrier 310 and the release paper 315 are removed, and build-up layers 340 are stacked on the semiconductor chip 320. Next, as shown in FIG. Here, the buildup layer 340 may be layers formed by adding an organic dielectric and a patterned conductive layer to one or both of the PWB laminated cores.

다음으로, 도 2d에 도시된 바와 같이 빌드업층(340) 위에 솔더볼(350)을 부착한다. 상기 솔더볼(350)은 각각의 다이를 마더보드 등의 외부회로(미도시)와 전기적으로 연결하기 위한 것이다. Next, a solder ball 350 is attached on the buildup layer 340 as shown in FIG. 2D. The solder ball 350 is for electrically connecting each die to an external circuit (not shown) such as a mother board or the like.

다음으로, 도 2e에 도시된 바와 같이 각 반도체 칩(320) 사이의 빌드업층(340) 및 보호층(330)을 부분적으로 제거하여 분할홈(360)을 형성한다. 여기서, 빌드업층(340) 및 보호층(330)의 제거는 예를 들면, 블레이드(blade)를 사용하여 이루어질 수 있으며, 분할홈(360)의 깊이는 이후 반도체 칩(320) 두께를 감소시키기 위한 백그라인딩 공정시 개개의 다이로 분리될 수 있을 정도의 깊이가 되도록 한다. Next, as shown in FIG. 2E, the build-up layer 340 and the protective layer 330 between the semiconductor chips 320 are partially removed to form the dividing grooves 360. Here, the removal of the build-up layer 340 and the protective layer 330 may be performed using, for example, a blade, and the depth of the split trench 360 may be adjusted by a method for reducing the thickness of the semiconductor chip 320 The back grinding process should be such that it can be separated into individual dies.

다음으로, 도 2f에 도시된 바와 같이 반도체 칩(320)의 배면 및 보호층(330)을 그라인딩 하여 원하는 두께의 반도체 칩(320)을 형성한다. 이때, 솔더볼(350)이 형성된 면의 빌드업층(340) 상에 빌드업층(340) 및 솔더볼(350)을 보호하기 위한 보호필름(370)을 부착한 다음 그라인드 휠(grind wheel) 등을 이용하여 반도체 칩(320) 배면을 백그라인딩 한다. Next, as shown in FIG. 2F, the rear surface of the semiconductor chip 320 and the protective layer 330 are ground to form a semiconductor chip 320 having a desired thickness. At this time, a buildup layer 340 and a protective film 370 for protecting the solder ball 350 are attached on the buildup layer 340 on the surface where the solder ball 350 is formed, and then a grinding wheel or the like is used The back surface of the semiconductor chip 320 is back-grounded.

다음으로, 도 2g에 도시된 바와 같이 보호필름(370)을 제거하여 개별 다이(300a, 300b, 300c)로 분리(singulation)한다.Next, as shown in FIG. 2G, the protective film 370 is removed and singulated by the individual dies 300a, 300b, and 300c.

전술한 바와 같이 본 실시예에서는 반도체 패키지 제조시 개별 다이로 분리하기 전에 빌드업층 및 보호층에 분할홈을 형성하여 부분적으로 분리한 후 백그라인딩을 진행하여 개별 다이로 분리함으로써 패키지의 워페이지를 감소시킬 수 있다. As described above, in this embodiment, the dividing grooves are formed in the build-up layer and the protective layer before the semiconductor die is separated into individual dies in the semiconductor package manufacturing process. .

또한, 본 실시예에 의하면 배면 그라인딩 공정에 의해 반도체 칩이 몰드 외부로 노출되므로 방열특성 개선 및 반도체 칩을 외부로 노출시키기 위한 필름 어시스트 몰드(FAM)가 필요하지 않아 비용 절감의 효과를 얻을 수 있다.According to the present embodiment, since the semiconductor chip is exposed to the outside of the mold by the back grinding process, the film assist mold (FAM) for improving the heat dissipation characteristics and exposing the semiconductor chip to the outside is not required, .

한편, 본 발명의 상세한 설명 및 첨부도면에서는 구체적인 실시예에 관해 설명하였으나, 본 발명은 개시된 실시예에 한정되지 않고 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다. 따라서, 본 발명의 범위는 설명된 실시예에 국한되어 정해져서는 안되며 후술하는 특허청구범위뿐만 아니라 이 특허청구범위와 균등한 것들을 포함하는 것으로 해석되어야 할 것이다.
While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and similarities. Accordingly, the scope of the present invention should be construed as being limited to the embodiments described, and it is intended that the scope of the present invention encompasses not only the following claims, but also equivalents thereto.

100 : 인쇄회로기판 110, 320 : 반도체 칩
120, 330 : 보호층 130, 350 : 솔더볼
140, 360 : 분할홈 150, 370 : 보호필름
310 : 캐리어 340 : 빌드업층
100a~100c, 300a~300c : 개별 다이100: printed circuit board 110, 320: semiconductor chip
120, 330: protection layer 130, 350: solder ball
140, 360: division grooves 150, 370: protective film
310: Carrier 340: Buildup layer
100a to 100c, 300a to 300c: individual die

Claims (8)

(A) 기판의 제1면에 복수의 반도체 칩을 탑재하는 과정과;
(B) 상기 반도체 칩 전체를 밀봉하도록 상기 기판의 제1면 상에 보호층을 형성하는 과정과;
(C) 상기 복수의 반도체 칩 사이에 상기 기판을 관통하고, 상기 보호층이 부분적으로 제거되도록 분할홈을 형성하되, 이후 상기 반도체 칩의 두께 조절을 위한 공정시 상기 분할홈에 의해 개별 다이로 분할될 수 있는 깊이로 상기 분할홈을 형성하는 과정과;
(D) 상기 기판의 제2면 상에 보호필름을 부착하는 과정과;
(E) 상기 반도체 칩의 배면 및 상기 보호층의 일부를 제거하되, 적어도 상기 분할홈의 깊이까지 제거하여 상기 반도체 칩의 두께를 조절하는 과정; 및
(F) 상기 보호필름을 제거하는 과정을 포함하는 것을 특징으로 하는 집적회로 패키지 제조방법.
(A) mounting a plurality of semiconductor chips on a first surface of a substrate;
(B) forming a protective layer on the first surface of the substrate to seal the entire semiconductor chip;
(C) forming a dividing groove through the substrate between the plurality of semiconductor chips so that the protective layer is partially removed, and then dividing the semiconductor chip into individual dies by the dividing groove in a process for adjusting the thickness of the semiconductor chip, Forming the dividing groove at a depth to which the dividing groove can be formed;
(D) attaching a protective film on the second side of the substrate;
(E) adjusting a thickness of the semiconductor chip by removing at least a depth of the dividing groove by removing a back surface of the semiconductor chip and a portion of the protective layer; And
(F) removing the protective film.
제 1 항에 있어서, 상기 (B) 과정과 상기 (C) 과정 사이에
(G) 상기 기판의 제2면에 솔더볼을 형성하는 과정을 더 포함하는 것을 특징으로 하는 집적회로 패키지 제조방법.
The method according to claim 1, further comprising, during the step (B) and the step (C)
(G) forming a solder ball on the second surface of the substrate.
제 1 항에 있어서, 상기 (E) 과정은
백그라인딩 공정에 의해 이루어지는 것을 특징으로 하는 집적회로 패키지 제조방법.
The method of claim 1, wherein the step (E)
And a back grinding process.
제 1 항에 있어서, 상기 복수의 반도체 칩은
플립칩 공정에 의해 상기 기판의 제1면에 탑재되는 것을 특징으로 하는 집적회로 패키지 제조방법.
The semiconductor device according to claim 1, wherein the plurality of semiconductor chips
And is mounted on a first surface of the substrate by a flip chip process.
제 4 항에 있어서, 상기 기판은
인쇄회로기판인 것을 특징으로 하는 집적회로 패키지 제조방법.
The method of claim 4, wherein the substrate
Wherein the printed circuit board is a printed circuit board.
(a) 캐리어 상에 복수의 반도체 칩을 배열하는 과정과;
(b) 상기 반도체 칩 전체를 밀봉하도록 상기 캐리어의 제1면 상에 보호층을 형성하는 과정과;
(c) 상기 캐리어를 제거한 다음 상기 반도체 칩 상에 빌드업층(build-up layers)을 적층하는 과정과;
(d) 상기 복수의 반도체 칩 사이에 상기 빌드업층을 관통하고, 상기 보호층이 부분적으로 제거되도록 분할홈을 형성하되, 이후 상기 반도체 칩의 두께 조절을 위한 공정시 상기 분할홈에 의해 개별 다이로 분할될 수 있는 깊이로 상기 분할홈을 형성하는 과정과;
(e) 상기 빌드업층의 배면에 보호필름을 부착하는 과정과;
(f) 상기 반도체 칩의 배면 및 상기 보호층의 일부를 제거하되, 적어도 상기 분할홈의 깊이까지 제거하여 상기 반도체 칩의 두께를 조절하는 과정; 및
(g) 상기 보호필름을 제거하는 과정을 포함하는 것을 특징으로 하는 집적회로 패키지 제조방법.
(a) arranging a plurality of semiconductor chips on a carrier;
(b) forming a protective layer on the first surface of the carrier to seal the entire semiconductor chip;
(c) stacking build-up layers on the semiconductor chip after removing the carrier;
(d) forming dividing grooves through the build-up layer between the plurality of semiconductor chips so that the protective layer is partially removed, and then dividing the semiconductor die by dividing grooves into separate dies Forming the dividing groove at a depth that can be divided;
(e) attaching a protective film to the back surface of the build-up layer;
(f) adjusting a thickness of the semiconductor chip by removing at least a depth of the dividing groove by removing a back surface of the semiconductor chip and a part of the protective layer; And
(g) removing the protective film. < RTI ID = 0.0 > 11. < / RTI >
제 6 항에 있어서, 상기 (c) 과정과 상기 (d) 과정 사이에
(h) 상기 빌드업층의 배면에 솔더볼을 형성하는 과정을 더 포함하는 것을 특징으로 하는 집적회로 패키지 제조방법.
7. The method of claim 6, further comprising, between (c) and (d)
(h) forming a solder ball on the backside of the build-up layer.
제 6 항에 있어서, 상기 (f) 과정은
백그라인딩 공정에 의해 이루어지는 것을 특징으로 하는 집적회로 패키지 제조방법.7. The method of claim 6, wherein step (f)
And a back grinding process.
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KR20180077028A (en) * 2016-12-28 2018-07-06 가부시기가이샤 디스코 Method of manufacturing semiconductor package

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20180077028A (en) * 2016-12-28 2018-07-06 가부시기가이샤 디스코 Method of manufacturing semiconductor package

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