CN103367245A - 形成半导体器件的方法 - Google Patents

形成半导体器件的方法 Download PDF

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CN103367245A
CN103367245A CN2013101131886A CN201310113188A CN103367245A CN 103367245 A CN103367245 A CN 103367245A CN 2013101131886 A CN2013101131886 A CN 2013101131886A CN 201310113188 A CN201310113188 A CN 201310113188A CN 103367245 A CN103367245 A CN 103367245A
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wafer
via hole
reproduces
reproduce
stacking
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霍斯特·托伊斯
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明公开了一种形成半导体器件的方法。在一个实施例中，半导体器件形成方法包括堆叠第一晶圆和第二晶圆、以及在第二晶圆堆叠有第一晶圆的同时，形成延伸通过第二晶圆的贯穿过孔。在另一个实施例中，形成半导体器件的方法包括将第一晶圆单个化成第一多个晶片中、以及在具有第二多个晶片的第二晶圆上附接第一多个晶片。该方法进一步包括在第二晶圆上附接第一多个晶片之后，形成延伸通过第一多个晶片中的晶片的贯穿过孔。

Description

形成半导体器件的方法
技术领域
本发明主要涉及半导体器件，并在具体实施例中，涉及三维（3D）集成电路及其形成方法。
背景技术
半导体器件在许多电子方面和其它应用中使用。半导体器件包括在半导体晶圆（wafer）上形成的集成电路。
半导体器件通过在半导体工件或晶圆上方沉积多种不同类型的材料层，并使用光刻（lithography）对各种材料层图案化而制造。材料层通常包括导电、半导电和绝缘材料的薄膜，这些材料被图案化并被蚀刻从而形成集成电路（IC）。例如，可以有形成在单个晶片（die）或芯片上的多个晶体管、存储器件、开关、导线、二极管、电容器、逻辑电路和其它电子部件。
在集成电路制造之后，从晶圆上单个化（分离，singulated）得到单独的晶片，且通常地，晶片被封装。多年以来，最常见的封装晶片的方式是水平放置在单独的塑料或陶瓷封装内。可替换地，多个晶片可以在单个封装中水平地封装，形成一多芯片模块。可在晶片的终端或结合垫上进行电连接，例如使用非常小股的线来进行电连接，所述线被导引到封装的引脚。
具有更高性能的较小IC的需求已导致芯片上系统型（system-on-a-chip）器件的发展，其中芯片的部分用于存储器，且其它部分用于逻辑电路或其它类型电路。然而，由于不同电路制造技术的集成问题，可能难以制造具有多种类型电路的IC。
半导体工业的一个趋势是朝向三维集成电路（3D-IC）发展，例如其中，两个或更多个芯片或晶圆堆叠并竖直地集成。电路的一些部分在不同的晶圆上制造，且晶圆或晶片用胶层（诸如基于铜或聚合物的粘合剂）结合在一起。不同类型的电路（作为例子，例如为存储器和逻辑电路）可单独地制造并然后竖直地附接，这可以相比于在单个晶圆上将两个电路技术组合于芯片上系统型器件中来说更便宜并更易于制造。3D-IC预计未来用于低功率高速应用，因为导通路径可以通过电路之间的竖直电连接而被缩短，这使得功耗低且速度高。
半导体器件制造商不断努力提高其产品性能，同时降低制造成本。由于相关的设计和制造挑战，3D封装在半导体器件制造中是成本密集型领域。
发明内容
通过本发明说明性实施例，这些和其它问题被总体上解决或规避，并且总体上实现技术优点。
根据本发明的实施例，一种形成半导体器件的方法包括：堆叠第一晶圆和第二晶圆；以及在第二晶圆堆叠有第一晶圆的同时，形成延伸通过第二晶圆的贯穿孔。该方法进一步包括通过用导电材料填充贯穿孔形成贯穿过孔。
根据本发明的另一个实施例，一种形成半导体器件的方法包括：提供第一再造晶圆，该第一再造晶圆包括嵌入在第一封装物内的第一多个晶片；以及提供第二再造晶圆，第二再造晶圆包括嵌入在第二封装物内的第二多个晶片。该方法进一步包括堆叠第一再造晶圆和第二再造晶圆，并形成延伸通过第二再造晶圆的贯穿过孔。在第一再造晶圆保持堆叠有第二再造晶圆的同时，形成该贯穿过孔。
根据本发明的另一个实施例，一种形成半导体器件的方法包括将第一晶圆单个化成第一多个晶片；以及在包括第二多个晶片的第二晶圆上附接第一多个晶片。该方法进一步包括，在第二晶圆上附接第一多个晶片之后，形成延伸通过第一多个晶片中的晶片的贯穿过孔。
上述已经较广泛地概述了本发明实施例的特征，以便可以更好地理解如下的本发明的详细描述。本发明实施例的其它特征和优点将在下文描述，其形成本发明的权利要求主题。本领域那些技术人员应该理解，公开的概念和具体实施例可易于用作用于修改或设计用于实施本发明相同目的其它结构或过程的基础。本领域那些技术人员也应该意识到，这类等同构造不背离权利要求所述的本发明精神和保护范围。
附图说明
为了更完整地理解本发明及其优点，现参考结合附图的以下描述，附图中：
图1-4描述了根据本发明实施例的形成具有贯穿衬底过孔的堆叠半导体晶片的方法；
图5-7示出了形成堆叠半导体器件的可替换实施例，所述堆叠半导体器件利用背对背（back-to-back）接合形成并具有用于互连晶片的贯穿过孔；
图8-11示出了形成具有贯穿过孔的堆叠半导体器件的可替换实施例；
图12-22示出了堆叠半导体器件的制造，所述堆叠半导体器件包括互相堆叠的并使用贯穿衬底过孔连接的多个扇出型（fan-out）封装；
图23A和23B示出了形成具有多个堆叠晶片的3D集成扇出型封装的进一步实施例；
图24A-24E示出了形成具有多个堆叠晶片的3D集成封装的进一步实施例，其中图24A-24D示出了扇出型封装，而图24E示出了堆叠的半导体芯片；
图25示出了根据本发明实施例的包括堆叠芯片的引线框架（leadframe）封装；以及
图26A和26B示出了在本发明各种实施例中堆叠晶片的倒装芯片（flip-chip）安装。
除非另有说明，否则不同图中的相应的数字和符号一般指相应的部件。图被绘制成清楚地示出实施例的相关方面，且不必要等比例地绘制。
具体实施方式
在下面详细讨论各种实施例的实施和使用。然而应该理解，本发明提供许多可应用的发明概念，其可在广泛的特定背景中实现。讨论的具体实施例仅说明用于实施和使用本发明的具体方式，并不限制本发明的保护范围。
本发明的实施例克服了将多个不同芯片堆叠到单个封装中以由此形成3D集成电路的问题。实施例使用低成本贯穿过孔实现，所述低成本贯穿过孔在堆叠晶圆上全局地形成，极大地降低了处理成本。本发明的实施例在多个堆叠晶圆上方同时形成贯穿过孔，而不是在每个晶片上方单独地形成贯穿过孔，从而极大地降低了处理成本。
利用图1-4描述根据本发明实施例的制造堆叠半导体晶片的方法。利用图5-7描述制造堆叠背对背半导体晶片的可替换实施例。利用图8-10描述制造堆叠晶片的另一个可替换实施例。利用图12-22描述形成堆叠半导体封装的可替换实施例，所述堆叠半导体封装使用嵌入式晶圆级封装工艺。利用图23A-24E描述形成堆叠半导体封装的进一步实施例，所述堆叠半导体封装使用嵌入式晶圆级封装工艺。利用图25描述应用到引线框架封装的本发明实施例。利用图26A和26B描述应用到倒装芯片的本发明实施例。正如也将再次描述的，各种实施例的特征可以组合到一起。
图1-4描述了根据本发明实施例的形成堆叠半导体晶片的方法，所述堆叠半导体晶片具有贯穿衬底过孔。
图1示出在所有的前端和后端处理之后，具有多个晶片的衬底10。前端处理是指有源器件区域的形成，而后端处理是指金属化层的形成从而互连集成电路的各种器件。换句话说，第一晶圆1是具有多个晶片的处理后的晶圆，所述多个晶片包括形成于晶片中的金属化部。例如，在一个或多个实施例中，衬底10包括具有位于前侧上的晶片阵列的晶圆。在各种实施例中，衬底10可以是硅合金和化合物半导体。在一些实施例中，衬底10可以是具有族III和族V元素的III-V衬底，或衬底10可以是具有族II和族VI元素的II-VI衬底。在一个或多个实施例中，衬底10可以是蓝宝石上硅（蓝宝石硅，silicon-on-sapphire）（SOS）衬底。在一个或多个实施例中，衬底10可以是绝缘体上锗（germanium-on-insulator，GeOI）衬底。在一个或多个实施例中，衬底10可包含一种或多种半导体材料，诸如硅、锗硅、锗、砷化镓、砷化铟、氮化镓、砷化镓铟、或锑化铟。
多个晶片可包括具有集成电路或分立器件不同类型的晶片。在一个或多个实施例中，衬底10中的多个晶片可包括逻辑芯片、存储器芯片、模拟芯片、混合信号芯片及它们的组合，如芯片上系统。多个晶片可包括各种类型的有源和无源器件，如二极管、晶体管、晶闸管、电容器、电感器、电阻器、光电器件、传感器、微机电系统、和其它器件。
触点30可形成为用于将晶片电连接到外部源上。触点30可通过互连金属化部（未示出）耦接到衬底10。钝化层或保护层20设置在衬底10的前侧上。在一个实施例中，保护层20可以是氧化物（诸如二氧化硅）层。在其它实施例中，保护层20可包括其它介电材料，诸如氮化物、氮氧化硅。因此，触点30可设置在保护层20内。
从后侧对衬底10进行薄化。在各种实施例中，在薄化之后衬底10的厚度为约20μm至约100μm，且在一个实施例中是80μm至约120μm。在另一个实施例中，在薄化之后衬底10的厚度为约50μm至约100μm。在另一个实施例中，在薄化之后衬底10的厚度为约20μm至约50μm。在另一个实施例中，在薄化之后衬底10的厚度为约10μm至约20μm。在另一个实施例中，在薄化之后衬底10的厚度是至少10μm。在另一个实施例中，在薄化之后衬底10的厚度是至少20μm。在另一个实施例中，在薄化之后衬底10的厚度是至少50μm。在另一个实施例中，在薄化之后衬底10的厚度小于100μm。在另一个实施例中，在薄化之后衬底10的厚度小于80μm。在另一个实施例中，在薄化之后衬底10的厚度小于50μm。在另一个实施例中，在薄化之后衬底10的厚度小于30μm。衬底10的最后厚度可基于机械稳定性、减小电阻的需要及其它而选择。
接着如图2中示出，多个薄化的衬底10（例如第一晶圆1、第二晶圆2，第三晶圆3和第四晶圆4）彼此堆叠。在各种实施例中，相同类型的晶圆堆叠。例如，在一个实施例中，第一晶圆1和第二晶圆2包括存储器芯片。在可替换实施例中，不同类型的晶圆可堆叠。例如，在一个实施例中，第一晶圆1包括逻辑芯片，而第二晶圆2包括存储器芯片。类似地，在一些实施例中，晶圆中的一个可包括模拟芯片，而其它晶圆中的一个包括逻辑芯片或存储器芯片。在一个实施例中，第一晶圆1、第二晶圆2、第三晶圆3和第四晶圆4可以是逻辑芯片、存储器芯片、模拟芯片、混合信号芯片及芯片上系统中的一个或多个。
有利地，堆叠薄化晶圆提供了用于后续处理所需的机械稳定性。另外，形成贯穿过孔的开口的纵横比（aspect ratio）是工艺兼容的（因为薄化）。
晶圆的堆叠使用任何合适的方法接合。在一个实施例中，可以使用阳极接合（anodic bonding，阳极焊）。在可替换实施例中，可以使用直接接合或中间层接合。在直接或融化接合中，晶圆在没有显著压力或任何中间层或场的帮助情况下直接接触。在直接接合中，晶圆的表面被制备成确保良好的接触，例如，表面粗糙度和晶圆弓曲度（弯曲度，bow）可严格控制。在一种情形中，接合之前的晶圆表面粗糙度小于2nm，且在一个实施例中约小于1nm。在接合之前，对晶圆的表面进行清洁从而去除颗粒材料。清洁过的表面可变成亲水性或疏水性。在一些实施例中，在接触之前，可使用等离子体来清洁和/或活化表面。在接触晶圆之后，堆叠的晶圆可以退火。在一个实施例中，堆叠的晶圆在约250°C至约320°C的温度下退火，并在另一个实施例中在约280°C至约300°C温度下退火。
在阳极接合的情形中，晶圆中的一个上的介电层接合到其它晶圆的半导体区域中。例如，第二晶圆2的保护层20接合于第一晶圆1的衬底10的半导体区域。第一晶圆1的衬底10与第二晶圆2的保护层20之间施加有电势差，且堆叠的晶圆被加热。由于更高的温度和施加的场，在第一晶圆1的衬底10与第二晶圆2的保护层20之间形成化学接合。可替换地，玻璃层可在保护层20上方溅射，以用于与第一晶圆1的衬底10接合。在各种实施例中，堆叠的晶圆被加热到约100°C至约400°C，且在一个实施例中约200°C至约300°C。
在中间层接合中，中间层可用于接合晶圆。示例包括使用玻璃粉接合、共晶接合、环氧树脂、聚合物、焊料或热压缩接合。在玻璃粉接合或玻璃焊接中，玻璃状配方施加在待接合的晶圆表面上。接着，堆叠的晶圆被加热到约100°C至约200°C的第一温度，且在一个实施例中被加热到约100°C至约140°C。可使用退火来从玻璃配方中去除溶剂。接着，堆叠的晶圆被加热到第二温度以去除任何有机材料。第二温度可以是约200°C至约400°C，且在一个实施例中是约250°C至约350°C。在一个实施例中，可使用较高温度下的单个退火来代替上述的两次退火。在第三退火步骤中，晶圆叠层在第三温度下进行退火，该第三温度融化玻璃状配方。在一个实施例中，可使用较高温度下的单个退火来代替上述的三次退火。最后，在晶圆被挤压在一起从而形成接合的同时，将晶圆对准并再次在高于玻璃融化的温度下加热。在共晶接合中，共晶材料沉积在晶圆中的一个上（例如，作为图案），并且使晶圆接触并保持在高于形成共晶的共晶温度下，这形成共晶接合。共晶接合的实例包括焊接。
参考图3，穿过堆叠晶片形成贯穿开口50。在各种实施例中，贯穿开口50可在掩模工艺形成硬掩模之后使用化学蚀刻工艺（例如深反应离子蚀刻）形成。在各种实施例中，贯穿开口50可使用博世工艺（BoschProcess）、或通过沉积硬掩模层并使用竖直反应离子蚀刻穿过堆叠晶圆蚀刻而形成。
在博世工艺中，蚀刻和沉积交替执行并可重复多次。在第一步骤中，使用等离子体蚀刻来竖直地蚀刻开口，而在第二步骤中，沉积钝化层以便在已蚀刻区域中阻止开口的扩宽。等离子体蚀刻被配置成竖直蚀刻，例如在等离子体中使用六氟化硫[SF6]。例如使用八氟环丁烷（octa-fluoro-cyclobutane）作为源气体来沉积该钝化层。每个单独的步骤可进行几秒或更少时间。该钝化层保护衬底10以便阻止横向蚀刻。然而，在等离子体蚀刻过程中，轰击衬底10的定向离子在正在形成的开口的底部（但不沿着侧边）去除钝化层，且蚀刻继续。博世工艺可产生扇形的（scalloped）侧壁。
贯穿开口50也可使用其他工艺形成，诸如使用激光形成。在一些实施例中，也可用机械工艺来形成贯穿开口50。然而，当贯穿开口50的纵横比较大时，尤其可以使用化学工艺。
图4A-4C示出根据本发明实施例的贯穿过孔的形成，其中图4B和4C示出使用电镀工艺形成的贯穿过孔的放大横截面图。
如接下来在图4A中示出，在堆叠晶圆的贯穿开口50内形成贯穿过孔60。贯穿过孔60可使用任何方便的工艺形成，所述工艺包括电镀、化学镀、溅射、印刷、涂覆、沉积和其它工艺。在化学镀中，堆叠晶圆浸在镀槽中。因此，堆叠晶圆的两侧都暴露于镀槽，并因此被立即处理。
可替换地，在一个实施例中，并参考图4B，可使用电镀工艺。在这类实施例中，可在堆叠晶圆的顶部表面和相对底部表面上形成种子层（种晶层，seed layer）55。种子层55可使用金属沉积工艺（诸如溅射、包括化学气相沉积（CVD）及等离子体气相沉积（PVD）的气相沉积工艺）而形成。在一个或多个实施例中，种子层55可作为覆层（包层，blanket layer）在整个表面上方形成。种子层55可包括钛、钽、钨、铪、钼、钌、氮化钽、氮化钛、氮化钨、它们的碳化物、及它们的组合。
可在没有镀敷的区域上形成抗蚀部56以覆盖种子层55。可替换地，可从堆叠晶圆的顶部和底部表面去除种子层55。在贯穿开口50内使用电镀工艺镀敷填充材料57。在一个实施例中，填充材料57可包括铜。填充材料57可包括纯铜或铜合金。在其它实施例中，填充材料57包括银、金、铂、镍、锌和其它材料。电镀工艺不在覆盖的种子层55上生长，并仅在暴露的种子层55上生长。
在镀敷之后，如图4C中示出，例如使用蚀刻工艺去除抗蚀部56。接着，蚀刻暴露的种子层55，从而形成贯穿过孔60。
在一个或多个实施例中，贯穿过孔60可通过施加液体、膏状料或焊料形成。在一个实施例中，贯穿过孔60可被施加作为聚合物基体中的导电粒子。在可替换实施例中，可施加导电纳米膏，诸如银纳米膏。在各种实施例中，可使用任何合适的材料来形成贯穿过孔60，所述材料包括金属或金属合金，诸如铝、钛、金、银、铜、钯、铂、镍、铬或镍钒。
可形成附加的接触垫（contact pad）70来用于接触贯穿过孔60。在一个或多个实施例中，接触垫70可包括适于后续焊料形成的材料沉积。
与传统工艺不同，本发明实施例在堆叠晶圆之后形成贯穿过孔。相反，在传统工艺中，在晶片堆叠之前形成贯穿过孔。
图5-7示出形成堆叠半导体器件的可替换实施例，所述堆叠半导体器件使用背对背接合形成并具有互连晶片的贯穿过孔。
如前述实施例地执行前侧处理。在完成前侧处理之后，从后侧对晶圆进行薄化。晶圆可使用研磨工艺、化学工艺、或化学机械工艺薄化。
如图5中示出，使第一晶圆1的后侧与第二晶圆2的后侧放在一起。与前述实施例不同，使衬底10的由相同材料类型制成的表面互相接触。例如，在一种情形中，使第一晶圆1的硅表面接触第二晶圆2的硅表面。因此，该实施例更适合前面描述的直接接合和阳极接合技术。背对背堆叠晶圆允许贯穿过孔更密集地集成。
如接下来在图6中示出，使第一晶圆1和第二晶圆2接触并接合在一起，以形成堆叠晶圆。本发明的实施例可使用用于晶圆接合的任何合适的方法，所述晶圆接合方法包括前述实施例中的上述方法。
参考图7，如前面描述地形成具有接触垫70的贯穿过孔60。如在前述实施例中，（在堆叠和接合晶圆之后）贯穿开口形成在堆叠晶圆内，且用导电材料填充贯穿开口从而形成贯穿过孔60。
图8-11示出形成具有贯穿过孔的堆叠半导体器件的可替换实施例。
在该实施例中，可在晶圆上方堆叠多个晶片。因此，与前述实施例中描述的晶圆与晶圆堆叠相对照，该实施例描述晶片与晶圆堆叠。因此，如图8中示出，第一晶片6可在包括晶片的第一晶圆1上方堆叠。如前面描述，第一晶圆1是处理过的晶圆，其具有包括在晶圆中形成金属化部的多个晶片。金属化部和有源器件使用顶部保护层20保护。第一晶圆1包括用于形成外部接触的触点30。
类似地，第二晶片7堆叠在第一晶圆1的另一个晶片上方，且第三晶片8堆叠在第一晶圆1上方。本发明的实施例包括在晶圆上方堆叠多个晶片。例如，另一个晶片可堆叠在第一晶片6的上方，形成三个或更多个晶片的堆叠。在各种实施例中，晶片可如图5-7背对背地堆叠，或如图1-4面对背地堆叠。在背对背的配置中，第一晶片6的后侧（与邻近有源器件的前侧相对并具有保护层20和触点30）接触第一晶圆1的相应后侧。
如前述实施例，第一晶片6可以是与第一晶圆1的晶片不同或相同类型的晶片。
参考图9，多个晶片附接于第一晶圆1。该附接可使用用于接合晶片到衬底的任何合适工艺执行。示例包括如上描述的中间层接合，如果可能也可使用阳极接合和直接接合。在一个或多个实施例中，当使用背对背的配置将多个晶片附接到第一晶圆1时，可使用阳极接合。
参考图10，在该多个晶片内形成贯穿过孔60。在一些实施例中，贯穿过孔60可形成在该多个晶片和第一晶圆1内，如图11示出。
在形成贯穿过孔60之后，将第一晶圆1单个化。在一些实施例中，第一晶圆1可从后侧薄化，并然后单个化。换句话说，在一些实施例中附接多个晶片之前，特别是当多个晶片较薄以便在贯穿过孔60形成期间不出现稳定性问题时，第一晶圆1可以薄化。可替换地，为提供贯穿过孔60形成期间的稳定性，第一晶圆1的薄化可在贯穿过孔60形成之后执行。
图12-22示出堆叠半导体器件的制造，所述堆叠半导体器件包括互相堆叠并使用贯穿衬底过孔耦接的多个扇出型（成扇形散开，fan-out）封装。
本发明的实施例可应用到扇出型封装中。嵌入式晶圆级封装是增强的标准晶圆级封装，其中在人工晶圆上实现封装。标准晶圆被分割（diced），且单个化后的芯片放置在载体上。载体上芯片之间的距离可以自由选择。芯片周围的间隙可用封装材料填充从而形成人工晶圆。人工晶圆被处理以制造包括芯片和环绕扇出型区域的封装。互连元件可在形成嵌入式晶圆级球栅阵列（eWLB）封装的芯片和扇出型区域上实现。
在扇出类型封装中，外部接触垫和/或连接半导体芯片到外部接触垫的导体线路中的至少一些横向地位于半导体芯片轮廓的外侧、或至少与半导体芯片轮廓相交。因此，在扇出类型封装中，半导体芯片封装的周边的外部通常（附加地）用于将封装电接合到外部应用部件，如应用电路板等。包围半导体芯片的封装的该外部有效地增大了与半导体芯片占位面积（footprint）有关的封装接触面积，因此鉴于封装垫尺寸和随后处理（例如第二级组装）有关的间距，导致宽松的限制。
图12示出嵌入式晶圆级封装晶圆（也称为再造晶圆）。再造晶圆11通过在载体上方设置单个化晶片和用封装材料150封装晶片形成，所述封装材料150保护和密封晶片。
在一个实施例中，封装材料150使用压缩模制工艺施加。在压缩模制中，封装材料150可放置到模腔中，然后关闭模腔以压缩封装材料150。当模制单个图案化时，可使用压缩模制。在可替换实施例中，封装材料150使用转印模制工艺（transfer molding process）施加。
在其它实施例中，封装材料150可使用注射模制、颗粒模制、粉末模制或液态模制施加。可替换地，封装材料150可使用印刷工艺（如模板印刷或丝网印刷）施加。
在各种实施例中，封装材料150包含介电材料，并在一个实施例中可包含模制化合物。在其它实施例中，封装材料150可包括聚合物、生物聚合物、纤维浸渍聚合物（例如树脂中的碳纤维或玻璃纤维）、颗粒填充聚合物和其它有机材料。在一个或多个实施例中，封装材料150包括不使用模制化合物和诸如环氧树脂和/或硅树脂材料形成的密封剂。在各种实施例中，封装材料150可由任何合适的硬质塑料、热塑性塑料、或热固性材料或层压材料制成。在一些实施例中，封装材料150的材料可包括填充材料。在一个实施例中，封装材料150可包括环氧树脂材料和填充材料，所述填充材料包括小颗粒玻璃或其它电绝缘矿物填充材料，如氧化铝或有机填充材料。
封装材料150可被固化，即经受热过程以被硬化，从而形成保护晶片（如第一晶片6和第二晶片7）的密封。
如图13中示出的，第一介电层110可沉积。第一介电层110可包括氧化物或氮化物材料，如氧化硅或氮化硅。
如接下来图14中示出，抗蚀部120沉积在第一介电层110上方并被图案化以形成开口130。抗蚀部120可包括光致抗蚀部及硬掩模材料，如氮化硅、碳化硅或组合。抗蚀部120可在各种实施例中包括多个层。
使用抗蚀部120作为掩模，第一介电层110可图案化，如图15中示出。抗蚀部120可以去除，如图16中示出。接着，多个再分配线160和嵌入式接触垫165形成，如图17A和图17B示出。第二介电层170可选地可用于保护接触垫165。
因此，形成了扇出型嵌入式晶圆或具有再分配线和嵌入式接触垫165的再造晶圆。在各种实施例中，任何其它合适的设计和工艺可用于形成再造晶圆。
接着，如图18中示出，多个再造晶圆堆叠。根据本发明实施例在堆叠之前再造晶圆可薄化。再造晶圆可背对背堆叠或者面对背配置，其在图18中示出。
在一个实施例中，第一晶片6堆叠在第三晶片8上方，而第二晶片7堆叠在第四晶片9上方。此外，在一些实施例中，第一晶片6可耦接到第二晶片7，和/或第三晶片8可耦接到第四晶片9。在可替换实施例中，第一晶片6可部分地堆叠在第三晶片8和第四晶片9上方，以便形成包括第一晶片6、第三晶片8和第四晶片9的封装。
在第一再造晶圆11对准和布置在第二再造晶圆12上方之后，可使用接合工艺。在一个实施例中，可使用中间层接合。例如，在接触之前，可施加中间层，如粘合剂、环氧树脂、聚合物层。
参考图19，如之前的实施例，抗蚀部180可沉积并图案化以形成用于贯穿过孔190的开口。
使用图案化抗蚀部180作为蚀刻掩模，可形成贯穿开口50。在一个实施例中，贯穿开口50延伸通过第一再造晶圆11，而不延伸通过下方的第二再造晶圆12。在可替换实施例中，贯穿过孔50延伸通过第一和第二再造晶圆11和12两者。
在一个实施例中，贯穿开口50停止在下方再造晶圆（图20）的着陆垫（landing pad）（例如，嵌入式接触垫165）。可替换地，贯穿开口50可延伸通过这两个再造晶圆。
如接下来图21中示出，用导电填充材料填充贯穿开口50，从而形成贯穿过孔60。如示出，贯穿过孔60中的一个将第一晶片6耦接到第三晶片8，而另一个贯穿过孔60将第二晶片7上与第四晶片9耦接。
参考图22，堆叠的再造晶圆可被单个化，以形成3D集成芯片封装。
图23A和23B示出形成具有多个堆叠晶片的3D集成扇出型封装的进一步实施例。
该实施例可按照图12-21中示出的方法进行。接着，在单个化之前，另一个晶圆（例如具有多个晶片的第三晶圆3）可被布置在堆叠的晶圆上方，如图23A示出。在将第三晶圆3放置于堆叠晶圆上方之后，第三晶圆3可使用上述技术之一附接或接合。如图23A和23B中示出，第三晶圆3的晶片可以与第一晶圆1和/或第二晶圆2不同地布置。因此，第五晶片19放置在第一晶片6和第二晶片7上方，如图23A和23B中的一种情形中所示出的。在其它实施例中，第五晶片19的位置可适当地调整。
参考图23B，第三晶圆3可使用在堆叠的第一和第二晶圆1和2内的贯穿过孔60的不同布置来耦接到堆叠晶圆。
图24A-24E示出形成具有多个堆叠晶片的3D集成封装的进一步实施例，其中图24A-24D示出扇出型封装，而图24E示出堆叠的半导体芯片。
参考图24A，第三再造晶圆13堆叠在第一再造晶圆11上方，所述第一再造晶圆11堆叠在第二再造晶圆12上方。尽管这里使用再造晶圆的堆叠进行描述，但是该实施例可应用到晶圆（例如图2的第一晶圆1，第二晶圆2，第三晶圆3，如下图24E中示出）的堆叠。
接着，如图24B中示出，贯穿开口50如之前实施例中描述地形成。在图24C中示出的一个实施例中，用导电材料填充贯穿开口50，例如，如相对于图4A-4C描述地。
在图24D中示出的可替换实施例中，贯穿过孔被部分地用导电材料填充。贯穿开口50的剩余部分用绝缘填充材料填充，从而形成绝缘插头65。因此，贯穿过孔60中的一个通过将第二再造晶圆12电互连到第一再造晶圆11上而形成3D堆叠IC的内部电路的一部分。
在如图24E示出的一个或多个实施例中，图24D的实施例可应用到图4A中的实施例中。
图25根据本发明实施例示出包括堆叠芯片的引线框架（lead frame）封装。
在各种实施例中，可使用任何合适的封装技术封装堆叠的晶片。示例包括倒装芯片封装、引线框架封装和其它封装。
图25示出引线框架封装，其包括具有多个引线41的引线框架40。包括第一晶片6和第二晶片7的堆叠晶圆被互相堆叠，并被堆叠在引线框架40上方。根据前面描述的本发明实施例，可形成包括设置在第一晶片6上方的第二晶片7的堆叠晶片。
线接合部42可形成为将设置在第一晶片6上的接触垫与引线框架40的多个引线41连接。该多个引线41还耦接到第二晶片7上，因为第一晶片6上的接触垫利用贯穿过孔60耦接到第二晶片7。
封装材料150设置在引线框架40上、以及第一和第二晶片6和7上。封装材料150可包括早先描述的材料，并可在各种实施例中包括模制化合物、环氧树脂和其它材料。引线框架封装可使用焊球43安装在电路封装45上方。
图26A和26B示出了本发明各种实施例中堆叠晶片的倒装芯片安装。
参考图26A，制备堆叠晶片的接触垫70，以用于倒装芯片安装。作为一个例子，在一个实施例中，可形成焊球43。在各种实施例中，可沉积一些合适的凸点下材料。
接着，如图26B中示出，堆叠晶片使用焊球安装在诸如电路板45的衬底上，所述焊球可被加热从而形成与电路板45的共晶接合。在一些实施例中，在单个化之后，堆叠晶片可被封装在封装材料150中。
如各种实施例中描述，包括金属的材料可以例如是纯金属、金属合金、金属化合物、金属间化合物和其它材料，即，任何包括金属原子的材料。例如，铜可以是纯铜或包括铜的任何材料，例如但不限于铜合金、铜化合物、铜金属间化合物、包含铜的绝缘体、和包含铜的半导体。
当参考说明性实施例描述本发明时，该描述不旨在限制意义上解释。在参考描述的基础上，对于本领域技术人员将是明显的是，说明性实施例和本发明其它实施例可进行各种修改和组合。作为示例，图1-4、图5-7、图8-10、图12-22、图23A-23B、图24A-24E、图25和/或图26A和26B中描述的实施例可互相组合。因此，本发明旨在权利要求包括任何这类修改或实施例。
尽管本发明及其优点已详细描述，应该理解的是，在不背离权利要求定义的本发明精神和保护范围的情况下，可在这里做出各种变化、替换和变更。例如，本领域那些技术人员易于理解，可改变这里描述的许多特征、功能、工艺和材料，同时保持在本发明的保护范围之内。
此外，本发明应用的保护范围不旨在限于说明书中描述的工艺、机器、制造、物质的组分、装置、方法和步骤的具体实施例。作为本领域普通技术人员，将易于从本发明的公开中理解的是，根据本发明可利用当前已有或以后开发的工艺、机器、制造、物质的组分、装置、方法或步骤，这些工艺、机器、制造、物质的组分、装置、方法或步骤如这里描述的相应实施例一样基本执行相同功能或基本实现相同结果。因此，权利要求旨在将这些工艺、机器、制造、物质的组分、装置、方法或步骤包括在它们的保护范围内。

Claims (30)

1.一种形成半导体器件的方法，所述方法包括：
堆叠第一晶圆和第二晶圆；以及
在所述第二晶圆堆叠有所述第一晶圆的同时，形成延伸通过所述第二晶圆的贯穿过孔。
2.根据权利要求1所述的方法，其中，形成所述贯穿过孔的步骤包括：
形成延伸通过所述第二晶圆的贯穿孔；以及
用导电材料填充所述贯穿孔。
3.根据权利要求1所述的方法，其中，形成所述贯穿过孔的步骤包括：
形成延伸通过所述第一晶圆和所述第二晶圆的贯穿孔；以及
用导电材料填充所述贯穿孔。
4.根据权利要求3所述的方法，其中，所述导电材料包括金属。
5.根据权利要求3所述的方法，其中，所述导电材料包括铜。
6.根据权利要求5所述的方法，其中，所述导电材料包括纯铜或铜合金。
7.根据权利要求3所述的方法，其中，所述导电材料包括多晶硅。
8.根据权利要求3所述的方法，进一步包括：
在形成所述贯穿孔之前，接合所述第一晶圆和所述第二晶圆。
9.根据权利要求3所述的方法，其进一步包括：
堆叠所述第二晶圆和第三晶圆；以及
堆叠所述第三晶圆和第四晶圆，其中所述贯穿孔延伸通过所述第三晶圆和所述第四晶圆。
10.根据权利要求1所述的方法，进一步包括：
在所述堆叠之前，在所述第一晶圆中提供第一多个晶片并且在所述第二晶圆中提供第二多个晶片；以及
在所述堆叠之前，薄化所述第一晶圆和所述第二晶圆。
11.根据权利要求10所述的方法，其中，所述提供的步骤包括在所述第一晶圆中形成所述第一多个晶片并且在所述第二晶圆中形成所述第二多个晶片。
12.根据权利要求1所述的方法，进一步包括：
在形成所述贯穿过孔之后，将所述第一晶圆和所述第二晶圆单个化。
13.根据权利要求1所述的方法，其中，所述堆叠的步骤包括使所述第一晶圆的后侧与所述第二晶圆的后侧接触，其中，所述第一晶圆的前侧和所述第二晶圆的前侧包括有源器件。
14.根据权利要求1所述的方法，进一步包括：
堆叠多个晶圆和所述第二晶圆，其中，形成所述贯穿过孔的步骤包括：在所述多个晶圆堆叠有所述第一和所述第二晶圆的同时，形成延伸通过所述多个晶圆和所述第二晶圆的所述贯穿过孔。
15.一种形成半导体器件的方法，所述方法包括：
提供第一再造晶圆，所述第一再造晶圆包括嵌入在第一封装物内的第一多个晶片；
提供第二再造晶圆，所述第二再造晶圆包括嵌入在第二封装物内的第二多个晶片；
堆叠所述第一再造晶圆和所述第二再造晶圆；以及
在所述第二再造晶圆堆叠有所述第一再造晶圆的同时，形成延伸通过第二再造晶圆的第一贯穿过孔。
16.根据权利要求15所述的方法，其中，提供所述第一再造晶圆和提供所述第二再造晶圆的步骤包括形成所述第一再造晶圆和所述第二再造晶圆。
17.根据权利要求15所述的方法，其中，所述第一贯穿过孔延伸通过所述第一再造晶圆。
18.根据权利要求15所述的方法，其中，形成所述第一贯穿过孔的步骤包括：
形成延伸通过所述第一再造晶圆和所述第二再造晶圆的贯穿孔；以及
用导电材料填充所述贯穿孔。
19.根据权利要求15所述的方法，进一步包括在形成所述第一贯穿过孔之后，将所述第一再造晶圆和所述第二再造晶圆单个化。
20.根据权利要求15所述的方法，进一步包括：
在形成所述第一贯穿过孔之前，接合所述第一再造晶圆和所述第二再造晶圆，以形成堆叠的再造晶圆。
21.根据权利要求15所述的方法，其中，形成所述第一贯穿过孔的步骤包括利用电解或无电处理来沉积导电材料。
22.根据权利要求15所述的方法，进一步包括：
形成第三再造晶圆，所述第三再造晶圆包括嵌入在第三封装物内的第三多个晶片；
在形成所述第一贯穿过孔之后，堆叠所述第二再造晶圆和所述第三再造晶圆；以及
在所述第三再造晶圆内形成第二贯穿过孔。
23.根据权利要求15所述的方法，进一步包括：
形成第三再造晶圆，所述第三再造晶圆包括嵌入在第三封装物内的第三多个晶片；
在形成所述第一贯穿过孔之前，堆叠所述第二再造晶圆和所述第三再造晶圆，其中，形成所述第一贯穿过孔包括在所述第二再造晶圆和所述第三再造晶圆内形成所述第一贯穿过孔。
24.根据权利要求15所述的方法，进一步包括：
形成第三再造晶圆，所述第三再造晶圆包括嵌入在第三封装物内的第三多个晶片；
在形成所述第一贯穿过孔之前，堆叠所述第二再造晶圆和所述第三再造晶圆；
形成延伸通过所述第二再造晶圆和所述第三再造晶圆的第一贯穿开口；
用导电材料填充所述第一贯穿开口的位于所述第二再造晶圆内的第一部分，以形成第一贯穿过孔；以及
用绝缘材料填充第一贯穿开口的剩余部分。
25.根据权利要求24所述的方法，进一步包括：
形成第二贯穿开口，所述第二贯穿开口延伸通过所述第三再造晶圆到达所述第二再造晶圆上的触点；以及
用导电材料填充所述第二贯穿开口。
26.一种形成半导体器件的方法，所述方法包括：
将第一晶圆单个化成第一多个晶片；
将所述第一多个晶片附接到包括第二多个晶片的第二晶圆上；以及
在附接之后，形成延伸通过所述第一多个晶片中的晶片的贯穿过孔。
27.根据权利要求26所述的方法，进一步包括：
通过单个化所述第二晶圆而形成堆叠晶片。
28.根据权利要求27所述的方法，进一步包括：
将所述堆叠晶片放置在引线框架上；
形成接合线，所述接合线将所述第二多个晶片上的触点耦接到所述引线框架；以及
用封装材料封装所述接合线、所述引线框架和所述堆叠晶片。
29.根据权利要求27所述的方法，其中，所述贯穿过孔延伸通过所述第二晶圆。
30.根据权利要求27所述的方法，进一步包括：
将第三晶圆单个化成第三多个晶片中；以及
将所述第三多个晶片附接到所述第一多个晶片上，其中，所述贯穿过孔延伸通过所述第三多个晶片中的晶片。
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