TWI682449B - 封裝件及其製造方法 - Google Patents

封裝件及其製造方法 Download PDF

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Publication number
TWI682449B
TWI682449B TW107140531A TW107140531A TWI682449B TW I682449 B TWI682449 B TW I682449B TW 107140531 A TW107140531 A TW 107140531A TW 107140531 A TW107140531 A TW 107140531A TW I682449 B TWI682449 B TW I682449B
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Taiwan
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etch stop
layer
stop layer
die
opening
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TW107140531A
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TW201923866A (zh
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陳明發
陳憲偉
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台灣積體電路製造股份有限公司
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Abstract

一種方法包括將第一元件晶粒與第二元件晶粒接合至第 三元件晶粒、形成多個間隙填充層以在第一元件晶粒與第二元件晶粒之間延伸以及進行第一蝕刻製程以蝕刻多個間隙填充層中的第一介電層，藉此形成開口。多個間隙填充層中的第一蝕刻停止層用以停止第一蝕刻製程。然後開口延伸穿過第一蝕刻停止層。進行第二蝕刻製程以將開口延伸穿過第一蝕刻停止層下方的第二介電層。第二蝕刻製程停止在多個間隙填充層中的第二蝕刻停止層上。該方法還包括將開口延伸穿過第二蝕刻停止層，並將導電材料填入開口以形成穿孔。

Description

封裝件及其製造方法
本發明實施例提供一種封裝件及其製造方法。
積體電路的封裝為了將更多的元件晶粒封裝在同一個封裝件中以實現更多的功能而變得越來越複雜。舉例來說，已開發一種封裝結構，以在同一封裝件中包括多個元件晶粒，例如處理器與記憶體立方體(memory cubes)。封裝結構可以將使用不同的技術形成並具有不同功能的元件晶粒接合至同一元件晶粒，從而形成系統。這可以節省製造成本並最佳化元件效率。
本發明實施例提供一種封裝件的製造方法，其步驟如下。將第一元件晶粒與第二元件晶粒接合至第三元件晶粒；形成多個間隙填充層以在第一和第二元件晶粒之間延伸；進行第一蝕刻製程，以蝕刻多個間隙填充層中的第一介電層，藉此形成開口，其中多個間隙填充層中且在第一介電層下方的第一蝕刻停止層用以停 止第一蝕刻製程；將開口延伸穿過第一蝕刻停止層；進行第二蝕刻製程，以將開口延伸穿過第一蝕刻停止層下方的第二介電層，其中第二蝕刻製程停止在多個間隙填充層中的第二蝕刻停止層上；將開口延伸穿過第二蝕刻停止層；以及將導電材料填入開口，以形成穿孔。
本發明實施例提供另一種封裝件的製造方法，其步驟如下。將多個元件晶粒接合至元件晶圓；在多個元件晶粒之間形成隔離區，其中形成隔離區包括：形成第一蝕刻停止層，其具有接觸多個元件晶粒的側壁部分和接觸元件晶圓的頂表面的底部部分；在第一蝕刻停止層上形成第一介電層；在第一介電層上形成第二蝕刻停止層；以及在第二蝕刻停止層上形成第二介電層；蝕刻隔離區以形成穿透隔離區的第一開口和第二開口，其中元件晶圓的接合墊外露於第一開口，而在蝕刻隔離區期間，第二蝕刻停止層用以停止蝕刻；將導電材料填充第一開口，形成第一穿孔。
本發明實施例提供一種封裝件，包括第一元件晶粒、第二元件晶粒、第三元件晶粒、隔離區以及穿孔。第二元件晶粒與第三元件晶粒接合至第一元件晶粒。隔離區位於第二元件晶粒和第三元件晶粒之間。隔離區包括：第一蝕刻停止層，其具有與第一和第二元件晶粒接觸的側壁部分以及與第一元件晶粒的頂表面接觸的底部部分；第一蝕刻停止層上的第一介電層；第一介電層上的第二蝕刻停止層；以及第二蝕刻停止層上的第二介電層。穿孔穿透隔離區的，以電性連接至第一元件晶粒。
2‧‧‧晶圓
4‧‧‧晶片
42A、42B‧‧‧元件晶粒
20、44A、44B‧‧‧半導體基底
22‧‧‧積體電路元件
24‧‧‧層間介電質
28‧‧‧接觸插塞
30、48A、48B‧‧‧內連線結構
32、38、52A、52B、56、60、64、74‧‧‧介電層
34‧‧‧金屬線
36、78‧‧‧通孔
40、40A、40B、50A、50B‧‧‧接合墊
44A-BS1、44B-BS1‧‧‧背側研磨之前的元件晶粒的背表面
44A-BS2、44B-BS2‧‧‧背側研磨之後的元件晶粒的背表面
46A、46B‧‧‧矽穿孔
70、112‧‧‧穿孔
53‧‧‧間隙
54、58、62‧‧‧蝕刻停止層
65‧‧‧隔離區
66‧‧‧開口
68‧‧‧光阻
71‧‧‧虛線
72‧‧‧重分佈線
76、82‧‧‧鈍化層
80‧‧‧金屬墊
84、88‧‧‧聚合物層
86‧‧‧鈍化後互連件
90‧‧‧凸塊下金屬
92‧‧‧電連接件
94‧‧‧複合晶圓
96、98、108‧‧‧封裝件
100‧‧‧記憶體立方體
102、114‧‧‧包封材料
106‧‧‧疊層封裝結構
110‧‧‧頂部封裝件
200‧‧‧製程流程
202、204、206、208、210、212、214、216、218、220、222‧‧‧步驟
H1‧‧‧高度
T1、T1A、T1B、T2、T3、T4‧‧‧厚度
當結合附圖閱讀時，自以下實施方式最佳地理解本揭露的態樣。應注意，根據業界中的標準慣例，各種特徵未按比例繪製。事實上，可出於論述清楚起見，任意地增大或減小各種特徵的尺寸。
圖1至圖13是根據一些實施例的封裝件在製造中的中間階段的剖面示意圖。
圖14繪示出根據一些實施例的封裝件的剖面示意圖。
圖15與圖16繪示出根據一些實施例的嵌入有另外封裝結構的封裝件的剖面示意圖。
圖17繪示出根據一些實施例的用於形成封裝結構的製程流程。
以下揭露內容提供用於實施所提供的目標的不同特徵的許多不同實施例或實例。以下所描述構件與配置的具體實例來簡化本揭露。當然，這些僅僅是示例，而非用以限制。舉例而言，在以下的描述中，在第二特徵上方或在第二特徵上形成第一特徵可包括第一特徵與第二特徵形成為直接接觸的實施例，並且還可以包括第一特徵與第二特徵之間可形成有額外特徵，使得第一特徵與第二特徵可不直接接觸的實施例。此外，本揭露在各種實例中可重複使用元件標號及/或字母。元件標號的重複使用是為了簡單及 清楚起見，且並不表示所欲討論的各個實施例及/或配置本身之間的關係。
另外，如「在...下方」、「下面」、「下部」、「在...上方」、「上部」等空間相對術語來闡述圖中所示的一個元件或特徵與另一(些)元件或特徵的關係。除圖式中所描繪之定向以外，空間相對術語意欲涵蓋裝置或設備在使用或操作中之不同定向。裝置或設備可以其他方式定向(旋轉90度或位於其他定向)，且本文中所使用之空間相對描述詞可同樣相應地進行解釋。
根據各種例示性實施例提供封裝體以及其形成方法。根據一些實施例繪示出形成封裝體的中間階段。一些實施例的一些變化型亦被討論。在各視圖以及說明性實施例中，相同的元件標號用以表示相同元件。
圖1至圖13繪示出根據本揭露的一些實施例形成封裝件的中間階段的剖面示意圖。圖1至圖13所示的步驟亦示意性地反映在圖17所示的製程流程200中。
圖1繪示出晶圓2的形成的剖面示意圖。相應的製程被繪示在圖17所示的製程流程中的步驟202。根據本揭露的一些實施例，晶圓2是元件晶圓，其包括例如電晶體以及/或二極體的主動元件，且可能包括例如電容器、電感器、電阻器或其類似物的被動元件。元件晶圓2可包括多個晶片4在其中，以下說明晶片4中的一個。在下文中，晶片4另稱為(元件)晶粒。根據本揭露的一些實施例，元件晶粒4是邏輯晶粒，其可以是中央處理單元 (Central Processing Unit，CPU)晶粒、微控制單元(Micro Control Unit，MCU)晶粒、輸入-輸出(input-output，IO)晶粒、基頻(BaseBand，BB)晶粒或應用處理器(Application processor，AP)晶粒。元件晶粒4也可以是記憶體晶粒，例如動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)晶粒或靜態隨機存取記憶體(Static Random Access Memory，SRAM)晶粒。
根據本揭露的替代實施例，封裝組件2包括被動元件(即沒有主動元件)。在後續討論中，元件晶圓被討論為示例性封裝組件2。本揭露的實施例亦可應用於其他類型的封裝組件，例如中介件晶圓。
根據本揭露的一些實施例，示例性晶圓2包括半導體基底20與形成在半導體基底20的頂表面處的特徵。半導體基底20可由結晶矽、結晶鍺、結晶矽鍺以及/或III-V化合物半導體形成，所述III-V族化合物半導體例如是GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP或類似者。半導體基底20亦可以是塊狀矽基底或絕緣層上矽(Silicon-On-Insulator，SOI)基底。淺溝渠隔離(Shallow Trench Isolation，STI)區(未繪示)可形成在半導體基底20中，以隔離半導體基底20中的主動區。儘管未繪示，但穿孔可形成並延伸到半導體基底20中，其中穿孔用以將晶圓2的相對側上的特徵相互電耦接。
根據本揭露的一些實施例，晶圓2包括積體電路元件22，其形成在半導體基底20的頂表面上。示例性積體電路元件22可 包括互補金屬氧化物半導體(Complementary Metal-Oxide Semiconductor，CMOS)電晶體、電阻器、電容器、二極體以及/或其類似物。本文中並不贅述積體電路裝置22的細節。根據替代實施例，晶圓2用於形成中介件，其中基底20可以是半導體基底或介電基底。
層間介電質(Inter-Layer Dielectric，ILD)24形成在半導體基底20上，並填入積體電路元件22中的電晶體(未繪示)的閘極堆疊之間的空間。根據一些示例性實施例，ILD 24由磷酸鹽玻璃(Phospho Silicate Glass，PSG)、硼矽酸鹽玻璃(Boro Silicate Glass，BSG)、硼摻雜磷矽酸鹽玻璃(Boron-Doped Phospho Silicate Glass，BPSG)、氟摻雜矽酸鹽玻璃(Fluorine-Doped Silicate Glass，FSG)、四乙氧基矽烷(Tetra Ethyl Ortho Silicate，TEOS)或其類似物形成。ILD 24可使用旋塗法、可流動化學氣相沈積法(Flowable Chemical Vapor Deposition，FCVD)、化學氣相沈積法(Chemical Vapor Deposition，CVD)或其類似方法形成。根據本揭露的一些實施例，ILD 24使用例如電漿增強式化學氣相沈積法(Plasma Enhanced Chemical Vapor Deposition，PECVD)、低壓化學氣相沈積法(Low Pressure Chemical Vapor Deposition，LPCVD)或其類似的沉積方法形成。
接觸插塞28形成在ILD 24中，且用以將積體電路元件22電性連接至上覆金屬線和通孔。根據本揭露的一些實施例，接觸插塞28由選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金 以及/或其多層的導電材料形成。接觸插塞28的形成可包括在ILD 24中形成接觸窗開口，將導電材料填入至接觸窗開口中，並且進行平坦化(例如化學機械研磨(Chemical Mechanical Polish，CMP)製程)，以使接觸插塞28的頂表面與ILD 24的頂表面齊平。
ILD 24與接觸插塞28上具有內連線結構30。內連線結構30包括金屬線34和通孔36，其形成在介電層32中。在下文中，介電層32可替代地稱為內金屬介電質(Inter-Metal Dielectric，IMD)層32。根據本揭露的一些實施例，介電層32中的至少下部由具有低於約3.0、低於約2.5或甚至更低的介電常數(k值)的低介電常數介電材料形成。介電層32可由黑金剛石(應用材料公司(Applied Materials)的註冊商標)、含碳的低介電常數介電材料、氫矽倍半氧烷(Hydrogen SilsesQuioxane，HSQ)、甲基矽倍半氧烷(MethylSilsesQuioxane，MSQ)或其類似物形成。根據本揭露的替代實施例，介電層32的一些或全部由非低介電常數介電材料形成，所述材料例如氧化矽、碳化矽(silicon carbide，SiC)、碳氮化矽(silicon carbo-nitride，SiCN)、氧碳氮化矽(silicon oxy-carbo-nitride，SiOCN)或其類似物。根據本揭露的一些實施例，介電層32的形成包括沉積含致孔劑的介電材料，然後進行固化製程以驅除致孔劑，因此剩餘的介電層32為多孔的。由碳化矽、氮化矽或其類似物所形成的蝕刻停止層(未繪示)可形成在IMD層32之間，並且為簡單起見而未繪示。
金屬線34與通孔36形成在介電層32中。以下將處在相 同高度處的金屬線34統稱為金屬層。根據本揭露的一些實施例，內連線結構30包括藉由穿孔36相互連接的多個金屬層。金屬線34與通孔36可由銅或銅合金形成，且其亦可由其他金屬形成。形成製程可包括單金屬鑲嵌製程以及雙重金屬鑲嵌製程。在示例性單金屬鑲嵌製程中，首先在介電層32中的一者中形成溝渠，接著將導電材料填入溝渠。接著進行例如CMP製程的平坦化製程，以移除高於IMD層的頂表面的導電材料的多餘部分，從而在溝渠中留下金屬線。在雙重金屬鑲嵌製程中，在IMD層中形成溝渠以及通孔開口兩者，其中通孔開口位於溝渠之下且與溝渠連接。接著將導電材料填入至溝渠以及通孔開口中，以分別形成金屬線以及通孔。導電材料可包括擴散阻擋層以及在擴散阻擋層上方的含銅金屬材料。擴散阻擋層可包括鈦、氮化鈦、鉭、氮化鉭或其類似物。
圖1繪示出根據本揭露的一些實施例的表面介電層38。表面介電層38由例如氧化矽的非低介電常數介電材料形成。表面介電層38可替代地稱為鈍化層，因為它具有將下方的低介電常數介電層(如果有的話)與有害的化學品和水分的不利影響隔離的功能。表面介電層38亦可具有包括多於一層的複合結構，其可以由氧化矽、氮化矽、未摻雜矽酸鹽玻璃(Un-doped Silicate Glass，USG)或其類似物形成。元件晶粒4還可以包括金屬墊，例如鋁或鋁銅接墊、鈍化後互連件(Post-Passivation Interconnect，PPI)或其類似物，為簡單起見而未繪示。
接合墊40A和40B亦可統稱或個別地稱為接合墊40，其 形成在表面介電層38中。根據本揭露的一些實施例，接合墊40A和40B通過單金屬鑲嵌製程形成，且亦可包括阻障層和形成在阻障層上的含銅材料。根據本揭露的替代實施例，接合墊40A和40B可以通過雙重金屬鑲嵌製造形成。
根據本揭露的一些實施例，在晶圓2中沒有例如聚合物層的有機介電材料。有機介電層通常具有高的熱膨脹係數(Coefficient of Thermal Expansion，CTE)，其可例如是10ppm/℃或更高。這顯然大於矽基底(例如基底20)的CTE，矽基底的CTE約為3ppm/℃。因此，有機介電層趨向於造成晶圓2的翹曲。不包括有機材料於其中的晶圓2有助於減少晶圓2中的層之間的CTE失配，並使得翹曲情況減少。另外，不包括有機材料於其中的晶圓2有可能形成精細間距金屬線(例如圖10中的重分佈線72)以及高密度接合墊，並進而改善佈線能力。
頂部的表面介電層38和接合墊40被平坦化，使得它們的頂表面是共平面，這可能是由於接合墊40形成時的化學機械研磨所產生的。
接下來，將元件晶粒42A和42B接合至晶圓2，如圖2所示。相應的製程被繪示在圖17所示的製程流程中的步驟204。根據本揭露的一些實施例，各元件晶粒42A和42B可以是邏輯晶粒，其可為CPU晶粒、MCU晶粒、IO晶粒、基頻晶粒或AP晶粒。元件晶粒42A和42B可包括記憶體晶粒。元件晶粒42A和42B可選自上述所列出類型的不同類型的晶粒。此外，元件晶粒 42A和42B可使用不同的技術形成，例如45奈米技術、28奈米技術、20奈米技術或其類似技術。另外，元件晶粒42A和42B中的一個可以是數位電路晶粒，而另一個可以是類比電路晶粒。晶粒4、42A以及42B的組合用以作為系統。將系統的功能和電路分成例如晶粒4、42A以及42B的不同晶粒可最佳地這些晶粒的形成，且可使得製造成本的降低。
元件晶粒42A和42B分別包括半導體基底44A和44B，其可以是矽基底。矽穿孔(Through-Silicon Vias，TSVs)46A和46B(有時稱為半導體穿孔或穿孔)形成以分別穿透半導體基底44A和44B。TSVs 46A和46B用於將形成在半導體基底44A和44B的前側(所繪示的底側)上的元件和金屬線連接到背側。此外，元件晶粒42A和42B分別包括內連線結構48A和48B，用於連接元件晶粒42A和42B中的主動元件和被動元件。內連線結構48A和48B包括金屬線和通孔(未繪示)。
元件晶粒42A包括繪示在元件晶粒42A的底表面處的接合墊50A和介電層52A。接合墊50A的底表面與介電層52A的底表面共平面。元件晶粒42B包括繪示在底表面處的接合墊50B和介電層52B。接合墊50B的底表面與介電層52B的底表面共平面。根據本揭露的一些實施例，例如晶粒42A和42B的所有元件晶粒均不含有例如聚合物的有機介電材料。
所述接合可藉由混合接合方式來實現。舉例來說，接合墊50A和50B藉由金屬對金屬直接接合方式(metal-to-metal direct bonding)接合至接合墊40A。根據本揭露的一些實施例，所述金屬對金屬直接接合方式包括銅對銅直接接合方式。此外，介電層52A和52B接合至表面介電層38產生了例如Si-O-Si鍵結。
為了實現混合接合，首先將元件晶粒42A和42B輕微按壓在晶粒4上，以將元件晶粒42A和42B預接合(pre-bonded)至介電層38和接合墊40A。雖然繪示出兩個元件晶粒42A和42B，但是混合接合可以在晶圓級進行，且預接合與包括所繪示之元件晶粒42A和42B的晶粒群組相同的多個元件晶粒組，並佈置為多個列(rows)與多個行(columns)。
預接合所有元件晶粒42A和42B之後，進行退火以使接合墊40A與相應的上覆蓋接合墊50A和50B中的金屬相互擴散。根據一些實施例，退火溫度可以在約200℃與約400℃之間的範圍內，且可以在約300℃與約400℃之間的範圍內。根據一些實施例，退火時間可以在約1.5小時和約3.0小時之間的範圍內，並且可以在約1.5小時和約2.5小時之間的範圍內。藉由混合接合，接合墊50A和50B通過由金屬相互擴散所引起的直接金屬接合方式結合至相應的接合墊40A。接合墊50A和50B可以與相應的接合墊40A形成可區分的界面。
介電層38亦接合至介電層52A和52B，其間具有鍵結。舉例來說，介電層38以及52A/52B中的一者的原子(例如氧原子)與介電層38以及52A/52B中的另一者的原子(例如矽原子)形成化學或共價鍵結。介電層38以及52A/52B之間所產生的接合是介 電質對介電質接合(dielectric-to-dielectric bonding)。接合墊50A和50B的尺寸可以大於、等於或小於相應的接合墊40A的尺寸。鄰近的元件晶粒42A和42B之間具有間隙53。
進一步參照圖2，可進行背側研磨以薄化元件晶粒42A和42B，例如，將其厚度薄化至約15μm與約30μm之間。圖2示意性地繪示出虛線44A-BS1與44B-BS1，其分別是在背側研磨之前的元件晶粒42A和42B的背表面。而標號44A-BS2與44B-BS2則分別是指背側研磨後的元件晶粒42A和42B的背表面。藉由薄化元件晶粒42A和42B，可減小鄰近的元件晶粒42A和42B之間的間隙53的深寬比(aspect ratio)，以便進行間隙填充。否則，所述間隙填充可能因為間隙53的高深寬比而難以達到。在背側研磨之後，TSVs 46A和46B可被暴露出來。另外，當背側研磨停止在覆蓋TSVs 46A和46B的基底薄層上時，在此情況下，TSVs 46A和46B亦可不被暴露出來。根據這些實施例，TSVs 46A和46B可以在圖4所示的步驟中暴露出來。根據其他實施例，間隙53的深寬比對於間隙填充而言不是太高時，則可跳過背側研磨步驟。
圖3繪示出多個間隙填充層的形成，所述間隙填充層包括介電層及其下方的蝕刻停止層。相應的製程被繪示在圖17中所示的製程流程中的步驟206。根據本揭露的一些實施例，所述間隙填充層包括蝕刻停止層54、蝕刻停止層54上並接觸蝕刻停止層54的介電層56、介電層56上並接觸介電層56的蝕刻停止層58以及蝕刻停止層58上並接觸蝕刻停止層58的介電層60。層54、 56以及58可依序沉積，並且可以使用共形沉積法(例如原子層沉積(Atomic Layer Deposition，ALD)或化學氣相沉積(CVD))沉積。
蝕刻停止層54由介電材料形成，所述介電材料對於元件晶粒42A和42B的側壁、介電層38的頂表面以及接合墊40B具有良好的附著性。根據本揭露的一些實施例，蝕刻停止層54由含氮化物材料(例如氮化矽)形成。蝕刻停止層54的厚度T1(包括T1A和T1B)可在約500Å與約1,000Å之間的範圍內。應理解，整個說明書中引用的數值是示例，且可使用不同的數值。蝕刻停止層54在元件晶粒42A和42B的側壁上延伸並接觸元件晶粒42A和42B的側壁。蝕刻停止層54可以是共形層，舉例來說，其水平部分的厚度T1A和垂直部分的厚度T1B實質上彼此相等；舉例來說，其差值(T1A-T1B)的絕對值小於厚度T1A和T1B的約20%，或小於約10%。
介電層56由與蝕刻停止層54的材料不同的材料形成。根據本揭露的一些實施例，介電層56由氧化矽形成，其可由TEOS形成，而當介電層56和蝕刻停止層54之間具有足夠的蝕刻選擇性(例如，高於約50)時，亦可使用其他介電材料，例如碳化矽、氮氧化矽、氧碳氮化矽或其他類似物。所述蝕刻選擇性是在後續製程中的蝕刻介電層56時，介電層56的蝕刻速率與蝕刻停止層54的蝕刻速率之比。介電層56的厚度T2可在約15kÅ(1.5μm)與約25kÅ(2.5μm)之間的範圍內。介電層56也可以是共形層，其 水平部分的厚度和垂直部分實質上彼此相等。
蝕刻停止層58由與介電層56的材料不同的材料形成。蝕刻停止層58與蝕刻停止層54的材料可彼此相同或彼此不同。根據本揭露的一些實施例，蝕刻停止層58由氮化矽、氧化矽、碳化矽、氧氮化矽、氧碳氮化矽或其類似物形成。蝕刻停止層58的厚度T3可以在約3kÅ與約5kÅ之間的範圍內。蝕刻停止層58也可以是共形層，其水平部分的厚度和垂直部分實質上彼此相等。介電層56的厚度T3也可以大於、等於或小於蝕刻停止層54的厚度T1，這取決於厚度T4(圖4)是否分別大於、等於或小於厚度T1。根據本揭露的一些實施例，由於厚度T2小於厚度T4(圖4)，且開口66的蝕刻已經同步在蝕刻停止層58上，因此蝕刻停止層54的厚度T1可以小於蝕刻停止層58的厚度T3而不會犧牲蝕刻停止層54的蝕刻停止能力。
介電層60由與蝕刻停止層58的材料不同的材料形成。根據本揭露的一些實施例，介電層60由氧化矽形成，其可由TEOS形成，而當介電層60和蝕刻停止層58之間具有足夠的蝕刻選擇性(例如，高於約50)時，亦可使用其他介電材料，例如碳化矽、氮氧化矽、氧碳氮化矽、PSG、BSG、BPSG或其類似物。所述蝕刻選擇性是在後續製程中的蝕刻介電層60時，介電層60的蝕刻速率與蝕刻停止層58的蝕刻速率之比。介電層60可使用CVD、高密度電漿化學氣相沉積法(High-Density Plasma Chemical Vapor Deposition，HDPCVD)、FCVD、旋塗法或其類似方法形成。介電 層60完全填充剩餘的間隙53(圖2)，且沒有產生縫隙和孔洞在介電層60中。
參考圖4，進行平坦化製程(例如，化學機械研磨製程或機械研磨製程)，以移除間隙填充層60、58、56以及54的多餘部分，使得元件晶粒42A和42B暴露出來。相應的製程被繪示在圖17所示的製程流程中的步驟208。另外，穿孔46A和46B被暴露出來。層54、56、58以及60的剩餘部分統稱為(間隙填充)隔離區65。所形成的介電層60的厚度T4可在隔離區65的高度H1的約60%和約90%之間的範圍內。根據本揭露的一些實施例，隔離區65的高度H1大於約18μm，且可以在約20μm和約30μm之間的範圍內。
圖5繪示出蝕刻介電層60以形成開口66。相應的製程被繪示在圖17中所示的製程流程中的步驟210。根據本揭露的一些實施例，形成光阻68並將其圖案化，並使用圖案化的光阻68作為蝕刻罩幕來蝕刻介電層60。由此形成開口66，並向下延伸至用以當作蝕刻停止層的蝕刻停止層58。根據本揭露的一些實施例，介電層60包括氧化物，且所述蝕刻可以通過乾式蝕刻來進行。蝕刻氣體可包括NF3和NH3的混合物，或HF和NH3的混合物。使用蝕刻停止層58來停止用於形成開口66的蝕刻，使得同一晶圓2上的多個開口66同步向下行進在同一中間階段，因此，較快蝕刻的開口將在它們再次向下延伸之前等待較慢蝕刻的開口。
應當理解，晶圓2具有翹曲，這可能足以使不同的開口 66延伸到不同的水平。當隔離區65的厚度或高度H1大於特定值(其受到隔離區65的技術和材料等各種因素影響)時，如果形成單一介電層和單一蝕刻停止層，則用以形成開口66的蝕刻會面臨一些問題。也就是說，一些開口可能到達蝕刻停止層時，其他開口將無法到達蝕刻停止層。結果，導致了由於在開口中所形成的通孔未能到達並穿透單一蝕刻停止層而將形成開路(open circuit)的通孔開口問題。這個問題不能夠藉由增加過度刻蝕時間來解決，因為增加過度刻蝕時間亦會導致其他問題。根據本揭露的一些實施例，形成兩個蝕刻停止層54和58以及兩個介電層56和60，使得介電層60的厚度T4小於高度H1。厚度T4被選擇使得介電層60的蝕刻落入相應的製程裕度內，且所有開口66能夠到達並且停在蝕刻停止層58上。
參照圖6，蝕刻蝕刻停止層58，使得開口66向下延伸到介電層56。相應的製程被繪示在圖17所示的製程流程中的步驟212。根據本揭露的一些實施例，蝕刻停止層58包括氮化矽，並且使用乾式蝕刻法進行蝕刻。乾式氣體可包括CF4、O2以及N2的混合物、NF3和O2的混合物、SF6、或SF6和O2的混合物。蝕刻停止層58與介電層56之間亦具有高蝕刻選擇性，因此所述蝕刻停止在介電層56上，其中介電層56亦用作蝕刻層58的蝕刻停止層。
圖7繪示出介電層56的蝕刻，以進一步將開口66向下延伸至蝕刻停止層54，其用以當作蝕刻介電層56的蝕刻停止層。 相應的製程被繪示在圖17所示的製程流程中的步驟214。根據本揭露的一些實施例，介電層60包括氧化物。所述蝕刻可藉由乾式蝕刻法來進行。蝕刻氣體可包括NF3和NH3的混合物，或HF和NH3的混合物。
參照圖8，進一步蝕刻蝕刻停止層54，使得開口66向下延伸到接合墊40B，接觸墊40B外露於開口66。相應的製程被繪示在圖17所示的製程流程中的步驟216。蝕刻製程也可以是乾式蝕刻製程。根據本揭露的一些實施例，蝕刻停止層54由氮化矽形成，且使用乾式蝕刻法進行蝕刻。蝕刻氣體可包括CF4、O2以及N2的混合物、NF3和O2的混合物、SF6、或SF6和O2的混合物。然後，移除光阻68。
根據本揭露的替代實施例，在共同的蝕刻製程中使用相同的蝕刻氣體來蝕刻層56和54，其中所述蝕刻氣體被選擇用以蝕刻層56和54兩者，且層56與蝕刻停止層54之間的蝕刻選擇性相對較小，舉例來說，在約2和約10之間的範圍內，或在約5和10之間的範圍內。因此，儘管層54的蝕刻速率相對較小，但是當層54薄於上覆層時，仍可使用與蝕刻層56相同的蝕刻氣體來蝕刻層54。
圖9繪示出穿孔70的形成，其填充開口66(圖8)，並連接到接合墊40B。相應的製程被繪示在圖17中所示的製程流程中的步驟218。根據本揭露的一些實施例，穿孔70的形成包括進行鍍覆製程，例如電化學鍍覆製程或無電鍍覆製程。穿孔70可包 括金屬材料，例如鎢、鋁、銅或其類似物。導電阻障層(例如，鈦、氮化鈦、鉭、氮化鉭或其類似物)也可以形成在金屬材料下方。進行例如CMP的平坦化，以移除經鍍覆金屬材料的多餘部分，而金屬材料的剩餘部分則形成穿孔70。穿孔70可具有實質上筆直且垂直的側壁。另外，穿孔70可具有錐形輪廓，頂部寬度略大於相應的底部寬度。
根據替代實施例，TSVs 46A和46B未在元件晶粒42A和42B中預先形成。相反，它們是在元件晶粒42A和42B與晶粒4接合之後形成。舉例來說，在形成開口66之前或之後(圖8)，蝕刻元件晶粒42A和42B以形成另外的開口(由繪示的TSVs 46A和46B佔據)。在元件晶粒42A和42B中的附加開口以及開口66中可同時被填充，以形成TSVs 46A和46B以及穿孔70。所形成的穿孔46A和46B可具有上部分，其寬於相應的下部分，如圖9所示。反之，根據一些實施例，TSVs 46A和46B在接合之前預先形成，TSVs 46A和46B可具有上部寬度(如虛線71所示)，其小於相應的底部寬度，其與穿孔70相反。
參照圖10，形成重分佈線(redistribution lines，RDLs)72和介電層74。相應的製程被繪示在圖17中所示的製程流程中的步驟220。根據本揭露的一些實施例，介電層74由氧化物(例如氧化矽)、氮化物(例如氮化矽)或其類似物形成。RDLs 72可使用金屬鑲嵌製程形成，其包括蝕刻介電層74以形成開口，將導電阻障層沉積到開口中，鍍覆例如銅或銅合金的金屬材料，並進行 平坦化以去除RDLs 72的多餘部分。
圖11繪示出鈍化層、金屬墊以及上覆介電層的形成。鈍化層76(有時稱為第一鈍化層)形成在介電層74上，並且通孔78形成在鈍化層76中以電性連接到RDLs 72。金屬墊80形成在鈍化層76上方，且藉由通孔78電性耦接到RDLs 72。相應的製程亦被繪示在圖17中所示的製程流程中的步驟220。金屬墊80可以是鋁接墊或鋁銅接墊，也可以使用其他金屬材料。
如圖11所示，在鈍化層76上形成鈍化層82(有時稱為第二鈍化層)。各鈍化層76和82可以是單層或複合層，且可由非多孔的材料形成。根據本揭露的一些實施例，鈍化層76和82中的一個或兩個是複合層，其包括氧化矽層(未個別示出)以及在氧化矽層上的氮化矽層(未個別示出)。鈍化層76和82也可由其他非多孔的介電材料形成，例如USG、氧氮化矽以及/或其類似物。
接下來，圖案化鈍化層82，使得鈍化層82的一些部分覆蓋金屬墊80的邊緣部分，而金屬墊80的另一些部分外露於鈍化層82中的開口。然後形成聚合物層84，接著圖案化以暴露出金屬墊80。聚合物層84可由聚醯亞胺、聚苯並噁唑(polybenzoxazole，PBO)或其類似物形成。
依據本揭露的一些實施例，在金屬墊80下方的結構是不含有機材料(如聚合物層)，因此，用於形成在金屬墊80下方的結構的製造步驟可適用於形成元件晶粒的製程，且可能形成具有小間距和線寬的精細間距RDLs(例如72)。
參照圖12，形成鈍化後互連件(PPIs)86，其可包括形成金屬晶種層、在金屬晶種層上形成圖案化的罩幕層(未繪示)以及在圖案化的罩幕層中鍍覆PPIs 86。相應的製造亦被繪示在圖17中所示的製程流程中的步驟220。然後在蝕刻製程中去除圖案化的罩幕層和與圖案化的罩幕層重疊的部分金屬晶種層。然後形成聚合物層88，其可由PBO、聚醯亞胺或其類似物形成。
參照圖13，形成凸塊下金屬(Under-Bump Metallurgy，UBMs)90，而UBMs 90延伸到聚合物層88中以連接到PPIs 86。相應的製造亦被繪示在圖17中所示的製程流程中的步驟220。根據本揭露的一些實施例，各UBMs 90包括阻障層(未繪示)和阻障層上方的晶種層(未繪示)。阻障層可以是鈦層、氮化鈦層、鉭層、氮化鉭層，或由鈦合金或鉭合金形成的層。晶種層的材料可包括銅或銅合金。UBMS 90中還可以包括其他金屬，例如銀、金、鋁、鈀、鎳、鎳合金、鎢合金、鉻、鉻合金及其組合。
亦如圖13所示，形成電連接件92。相應的製造亦被繪示在圖17中所示的製程流程中的步驟220。用於形成UBMs 90和電連接件92的示例性形成製程包括：沉積毯覆式的UBM層、形成並圖案化罩幕(其可以是光阻，未繪示)，其中部分毯覆式的UBM層外露於罩幕中的開口。在形成UBMs 90之後，將所示的封裝件放入鍍覆液(未繪示)中，並進行鍍覆步驟以在UBMs 90上形成電連接件92。根據本揭露的一些示例性實施例，電連接件92包括非焊料部(未繪示)，其在後續的回焊製程中不熔化。非焊料部分 可由銅形成，因此在下文中稱為銅凸塊，儘管它們可以由其他非焊料材料形成。各電連接件92還可以包括選自鎳層、鎳合金、鈀層、金層、銀層或其多層的頂蓋層(未繪示)。頂蓋層形成在銅凸塊上方。電連接件92還可以包括焊料蓋，其可由Sn-Ag合金、Sn-Cu合金、Sn-Ag-Cu合金或其類似物形成，並且可以是不含鉛或含鉛。在前述步驟中所形成的結構稱為複合晶圓94。在複合晶圓94上進行晶粒切割(單體化)步驟，以將複合晶圓94分割成多個封裝件96。相應的製程亦被繪示在圖17中所示的製程流程中的步驟222。
圖14繪示出根據替代實施例的複合晶圓94和封裝件96。除了進一步形成蝕刻停止層62和介電層64之外，這些實施例與圖13所示的實施例類似。當隔離區65的厚度太厚且兩個蝕刻停止層54和58不能解決通孔開口問題時，則適用這些實施例。各蝕刻停止層62可選自與用於形成蝕刻停止層54和58的候選材料相似的材料形成。介電層64可選自用於形成介電層56和60的候選材料的材料形成。開口66(圖8)的形成因此進一步包括額外的蝕刻製程，其使用蝕刻停止層62來停止用於蝕刻介電層64的蝕刻，以及使用介電層60來停止用於蝕刻蝕刻停止層62的蝕刻。根據本揭露的一些實施例，各層64、62、60、58和56的蝕刻是使用相應的下層作為蝕刻停止層來進行。根據替代實施例，各層64和62的蝕刻分別停止在層62和60上，而一些下方的介電層60和56和相應的下方的蝕刻停止層58和54可共享共同的製程。舉例來說，層60和58可以(或可以不)使用共同的蝕刻氣體來共 享共同的蝕刻製程，且蝕刻可以停止在用作蝕刻停止層的層56上。層56和54可以(或可以不)使用共同的蝕刻氣體來共享共同的蝕刻製程，並且蝕刻可以停止在充當蝕刻停止層的金屬墊40B上。
圖15繪示出嵌入有封裝件96(圖13和14)的封裝件98。封裝件包括記憶體立方體100，其包括多個堆疊記憶體晶粒(未單獨示出)。封裝件96和記憶體立方體100包封在可以是模製化合物的包封材料102中。介電層和RDLs(統稱為104)位於封裝件96和記憶體立方體100之下且連接至封裝件96和記憶體立方體100。
圖16繪示出疊層封裝(Package-on-Package，PoP)結構106，其具有與頂部封裝件110接合的整合式扇出(Integrated Fan-Out，InFO)封裝件108。InFO封裝件108還包括嵌入於其中的封裝件96。封裝件96和穿孔112包封於可以是模塑化合物的包封材料114中。封裝件96接合至介電層和RDLs，統稱為116。
本揭露的實施例具有一些有利特徵。通過形成多個蝕刻停止層，隔離區的蝕刻可在所述蝕刻製程進一步進行之前在中間階段同步。這使得同一晶片上的多個開口能夠到達具有很大厚度/高度的隔離區的底部。因此，晶片的翹曲不會影響隔離區中穿孔的良率。
根據本揭露的一些實施例，一種方法包括：將第一與第二元件晶粒接合至第三元件晶粒、形成多個間隙填充層以在第一和第二元件晶粒之間延伸以及進行第一蝕刻製程以蝕刻多個間隙填 充層中的第一介電層，藉此形成開口。多個間隙填充層中的第一蝕刻停止層用以停止第一蝕刻製程。然後，將開口延伸穿過第一蝕刻停止層。進行第二蝕刻製程以將開口延伸穿過第一蝕刻停止層下方的第二介電層。第二蝕刻製程停在多個間隙填充層中的第二蝕刻停止層上。該方法還包括將開口延伸穿過第二蝕刻停止層，並用導電材料填充開口以形成穿孔。在一實施例中，接合第一元件晶粒和第二元件晶粒包括混合接合。在一實施例中，第二蝕刻停止層包括氮化矽層。在一實施例中，第二蝕刻停止層、第二介電層以及第一蝕刻停止層是共形介電層。在一實施例中，將開口延伸穿過第一蝕刻停止層包括使用第二介電層作為蝕刻停止層來蝕刻第一蝕刻停止層。在一實施例中，該方法還包括，在形成多個間隙填充層之前，薄化第一元件晶粒和第二元件晶粒。在一實施例中，該方法還包括，在多個間隙填充層形成之前，平坦化第一元件晶粒和第二元件晶粒以暴露出第一元件晶粒和第二元件晶粒中的穿孔。在一實施例中，第一元件晶粒、第二元件晶粒、第三元件晶粒以及多個間隙填充層不含有機介電材料。在一實施例中，該方法還包括在第一元件晶粒和第二元件晶粒上形成重分佈線，其中重分佈線與穿孔電性連接。
根據本揭露的一些實施例，一種方法包括：將多個元件晶粒接合至元件晶圓；在多個元件晶粒之間形成隔離區，其中形成隔離區包括：形成第一蝕刻停止層，其具有接觸多個元件晶粒的側壁部分和接觸元件晶圓的頂表面的底部部分；在第一蝕刻停止層上 形成第一介電層；在第一介電層上形成第二蝕刻停止層；以及在第二蝕刻停止層上形成第二介電層；蝕刻隔離區以形成穿透隔離區的第一開口和第二開口，其中元件晶圓的接合墊暴露於第一開口和第二開口，並且在蝕刻隔離區期間，第二蝕刻停止層用以停止蝕刻；將導電材料填充第一開口和第二開口，形成第一穿孔和第二穿孔。在一實施例中，第一蝕刻停止層、第一介電電層以及第二蝕刻停止層是使用共形沉積法形成。在一實施例中，第一蝕刻停止層、第一介電層以及第二蝕刻停止層是使用化學氣相沉積形成的。在一實施例中，第一蝕刻停止層薄於第二蝕刻停止層。在一實施例中，接合所述多個元件晶粒包括混合接合。在一實施例中，該方法還包括蝕刻多個元件晶粒以形成額外的開口；以及填充額加的開口以形成穿孔，其穿透多個元件晶粒的半導體基底，其中額加的開口、第一開口以及第二開口同時被填充。
根據本揭露的一些實施例，一種封裝件包括第一元件晶粒；第二元件晶粒和第三元件晶粒接合至第一元件晶粒；第二元件晶粒和第三元件晶粒之間的隔離區，其中隔離區包括：第一蝕刻停止層，其具有與第一和第二元件晶粒接觸的側壁部分以及與第一元件晶粒的頂表面接觸的底部部分；第一蝕刻停止層上的第一介電層；第一介電層上的第二蝕刻停止層；第二蝕刻停止層上的第二介電層；穿透隔離區的穿孔，其電性連接到第一元件晶粒。在一實施例中，穿孔穿過隔離區中的所有介電層。在一實施例中，穿孔是錐形的，其上部分逐漸寬於相對應的下部分。在一實施例中，第一 蝕刻停止層的厚度小於第二蝕刻停止層的厚度。在一實施例中，第一蝕刻停止層、第一介電電層以及第二蝕刻停止層是共形層。
前文概述若干實施例的特徵使得本領域的技術人員可更佳地理解本揭露的態樣。本領域的技術人員應理解，其可易於使用本揭露作為設計或修改用於實現本文中所引入的實施例的相同目的及/或達成相同優點的其他製程及結構的基礎。本領域的技術人員亦應認識到，這些等效構造並不脫離本揭露的精神及範疇，且本領域的技術人員可在不脫離本揭露的精神及範疇的情況下在本文中進行各種改變、替代及更改。
200‧‧‧製程流程
202、204、206、208、210、212、214、216、218、220、222‧‧‧步驟

Claims (10)

  1. 一種封裝件的製造方法，包括：將第一元件晶粒與第二元件晶粒接合至第三元件晶粒；形成多個間隙填充層，以在所述第一元件晶粒與所述第二元件晶粒之間延伸；進行第一蝕刻製程，以蝕刻所述多個間隙填充層中的第一介電層，藉此形成開口，其中在所述多個間隙填充層中且在所述第一介電層下方的第一蝕刻停止層用以停止所述第一蝕刻製程；將所述開口延伸穿過所述第一蝕刻停止層；進行第二蝕刻製程，以將所述開口延伸穿過所述多個間隙填充層中且在所述第一蝕刻停止層下方的第二介電層，其中所述第二蝕刻製程停止在所述多個間隙填充層中的第二蝕刻停止層上；將所述開口延伸穿過所述第二蝕刻停止層；以及將導電材料填入所述開口，以形成穿孔。
  2. 如申請專利範圍第1項所述的封裝件的製造方法，其中將所述第一元件晶粒與所述第二元件晶粒接合至所述第三元件晶粒包括混合接合。
  3. 如申請專利範圍第1項所述的封裝件的製造方法，更包括：在形成所述多個間隙填充層之前，薄化所述第一元件晶粒與所述第二元件晶粒。
  4. 如申請專利範圍第1項所述的封裝件的製造方法，更包括：在所述多個間隙填充層形成之前，平坦化所述第一元件晶粒與 所述第二元件晶粒以暴露出所述第一元件晶粒與所述第二元件晶粒中的穿孔。
  5. 如申請專利範圍第1項所述的封裝件的製造方法，其中所述第一元件晶粒、所述第二元件晶粒、所述第三元件晶粒以及所述多個間隙填充層均不含有機介電材料。
  6. 一種封裝件的製造方法包括：將多個元件晶粒接合至元件晶圓；在所述多個元件晶粒之間形成隔離區，其中所述形成所述隔離區包括：形成第一蝕刻停止層，其具有接觸所述多個元件晶粒的側壁部分與接觸所述元件晶圓的頂表面的底部部分；在所述第一蝕刻停止層上形成第一介電層；在所述第一介電層上形成第二蝕刻停止層；以及在所述第二蝕刻停止層上形成第二介電層；蝕刻所述隔離區以形成穿透所述隔離區的第一開口，其中所述元件晶圓的接合墊外露於所述第一開口，而在所述蝕刻所述隔離區期間，所述第二蝕刻停止層用以停止所述蝕刻；以及將導電材料填入所述第一開口，形成第一穿孔。
  7. 如申請專利範圍第6項所述的封裝件的製造方法，其中所述第一蝕刻停止層、所述第一介電層以及所述第二蝕刻停止層是使用共形沉積法形成的。
  8. 如申請專利範圍第6項所述的封裝件的製造方法，其中所述第一蝕刻停止層薄於所述第二蝕刻停止層。
  9. 如申請專利範圍第6項所述的封裝件的製造方法，更包括：蝕刻所述多個元件晶粒以形成第二開口；以及填充所述第二開口以形成第二穿孔，其穿透所述多個元件晶粒的半導體基底，其中所述第一開口與所述第二開口同時被填充。
  10. 一種封裝件：第一元件晶粒；第二元件晶粒與第三元件晶粒接合至所述第一元件晶粒；隔離區，位於所述第二元件晶粒與所述第三元件晶粒之間，其中所述隔離區包括：第一蝕刻停止層，具有接觸所述第三元件晶粒與所述第二元件晶粒的側壁部分以及接觸所述第一元件晶粒的頂表面的底部部分；第一介電層，位於所述第一蝕刻停止層上；第二蝕刻停止層，位於所述第一介電層上；以及第二介電層，位於所述第二蝕刻停止層上；以及穿孔，穿透所述隔離區以電性連接至所述第一元件晶粒。
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