CN109786264B - 用于封装件形成的工艺控制 - Google Patents

用于封装件形成的工艺控制 Download PDF

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CN109786264B
CN109786264B CN201811355244.6A CN201811355244A CN109786264B CN 109786264 B CN109786264 B CN 109786264B CN 201811355244 A CN201811355244 A CN 201811355244A CN 109786264 B CN109786264 B CN 109786264B
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etch stop
stop layer
device die
layer
dielectric layer
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CN109786264A (zh
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陈明发
陈宪伟
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括将第一器件管芯和第二器件管芯接合到第三器件管芯，形成在第一器件管芯和第二器件管芯之间延伸的多个间隙填充层，以及实施第一蚀刻工艺以蚀刻多个间隙填充层中的第一介电层以形成开口。多个间隙填充层中的第一蚀刻停止层用于停止第一蚀刻工艺。然后开口延伸穿过第一蚀刻停止层。实施第二蚀刻工艺以使开口延伸穿过第一蚀刻停止层下面的第二介电层。第二蚀刻工艺在多个间隙填充层中的第二蚀刻停止层上停止。该方法还包括使开口延伸穿过第二蚀刻停止层，以及用导电材料填充开口以形成通孔。本发明的实施例还涉及用于封装件形成的工艺控制。

Description

用于封装件形成的工艺控制
技术领域
本发明的实施例涉及用于封装件形成的工艺控制。
背景技术
集成电路的封装正变得越来越复杂，更多的器件管芯包封在同一封装件中以实现更多功能。例如，已经开发了封装件结构，以在同一封装件中包括多个器件管芯(例如处理器和存储器立方体)。封装件结构可以将使用不同技术形成并且具有不同功能的器件管芯接合到同一器件管芯，从而形成系统。这可以节省制造成本并且优化器件性能。
发明内容
本发明的实施例提供了一种形成封装件的方法，包括：将第一器件管芯和第二器件管芯接合到第三器件管芯；形成在所述第一器件管芯和所述第二器件管芯之间延伸的多个间隙填充层；实施第一蚀刻工艺以蚀刻所述多个间隙填充层中的第一介电层以形成开口，其中，所述多个间隙填充层中的第一蚀刻停止层和下面的所述第一介电层用于停止所述第一蚀刻工艺；使所述开口延伸穿过所述第一蚀刻停止层；实施第二蚀刻工艺以使所述开口延伸穿过所述多个间隙填充层中的第二介电层和下面的所述第一蚀刻停止层，其中，所述第二蚀刻工艺在所述多个间隙填充层中的第二蚀刻停止层上停止；使所述开口延伸穿过所述第二蚀刻停止层；以及用导电材料填充所述开口以形成通孔。
本发明的另一实施例提供了一种形成封装件的方法，包括：将多个器件管芯接合到器件晶圆；在所述多个器件管芯之间形成隔离区，其中，形成所述隔离区包括：形成第一蚀刻停止层，所述第一蚀刻停止层具有与所述多个器件管芯接触的侧壁部分和与所述器件晶圆的顶面接触的底部；在所述第一蚀刻停止层上形成第一介电层；在所述第一介电层上形成第二蚀刻停止层；以及在所述第二蚀刻停止层上形成第二介电层；蚀刻所述隔离区以形成穿过所述隔离区的第一开口，其中，所述器件晶圆的接合焊盘暴露于所述第一开口，并且在蚀刻所述隔离区期间，所述第二蚀刻停止层用于停止蚀刻；以及用导电材料填充所述第一开口以形成第一通孔和第二通孔。
本发明的又一实施例提供了一种封装件，包括：第一器件管芯；第二器件管芯和第三器件管芯，接合到所述第一器件管芯；隔离区，位于所述第二器件管芯和所述第三器件管芯之间，其中，所述隔离区包括：第一蚀刻停止层，具有与所述第一器件管芯和所述第二器件管芯接触的侧壁部分，以及与所述第一器件管芯的顶面接触的底部；第一介电层，位于所述第一蚀刻停止层上；第二蚀刻停止层，位于所述第一介电层上；以及第二介电层，位于所述第二蚀刻停止层上；以及通孔，穿过所述隔离区以电连接到所述第一器件管芯。
附图说明
当接合附图进行阅读时，从以下详细描述可最佳理解本发明的各个方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1至图13是根据一些实施例的封装件的制造中的中间阶段的截面图。
图14示出了根据一些实施例的封装件的截面图。
图15和图16示出了根据一些实施例的嵌入附加封装件结构的封装件的截面图。
图17示出了根据一些实施例的用于形成封装件结构的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征不同的实施例或实例。下面描述了组件和布置的具体实施例或实例以简化本发明。当然这些仅是实例而不旨在限制。例如，元件的尺寸不限于所公开的范围或值，但可能依赖于工艺条件和/或器件所需的性能。此外，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。为了简单和清楚的目的，各个部件可以以不同的比例任意地绘制。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等的空间关系术语，以描述如图中所示的一个元件或部件与另一元件或部件的关系。除了图中所示的方位外，空间关系术语旨在包括器件在使用或操作工艺中的不同方位。装置可以以其它方式定位(旋转90度或在其它方位)，并且在本文中使用的空间关系描述符可以同样地作相应地解释。
根据各种示例性实施例提供了封装件及其形成方法。根据一些实施例示出了形成封装件的中间阶段。讨论了一些实施例的一些变型。在各种视图和说明性实施例中，相同的附图标记用于表示相同的元件。
图1至图13示出了根据本发明的一些实施例的封装件的形成中的中间阶段的截面图。图1至图13中所示的步骤也在图17中所示的工艺流程200中示意性地反映。
图1示出了晶圆2的形成中的截面图。相应的工艺示出为图17中所示的工艺流程中的工艺202。根据本发明的一些实施例，晶圆2是器件晶圆，包括诸如晶体管和/或二极管的有源器件以及可能的无源器件(例如电容器、电感器、电阻器等)。器件晶圆2可以在其中包括多个芯片4，其中示出了芯片4中的一个。在下文中，芯片4可选地称为(器件)管芯。根据本发明的一些实施例，器件管芯4是逻辑管芯，其可以是中央处理单元(CPU)管芯、微控制单元(MCU)管芯、输入-输出(IO)管芯、基带(BB)管芯或应用处理器(AP)管芯。器件管芯4也可以是存储器管芯，例如动态随机存取存储器(DRAM)管芯或静态随机存取存储器(SRAM)管芯。
根据本发明的可选实施例，封装组件2包括无源器件(没有有源器件)。在随后的讨论中，器件晶圆被讨论为示例性封装组件2。本发明的实施例还可以应用于其他类型的封装组件，例如插入器晶圆。
根据本发明的一些实施例，示例性晶圆2包括半导体衬底20和形成在半导体衬底20的顶面处的部件。半导体衬底20可以由晶体硅、晶体锗、晶体硅锗和/或III-V族化合物半导体(例如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等)形成。半导体衬底20也可以是体硅衬底或绝缘体上硅(SOI)衬底。可以在半导体衬底20中形成浅沟槽隔离(STI)区(未示出)以隔离半导体衬底20中的有源区。虽然未示出，但是可以形成贯通孔以延伸到半导体衬底20中，其中贯通孔用于电互连晶圆2的相对侧上的部件。
根据本发明的一些实施例，晶圆2包括集成电路器件22，集成电路器件22形成在半导体衬底20的顶面上。示例性集成电路器件22可以包括互补金属氧化物半导体(CMOS)晶体管、电阻器、电容器、二极管等。这里未示出集成电路器件22的细节。根据可选实施例，晶圆2用于形成中介层，其中衬底20可以是半导体衬底或介电衬底。
层间电介质(ILD)24形成在半导体衬底20上方并且填充集成电路器件22中的晶体管(未示出)的栅极堆叠件之间的间隔。根据一些示例性实施例，ILD 24由磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、氟掺杂的硅酸盐玻璃(FSG)、正硅酸乙酯(TEOS)等形成。可以使用旋涂、可流动化学气相沉积(FCVD)、化学气相沉积(CVD)等形成ILD 24。根据本发明的一些实施例，使用诸如等离子体增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)等的沉积方法形成ILD 24。
接触插塞28形成在ILD 24中，并且用于将集成电路器件22电连接到上面的金属线和通孔。根据本发明的一些实施例，接触插塞28由选自钨、铝、铜、钛、钽、氮化钛、氮化钽、它们的合金和/或它们的多层的导电材料形成。接触插塞28的形成可以包括在ILD 24中形成接触开口，将导电材料填充到接触开口中，以及实施平坦化(诸如化学机械抛光(CMP)工艺)以使接触插塞28的顶面与ILD 24的顶面齐平。
互连结构30位于ILD 24和接触插塞28上方。互连结构30包括形成在介电层32中的金属线34和通孔36。介电层32在下文中可选地称为金属间介电(IMD)层32。根据本发明的一些实施例，至少下介电层32由低k介电材料形成，该低k介电材料具有低于约3.0、约2.5或甚至更低的介电常数(k值)。介电层32可以由Black Diamond(应用材料公司的注册商标)、含碳的低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等形成。根据本发明的可选实施例，介电层32中的一些或全部由非低k介电材料形成，例如氧化硅、碳化硅(SiC)、碳氮化硅(SiCN)、碳氧氮化硅(SiOCN)等。根据本发明的一些实施例，介电层32的形成包括沉积含致孔剂的介电材料，然后实施固化工艺以驱除致孔剂，因此剩余的介电层32是多孔的。可以由碳化硅、氮化硅等形成的蚀刻停止层(未示出)形成在IMD层32之间，并且为了简单起见未示出。
金属线34和通孔36形成在介电层32中。以下将相同层级的金属线34统称为金属层。根据本发明的一些实施例，互连结构30包括通过通孔36互连的多个金属层。金属线34和通孔36可以由铜或铜合金形成，并且它们也可以由其他金属形成。形成工艺可以包括单镶嵌和双镶嵌工艺。在示例性单镶嵌工艺中，首先在介电层32之一中形成沟槽，然后用导电材料填充沟槽。然后实施诸如CMP工艺的平坦化工艺以去除高于IMD层的顶面的导电材料的多余部分，在沟槽中留下金属线。在双镶嵌工艺中，沟槽和通孔开口都形成在IMD层中，通孔开口位于沟槽下方并且连接到沟槽。然后将导电材料填充到沟槽和通孔开口中以分别形成金属线和通孔。导电材料可以包括扩散阻挡层和位于扩散阻挡层上方的含铜金属材料。扩散阻挡层可以包括钛、氮化钛、钽、氮化钽等。
图1示出了根据本发明的一些实施例的表面介电层38。表面介电层38由诸如氧化硅的非低k介电材料形成。表面介电层38可选地称为钝化层，因为它具有将下面的低k介电层(如果有的话)与有害化学品和湿气的不利影响隔离的功能。表面介电层38还可以具有包括多于一层的复合结构，其可以由氧化硅、氮化硅、未掺杂的硅酸盐玻璃(USG)等形成。器件管芯4还可以包括金属焊盘(例如铝或铝铜焊盘)、钝化后互连(PPI)等，为简单起见未示出。
在表面介电层38中形成接合焊盘40A和40B，其也共同或单独地称为接合焊盘40。根据本发明的一些实施例，接合焊盘40A和40B通过单镶嵌工艺形成，并且还可以包括阻挡层和形成在阻挡层上的含铜材料。根据本发明的可选实施例，可以通过双镶嵌工艺形成接合焊盘40A和40B。
根据本发明的一些实施例，在晶圆2中不存在诸如聚合物层的有机介电材料。有机介电层通常具有高的热膨胀系数(CTE)，例如10ppm/℃或更高。这显着大于硅衬底(例如衬底20)的CTE，其为约3ppm/℃。因此，有机介电层倾向于引起晶圆2的翘曲。晶圆2中不包括有机材料有利地减少了晶圆2中的层之间的CTE失配，并且导致翘曲的减小。而且，晶圆2中不包括有机材料使得可以形成细间距金属线(例如图10中的72)和高密度接合焊盘，并且导致路由能力的提高。
平坦化顶面介电层38和接合焊盘40，使得它们的顶面是共面的，这可能是由于在形成接合焊盘40中的CMP而产生的。
接下来，器件管芯42A和42B接合到晶圆2，如图2所示。相应的工艺示出为图17中所示的工艺流程中的工艺204。根据本发明的一些实施例，每个器件管芯42A和42B可以是逻辑管芯，其可以是CPU管芯、MCU管芯、IO管芯，基带管芯或AP管芯。器件管芯42A和42B可以包括存储器管芯。器件管芯42A和42B可以是从上面列出的类型中选择的不同类型的管芯。此外，器件管芯42A和42B可以使用不同的技术形成，例如45nm技术、28nm技术、20nm技术等。而且，器件管芯42A和42B中的一个可以是数字电路管芯，而另一个可以是模拟电路管芯。管芯4、42A和42B组合起来作为系统。将系统的功能和电路分成诸如管芯4、42A和42B的不同管芯可以优化这些管芯的形成，并且可以导致制造成本的降低。
器件管芯42A和42B分别包括半导体衬底44A和44B，其可以是硅衬底。硅通孔(TSV)46A和46B(有时称为半导体通孔或通孔)形成为分别穿透半导体衬底44A和44B。TSV 46A和46B用于将形成在半导体衬底44A和44B的正面(图示的底侧)上的器件和金属线连接到背面。而且，器件管芯42A和42B分别包括互连结构48A和48B，用于连接到器件管芯42A和42B中的有源器件和无源器件。互连结构48A和48B包括金属线和通孔(未示出)。
器件管芯42A包括位于器件管芯42A的所示底面处的接合焊盘50A和介电层52A。接合焊盘50A的底面与介电层52A的底面共面。器件管芯42B包括位于所示底面处的接合焊盘50B和介电层52B。接合焊盘50B的底面与介电层52B的底面共面。根据本发明的一些实施例，诸如管芯42A和42B的所有器件管芯不含有机介电材料，例如聚合物。
可以通过混合接合来实现接合。例如，接合焊盘50A和50B通过金属-金属直接接合接合到接合焊盘40A。根据本发明的一些实施例，金属-金属直接接合是铜-铜直接接合。此外，例如，介电层52A和52B通过生成的Si-O-Si键接合到表面介电层38。
为了实现混合接合，首先通过将器件管芯42A和42B轻轻压向管芯4，将器件管芯42A和42B预先接合到介电层38和接合焊盘40A。尽管示出了两个器件管芯42A和42B，可以在晶圆级实施混合接合，并且预接合与包括器件管芯42A和42B的所示管芯组相同的多个器件管芯组，并且布置为行和列。
在预接合所有器件管芯42A和42B之后，实施退火以引起接合焊盘40A和对应的上面的接合焊盘50A和50B中的金属的相互扩散。根据一些实施例，退火温度可以在约200°和约400℃之间的范围内，并且可以在约300°和约400℃之间的范围内。根据一些实施例，退火时间可以在约1.5小时和约3.0小时之间的范围内，并且可以在约1.5小时和约2.5小时之间的范围内。通过混合接合，接合焊盘50A和50B通过由金属相互扩散引起的直接金属接合而接合到对应的接合焊盘40A。接合焊盘50A和50B可以与对应的接合焊盘40A形成可区分的界面。
介电层38也接合到介电层52A和52B，其间形成有接合。例如，介电层38和52A/52B之一中的原子(例如氧原子)与介电层38和52A/52B中的另一个中的原子(例如硅原子)形成化学键或共价键。介电层38和52A/52B之间产生的接合是电介质-电介质接合。接合焊盘50A和50B的尺寸可以大于、等于或小于相应接合焊盘40A的尺寸。间隙53留在相邻的器件管芯42A和42B之间。
进一步参考图2，可以对薄器件管芯42A和42B实施背面研磨至例如厚度在约15μm和约30μm之间。图2示意性地示出了虚线44A-BS1和44B-BS1，它们分别是在背面研磨之前的器件管芯42A和42B的背面。44A-BS2和44B-BS2分别是在背面研磨之后的器件管芯42A和42B的背面。通过减薄器件管芯42A和42B，减小了相邻器件管芯42A和42B之间的间隙53的高宽比，以便实施间隙填充。否则，由于间隙53的高高宽比，间隙填充可能是困难的。在背面研磨之后，可能露出TSV 46A和46B。或者，此时TSV 46A和46B未露出，并且当存在覆盖TSV 46A和46B的衬底的薄层时停止背面研磨。根据这些实施例，TSV 46A和46B可以在图4所示的步骤中露出来。根据其他实施例，其中间隙53的高宽比对于间隙填充而言不太高，跳过背面研磨。
图3示出了多个间隙填充层的形成，其包括介电层和下面的蚀刻停止层。相应的工艺示出为图17中所示的工艺流程中的工艺206。根据本发明的一些实施例，间隙填充层包括蚀刻停止层54、位于蚀刻停止层54上并且接触蚀刻停止层54的介电层56、位于介电层56上并且接触介电层56的蚀刻停止层58以及位于蚀刻停止层58上并且接触蚀刻停止层58的介电层60。层54、56和58可以顺序沉积，并且可以使用共形沉积方法沉积，例如原子层沉积(ALD)或化学气相沉积(CVD)。
蚀刻停止层54由介电材料形成，该介电材料对器件管芯42A和42B的侧壁以及介电层38和接合焊盘40B的顶面具有良好的粘附性。根据本发明的一些实施例，蚀刻停止层54由诸如氮化硅的含氮化物材料形成。蚀刻停止层54的厚度T1(包括T1A和T1B)可以在约
Figure BDA0001865917640000081
和约
Figure BDA0001865917640000082
之间的范围内。应该理解，整个说明书中引用的值是示例，并且可以使用不同的值。蚀刻停止层54在器件管芯42A和42B的侧壁上延伸并且接触器件管芯42A和42B的侧壁。蚀刻停止层54可以是共形层，例如，水平部分的厚度T1A和垂直部分的厚度T1B基本上彼此相等，例如，差值(T1A-T1B)的绝对值小于厚度T1A和T1B的约20％，或小于约10％。
介电层56由与蚀刻停止层54的材料不同的材料形成。根据本发明的一些实施例，介电层56由氧化硅形成，氧化硅可以由TEOS形成，而当在介电层56和蚀刻停止层54之间具有足够的蚀刻选择性(例如，高于约50)时，也可以使用其他介电材料，诸如碳化硅、氮氧化硅、碳氧氮化硅等。蚀刻选择性是在后续工艺中蚀刻介电层56时介电层56的蚀刻速率与蚀刻停止层54的蚀刻速率的比率。介电层56的厚度T2可以在约
Figure BDA0001865917640000091
(1.5μm)和约
Figure BDA0001865917640000092
(2.5μm)之间的范围内。介电层56也可以是共形层，水平部分和垂直部分的厚度基本上彼此相等。
蚀刻停止层58由与介电层56的材料不同的材料形成。蚀刻停止层58和蚀刻停止层54的材料可以彼此相同或彼此不同。根据本发明的一些实施例，蚀刻停止层58由氮化硅、氧化硅、碳化硅、氮氧化硅、碳氧氮化硅等形成。蚀刻停止层58的厚度T3可以在约
Figure BDA0001865917640000094
和约
Figure BDA0001865917640000093
之间的范围内。蚀刻停止层58也可以是共形层，水平部分和垂直部分的厚度基本上彼此相等。介电层56的厚度T3也可以大于、等于或小于蚀刻停止层54的厚度T1，这取决于厚度T4(图4)是分别大于、等于还是小于厚度T1。根据本发明的一些实施例，由于厚度T2小于厚度T4(图4)，并且开口66的蚀刻已在蚀刻停止层58上同步，因此蚀刻停止层54的厚度T1可以小于蚀刻停止层58的厚度T3，而不牺牲蚀刻停止层54的蚀刻停止能力。
介电层60由与蚀刻停止层58的材料不同的材料形成。根据本发明的一些实施例，介电层60由氧化硅形成，氧化硅可以由TEOS形成，而当在介电层60和蚀刻停止层58之间具有足够的蚀刻选择性(例如，高于约50)时，也可以使用诸如碳化硅、氮氧化硅、碳氧氮化硅、PSG、BSG、BPSG等的其他介电材料。蚀刻选择性是在后续工艺中蚀刻介电层60时介电层60的蚀刻速率与蚀刻停止层58的蚀刻速率的比率。可以使用CVD、高密度等离子体化学气相沉积(HDPCVD)、可流动化学气相沉积(CVD)、旋涂等形成介电层60。介电层60完全填充剩余的间隙53(图2)，并且在介电层60中不产生缝隙和空隙。
参考图4，实施诸如CMP工艺或机械研磨工艺的平坦化工艺以去除间隙填充层60、58、56和54的多余部分，从而暴露器件管芯42A和42B。相应的工艺示出为图17中所示的工艺流程中的工艺208。此外，暴露出通孔46A和46B。层54、56、58和60的剩余部分统称为(间隙填充)隔离区65。介电层60的最终厚度T4可以在隔离区65的高度H1的约60％和约90％之间的范围内。根据本发明的一些实施例，隔离区65的高度H1大于约18μm，并且可以在约20μm和约30μm之间的范围内。
图5示出了介电层60的蚀刻以形成开口66。相应的工艺示出为图17中所示的工艺流程中的工艺210。根据本发明的一些实施例，形成并且图案化光刻胶68，并且使用图案化的光刻胶68作为蚀刻掩模来蚀刻介电层60。由此形成开口66，并且向下延伸到蚀刻停止层58，蚀刻停止层58用作蚀刻停止层。根据本发明的一些实施例，介电层60包括氧化物，并且蚀刻可以通过干蚀刻来实施。蚀刻气体可以包括NF3和NH3的混合物，或HF和NH3的混合物。使用蚀刻顶层58来停止用于形成开口66的蚀刻允许同一晶圆2上的多个开口66的向下行进在相同的中间层级处同步，使得更快蚀刻的开口将在它们再次向下延伸之前等待较慢蚀刻的开口。
应当理解，晶圆2具有翘曲，这可能足以使不同的开口66延伸到不同的层级。当隔离区的厚度高度H1大于特定值(受诸如技术和隔离区65的材料的各种因素影响)时，如果形成单个介电层和单个蚀刻停止层，则用于形成开口66的蚀刻经历问题，并且一些开口可以到达蚀刻停止层，而一些其他开口将不能到达蚀刻停止层。结果，由于在未能到达并且穿透单个蚀刻停止层的开口中形成的通孔将形成开路，因此产生了通孔开口问题。这个问题不能通过增加过蚀刻时间来解决，因为它会导致其他问题。根据本发明的一些实施例，形成两个蚀刻停止层54和58以及两个介电层56和60，使得介电层60的厚度T4小于高度H1。选择厚度T4，使得介电层60的蚀刻落入相应的工艺窗口内，并且所有开口66能够到达蚀刻停止层58并且停止在蚀刻停止层58上。
参考图6，蚀刻蚀刻停止层58，使得开口66向下延伸到介电层56。相应的工艺示出为图17中所示的工艺流程中的工艺212。根据本发明的一些实施例，蚀刻停止层58包括氮化硅，并且使用干蚀刻实施蚀刻。蚀刻气体可以包括CF4、O2和N2的混合物，NF3和O2的混合物，SF6，或SF6和O2的混合物。在蚀刻停止层58和介电层56之间还存在高蚀刻选择性，因此蚀刻在介电层56上停止，介电层56也用作蚀刻层58的蚀刻停止层。
图7示出了介电层56的蚀刻以进一步向下延伸开口66至蚀刻停止层54，蚀刻停止层54用作用于蚀刻介电层56的蚀刻停止层。相应的工艺示出为图17中所示的工艺流程中的工艺214。根据本发明的一些实施例，介电层60包括氧化物。可以通过干蚀刻进行蚀刻。蚀刻气体可以包括NF3和NH3的混合物，或HF和NH3的混合物。
参考图8，进一步蚀刻蚀刻停止层54，使得开口66向下延伸到接合焊盘40B，接合焊盘40B暴露于开口66。相应的工艺示出为图17中所示的工艺流程中的工艺216。蚀刻工艺也可以是干蚀刻工艺。根据本发明的一些实施例，蚀刻停止层54由氮化硅形成，并且使用干蚀刻实施蚀刻。蚀刻气体可以包括CF4、O2和N2的混合物，NF3和O2的混合物，SF6，或SF6和O2的混合物。然后去除光刻胶68。
根据本发明的可选实施例，在使用相同的蚀刻气体的共同的蚀刻工艺中蚀刻层56和54，选择蚀刻气体以蚀刻层56和54两者，并且层56和蚀刻停止层54之间的蚀刻选择性相对较小，例如，在约2和约10之间的范围内，或在约5和10之间的范围内。因此，尽管层54的蚀刻速率相对较小，当层54比上面的层薄时，仍然可以使用用于蚀刻层56的相同蚀刻气体来蚀刻层54。
图9示出了通孔70的形成，其填充开口66(图8)，并且连接到接合焊盘40B。相应的工艺示出为图17中所示的工艺流程中的工艺218。根据本发明的一些实施例，通孔70的形成包括实施诸如电化学镀工艺或化学镀工艺的镀工艺。通孔70可以包括金属材料，例如钨、铝、铜等。还可以在金属材料下面形成导电阻挡层(例如钛、氮化钛、钽、氮化钽等)。实施诸如CMP的平坦化以去除镀的金属材料的多余部分，并且金属材料的剩余部分形成通孔70。通孔70可以具有基本笔直和垂直的侧壁。而且，通孔70可以具有锥形轮廓，顶部宽度略大于相应的底部宽度。
根据可选实施例，TSV 46A和46B未预形成在器件管芯42A和42B中。相反，它们是在器件管芯42A和42B接合到管芯4之后形成的。例如，在形成开口66(图8)之前或之后，蚀刻器件管芯42A和42B以形成另外的开口(由图示的TSV 46A和46B所占据)。器件管芯42A和42B中的附加开口以及开口66可以同时填充以形成TSV 46A和46B以及通孔70。所得到的通孔46A和46B可以具有比相应的下部宽的上部，如图9所示。相反，根据一些实施例，其中在接合之前预形成TSV 46A和46B，TSV 46A和46B可以具有小于相应底部宽度的上部宽度(如虚线71示意性所示)，其是与通孔70相反。
参考图10，形成再分布线(RDL)72和介电层74。相应的工艺示出为图17中所示的工艺流程中的工艺220。根据本发明的一些实施例，介电层74由诸如氧化硅的氧化物、诸如氮化硅的氮化物等形成。RDL 72可以使用镶嵌工艺形成，其包括蚀刻介电层74以形成开口，将导电阻挡层沉积到开口中，镀诸如铜或铜合金的金属材料，以及实施平坦化以去除RDL 72的多余部分。
图11示出了钝化层、金属焊盘和上面的介电层的形成。在介电层74上形成钝化层76(有时称为钝化-1)，并且在钝化层76中形成通孔78以电连接到RDL 72。金属焊盘80形成在钝化层76上方，并且通过通孔78电耦合到RDL 72。相应的工艺也示出为图17中所示的工艺流程中的工艺220。金属焊盘80可以是铝焊盘或铝-铜焊盘，并且可以使用其他金属材料。
还如图11所示，在钝化层76上形成钝化层82(有时称为钝化-2)。钝化层76和82中的每一个可以是单层或复合层，并且可以由无孔材料形成。根据本发明的一些实施例，钝化层76和82中的一个或两个是复合层，包括氧化硅层(未单独示出)以及位于氧化硅层上的氮化硅层(未单独示出)。钝化层76和82也可以由其他无孔介电材料形成，例如未掺杂的硅酸盐玻璃(USG)、氮氧化硅等。
接下来，图案化钝化层82，使得钝化层82的一些部分覆盖金属焊盘80的边缘部分，并且金属焊盘80的一些部分通过钝化层82中的开口暴露。然后形成聚合物层84，并且然后图案化聚合物层84以暴露金属焊盘80。聚合物层84可以由聚酰亚胺、聚苯并且恶唑(PBO)等形成。
根据本发明的一些实施例，金属焊盘80下面的结构不含有机材料(例如聚合物层)，使得用于形成金属焊盘80下面的结构的工艺可以采用用于形成器件管芯的工艺，并且具有小间距和线宽的细间距RDL(例如72)成为可能。
参考图12，形成钝化后互连件(PPI)86，其可以包括形成金属晶种层和在金属晶种层上形成图案化的掩模层(未示出)，以及在图案化的掩模层中镀PPI 86。相应的工艺也示出为图17中所示的工艺流程中的工艺220。然后在蚀刻工艺中去除图案化的掩模层和与图案化的掩模层重叠的金属晶种层的部分。然后形成聚合物层88，聚合物层88可以由PBO、聚酰亚胺等形成。
参考图13，形成凸块下金属(UBM)90，并且UBM 90延伸到聚合物层88中以连接到PPI 86。相应的工艺也示出为图17中所示的工艺流程中的工艺220。根据本发明的一些实施例，UBM90中的每一个包括阻挡层(未示出)和位于阻挡层上的晶种层(未示出)。阻挡层可以是钛层、氮化钛层、钽层、氮化钽层或由钛合金或钽合金形成的层。晶种层的材料可以包括铜或铜合金。UBM 90中还可以包括其他金属，例如银、金、铝、钯、镍、镍合金、钨合金、铬、铬合金及其组合。
还如图13所示，形成电连接件92。相应的工艺也示出为图17中所示的工艺流程中的工艺220。用于形成UBM 90和电连接件92的示例性形成工艺包括沉积毯状UBM层，形成并且图案化掩模(其可以是光刻胶，未示出)，毯状UBM层的一部分通过掩模中的开口暴露。在形成UBM 90之后，将所示的封装件放入镀溶液(未示出)中，并且实施镀步骤以在UBM90上形成电连接件92。根据本发明的一些示例性实施例，电连接件92包括非焊料部分(未示出)，非焊料部分在随后的回流工艺中不熔化。非焊料部分可以由铜形成，因此在下文中称为铜凸块，但是它们可以由其他非焊料材料形成。每个电连接件92还可以包括选自镍层、镍合金、钯层、金层、银层或其多层的覆盖层(未示出)。覆盖层形成在铜凸块上方。电连接件92还可以包括焊帽，焊帽可以由Sn-Ag合金、Sn-Cu合金、Sn-Ag-Cu合金等形成，并且可以是无铅或含铅的。在前面的步骤中形成的结构称为复合晶圆94。对复合晶圆94实施管芯锯切(分割)步骤，以将复合晶圆94分成多个封装件96。相应的工艺也示出为图17所示的工艺流程中的工艺222。
图14示出了根据可选实施例的复合晶圆94和封装件96。除了进一步形成蚀刻停止层62和介电层64之外，这些实施例类似于图13中所示的实施例。当隔离区65的厚度太厚时采用这些实施例，并且两个蚀刻停止层54和58不能解决通孔开口问题。蚀刻停止层62可以由选自用于形成蚀刻停止层54和58的类似候选材料的材料形成。介电层64可以由选自用于形成介电层56和60的候选材料的材料形成。因此，开口66(图8)的形成还包括蚀刻介电层64的附加蚀刻工艺(使用蚀刻停止层62来停止蚀刻)，以及蚀刻蚀刻停止层62(使用介电层60来停止蚀刻)。根据本发明的一些实施例，使用相应的下面的层作为蚀刻停止层来实施层64、62、60、58和56中的每一个的蚀刻。根据可选实施例，层64和62中的每一个的蚀刻分别停止在层62和60上，而一些下面的介电层60和56以及相应的下面的蚀刻停止层58和54可以共享共同的工艺。例如，层60和58可以(或可以不)共享使用共同的蚀刻气体的共同的蚀刻工艺，并且蚀刻可以停止在层56上，层56用作蚀刻停止层。层56和54可以(或可以不)共享使用共同的蚀刻气体的共同的蚀刻工艺，并且蚀刻可以停止在金属焊盘40B上，金属焊盘40B用作蚀刻停止层。
图15示出了封装件98，其中嵌入了封装件96(图13和图14)。该封装件包括存储器立方体100，存储器立方体100包括多个堆叠的存储器管芯(未单独示出)。封装件96和存储器立方体100包封在包封材料102中，包封材料102可以是模塑料。介电层和RDL(统称为104)位于封装件96和存储器立方体100的下方并且连接到封装件96和存储器立方体100。
图16示出了叠层封装(PoP)结构106，其具有与顶部封装件110接合的集成扇出(InFO)封装件108。InFO封装件108还包括嵌入其中的封装件96。封装件96和通孔112包封在包封材料114中，包封材料114可以是模塑料。封装件96接合到介电层和RDL，RDL统称为116。
本发明的实施例具有一些有利特征。通过形成多个蚀刻停止层，在蚀刻工艺进一步进行之前，隔离区的蚀刻在中间层级处同步。这允许同一晶圆上的多个开口能够到达具有大厚度/高度的隔离区的底部。因此，晶圆的翘曲不会影响隔离区中的通孔的产量。
根据本发明的一些实施例，一种方法包括将第一器件管芯和第二器件管芯接合到第三器件管芯，形成在第一器件管芯和第二器件管芯之间延伸的多个间隙填充层，以及实施第一蚀刻工艺以蚀刻多个间隙填充层中的第一介电层以形成开口。多个间隙填充层中的第一蚀刻停止层用于停止第一蚀刻工艺。然后开口延伸穿过第一蚀刻停止层。实施第二蚀刻工艺以使开口延伸穿过第一蚀刻停止层下面的第二介电层。第二蚀刻工艺在多个间隙填充层中的第二蚀刻停止层上停止。该方法还包括使开口延伸穿过第二蚀刻停止层，以及用导电材料填充开口以形成通孔。在一个实施例中，第一器件管芯和第二器件管芯的接合包括混合接合。在一个实施例中，第二蚀刻停止层包括氮化硅层。在一个实施例中，第二蚀刻停止层、第二介电层和第一蚀刻停止层是共形介电层。在一个实施例中，使开口延伸穿过第一蚀刻停止层包括使用第二介电层作为蚀刻停止层来蚀刻第一蚀刻停止层。在一个实施例中，该方法还包括：在形成多个间隙填充层之前，减薄第一器件管芯和第二器件管芯。在一个实施例中，该方法还包括：在形成多个间隙填充层之前，平坦化第一器件管芯和第二器件管芯以露出第一器件管芯和第二器件管芯中的通孔。在一个实施例中，第一器件管芯、第二器件管芯、第三器件管芯和多个间隙填充层不含有机介电材料。在一个实施例中，该方法还包括在第一器件管芯和第二器件管芯上形成再分布线，其中再分布线电连接到通孔。
根据本发明的一些实施例，一种方法包括将多个器件管芯接合到器件晶圆；在多个器件管芯之间形成隔离区，其中形成隔离区包括：形成第一蚀刻停止层，第一蚀刻停止层具有与多个器件管芯接触的侧壁部分和与器件晶圆的顶面接触的底部；在第一蚀刻停止层上形成第一介电层；在第一介电层上形成第二蚀刻停止层；以及在第二蚀刻停止层上形成第二介电层；蚀刻隔离区以形成穿过隔离区的第一开口和第二开口，其中器件晶圆的接合焊盘暴露于第一开口和第二开口，并且在蚀刻隔离区期间，第二蚀刻停止层用于停止蚀刻；以及用导电材料填充第一开口和第二开口，以形成第一通孔和第二通孔。在一个实施例中，使用共形沉积方法形成第一蚀刻停止层、第一介电层和第二蚀刻停止层。在一个实施例中，使用化学气相沉积形成第一蚀刻停止层、第一介电层和第二蚀刻停止层。在一个实施例中，第一蚀刻停止层形成为比第二蚀刻停止层薄。在一个实施例中，将多个器件管芯接合到器件晶圆包括混合接合。在一个实施例中，该方法还包括蚀刻多个器件管芯以形成附加开口；以及填充附加开口以形成穿过多个器件管芯的半导体衬底的通孔，其中同时填充附加开口以及第一开口和第二开口。
根据本发明的一些实施例，一种封装件包括第一器件管芯；第二器件管芯和第三器件管芯，接合到第一器件管芯；隔离区，位于第二器件管芯和第三器件管芯之间，其中，隔离区包括：第一蚀刻停止层，具有与第一器件管芯和第二器件管芯接触的侧壁部分；以及与第一器件管芯的顶面接触的底部；第一介电层，位于第一蚀刻停止层上；第二蚀刻停止层，位于第一介电层上；以及第二介电层，位于第二蚀刻停止层上；以及通孔，穿过隔离区以电连接到第一器件管芯。在一个实施例中，通孔穿过隔离区中的所有介电层。在一个实施例中，通孔是锥形的，上部比相应的下部逐渐变宽。在一个实施例中，第一蚀刻停止层的厚度小于第二蚀刻停止层的厚度。在一个实施例中，第一蚀刻停止层、第一介电层和第二蚀刻停止层是共形层。
上面概述了若干实施例的特征，使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解，它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到，这种等同构造并且不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中它们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成封装件的方法，包括：
将第一器件管芯和第二器件管芯接合到第三器件管芯；
形成在所述第一器件管芯和所述第二器件管芯之间延伸的多个间隙填充层，所述第一器件管芯、所述第二器件管芯和所述多个间隙填充层并排设置在所述第三器件管芯上；
实施第一蚀刻工艺以蚀刻所述多个间隙填充层中的第一介电层以形成开口，其中，位于所述多个间隙填充层中并且位于所述第一介电层下面的第一蚀刻停止层用于停止所述第一蚀刻工艺；
使所述开口延伸穿过所述第一蚀刻停止层；
实施第二蚀刻工艺以使所述开口延伸穿过位于所述多个间隙填充层中并且位于所述第一蚀刻停止层下面的第二介电层，其中，所述多个间隙填充层中的第二蚀刻停止层与所述第三器件管芯直接接触，所述第二蚀刻工艺在所述第二蚀刻停止层上停止；
使所述开口延伸穿过所述第二蚀刻停止层以暴露所述第三器件管芯；以及
用导电材料填充所述开口以形成通孔。
2.根据权利要求1所述的方法，其中，所述第一器件管芯和所述第二器件管芯的接合包括混合接合。
3.根据权利要求1所述的方法，其中，所述第二蚀刻停止层包括氮化硅层。
4.根据权利要求1所述的方法，其中，所述第二蚀刻停止层、所述第二介电层和所述第一蚀刻停止层是共形介电层。
5.根据权利要求1所述的方法，其中，使所述开口延伸穿过所述第一蚀刻停止层包括使用所述第二介电层作为蚀刻停止层来蚀刻所述第一蚀刻停止层。
6.根据权利要求1所述的方法，还包括：在形成所述多个间隙填充层之前，减薄所述第一器件管芯和所述第二器件管芯。
7.根据权利要求1所述的方法，还包括：在形成所述多个间隙填充层之前，平坦化所述第一器件管芯和所述第二器件管芯以露出所述第一器件管芯和所述第二器件管芯中的通孔。
8.根据权利要求1所述的方法，其中，所述第一器件管芯、所述第二器件管芯、所述第三器件管芯和所述多个间隙填充层不含有机介电材料。
9.根据权利要求1所述的方法，还包括：
在所述第一器件管芯和所述第二器件管芯上形成再分布线，其中，所述再分布线电连接到所述通孔。
10.一种形成封装件的方法，包括：
将多个器件管芯接合到器件晶圆；
在所述多个器件管芯之间形成隔离区，其中，形成所述隔离区包括：
形成第一蚀刻停止层，所述第一蚀刻停止层具有与所述多个器件管芯接触的侧壁部分和与所述器件晶圆的顶面接触的底部；
在所述第一蚀刻停止层上形成第一介电层；
在所述第一介电层上形成第二蚀刻停止层；以及
在所述第二蚀刻停止层上形成第二介电层，所述多个器件管芯和包括所述第一蚀刻停止层、所述第一介电层、所述第二蚀刻停止层以及所述第二介电层的所述隔离区并排设置在所述器件晶圆上；
蚀刻所述隔离区以形成穿过所述隔离区的第一开口，其中，所述器件晶圆的接合焊盘暴露于所述第一开口，并且在蚀刻所述隔离区期间，所述第二蚀刻停止层用于停止蚀刻所述第二介电层；
使所述第一开口延伸穿过所述第一介电层和所述第一蚀刻停止层以暴露所述器件晶圆；以及
用导电材料填充所述第一开口以形成第一通孔和第二通孔。
11.根据权利要求10所述的方法，其中，使用共形沉积方法形成所述第一蚀刻停止层、所述第一介电层和所述第二蚀刻停止层。
12.根据权利要求10所述的方法，其中，使用化学气相沉积形成所述第一蚀刻停止层、所述第一介电层和所述第二蚀刻停止层。
13.根据权利要求10所述的方法，其中，所述第一介电层形成为比所述第二介电层薄，所述第一蚀刻停止层形成为比所述第二蚀刻停止层薄。
14.根据权利要求10所述的方法，其中，将所述多个器件管芯接合到所述器件晶圆包括混合接合。
15.根据权利要求10所述的方法，还包括：
蚀刻所述多个器件管芯以形成第二开口；以及
填充所述第二开口以形成穿过所述多个器件管芯的半导体衬底的通孔，其中，同时填充所述第一开口和所述第二开口。
16.一种封装件，包括：
第一器件管芯；
第二器件管芯和第三器件管芯，接合到所述第一器件管芯；
隔离区，位于所述第二器件管芯和所述第三器件管芯之间，其中，所述隔离区包括：
第一蚀刻停止层，具有与所述第三器件管芯和所述第二器件管芯接触的侧壁部分，以及与所述第一器件管芯的顶面接触的底部；
第一介电层，位于所述第一蚀刻停止层上；
第二蚀刻停止层，位于所述第一介电层上；以及
第二介电层，位于所述第二蚀刻停止层上，所述第二器件管芯、所述第三器件管芯和包括所述第一蚀刻停止层、所述第一介电层、所述第二蚀刻停止层以及所述第二介电层的所述隔离区并排设置在所述第一器件管芯上；以及
通孔，穿过所述隔离区以电连接到所述第一器件管芯。
17.根据权利要求16所述的封装件，其中，所述通孔穿过所述隔离区中的所有介电层。
18.根据权利要求16所述的封装件，其中，所述通孔是锥形的，上部比相应的下部逐渐变宽。
19.根据权利要求16所述的封装件，其中，所述第一蚀刻停止层的厚度小于所述第二蚀刻停止层的厚度。
20.根据权利要求16所述的封装件，其中，所述第一蚀刻停止层、所述第一介电层和所述第二蚀刻停止层是共形层。
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