CN109786348B - 形成具有凹槽的金属接合件 - Google Patents

形成具有凹槽的金属接合件 Download PDF

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CN109786348B
CN109786348B CN201810448078.8A CN201810448078A CN109786348B CN 109786348 B CN109786348 B CN 109786348B CN 201810448078 A CN201810448078 A CN 201810448078A CN 109786348 B CN109786348 B CN 109786348B
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metal pad
metal
dielectric layer
forming
diffusion barrier
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CN109786348A (zh
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陈明发
陈宪伟
叶松峯
邱文智
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

一种方法包括形成第一器件管芯，其中，该形成包括沉积第一介电层，以及在第一介电层中形成第一金属焊盘。第一金属焊盘包括凹槽。该方法还包括形成第二器件管芯，其中，第二器件管芯包括第二介电层和位于第二介电层中的第二金属焊盘。将第一器件管芯接合至第二器件管芯，其中，第一介电层接合至第二介电层，并且第一金属焊盘接合至第二金属焊盘。本发明的实施例还涉及形成具有凹槽的金属接合件。

Description

形成具有凹槽的金属接合件
技术领域
本发明的实施例涉及形成具有凹槽的金属接合件。
背景技术
集成电路的封装正在变得越来越复杂，在相同封装件中封装更多的器件管芯以实现更多的功能。例如，已经将集成芯片上系统(SoIC)开发成在相同的封装件中包括诸如处理器和存储器数据集的多个器件管芯。SoIC可以包括使用不同的技术形成的器件管芯并且具有接合至相同的器件管芯的不同功能，从而形成系统。这可以节省制造成本并优化器件性能。
发明内容
本发明的实施例提供了一种形成半导体器件的方法，包括：形成第一器件管芯，包括：沉积第一介电层；以及在所述第一介电层中形成第一金属焊盘，其中，所述第一金属焊盘包括与所述第一金属焊盘的边缘部分相邻的第一凹槽；形成第二器件管芯，包括：第二介电层；以及第二金属焊盘，位于所述第二介电层中；以及将所述第一器件管芯接合至所述第二器件管芯，其中，将所述第一介电层接合至所述第二介电层，并且将所述第一金属焊盘接合至所述第二金属焊盘。
本发明的另一实施例提供了一种形成半导体器件的方法，包括：在晶圆的顶面上形成介电层；蚀刻所述介电层以在所述介电层中形成沟槽；以及在所述沟槽中形成第一金属焊盘，其中，所述第一金属焊盘包括：扩散阻挡件，接触所述介电层；以及金属材料，位于所述扩散阻挡件的相对部分之间，其中，在所述第一金属焊盘的截面图中，所述金属材料的顶面包括中间部分和比所述中间部分更低的边缘部分，并且所述边缘部分低于所述扩散阻挡件的最近部分的顶部边缘以形成凹槽。
本发明的又一实施例提供了一种半导体器件，包括：第一器件管芯，包括：第一介电层；以及第一金属焊盘，包括：扩散阻挡件，接触所述第一介电层；以及金属材料，位于所述扩散阻挡件的相对部分之间，其中，在所述第一金属焊盘的截面图中，从所述扩散阻挡件的最近部分的顶部边缘凹进所述金属材料的边缘部分以形成气隙；以及第二器件管芯，包括：第二介电层，接合至所述第一介电层；以及第二金属焊盘，通过金属-金属直接接合而接合至所述第一金属焊盘。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳地理解本发明的各个方面。应该注意，根据工业中的标准实践，各个部件未按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增大或减小。
图1至图14是根据一些实施例的在封装件的制造中的中间阶段的截面图。
图15示出根据一些实施例的通过面-背接合形成的封装件的截面图。
图16A和图16B至图27示出根据一些实施例的金属接合件的截面图。
图28示出根据一些实施例的用于形成封装件的工艺流程。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件以直接接触的方式形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为了便于描述，在此可以使用诸如“在…下方”、“在…下面”、“下部”、“在…之上”、“上部”等空间相对术语以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，并且在此使用的空间相对描述符可以同样地作出相应的解释。
根据各个实施例提供了一种集成芯片上系统(SoIC)封装件及其形成方法。根据一些实施例示出形成SoIC封装件的中间阶段。讨论了一些实施例的一些变化。贯穿各个图和示例性实施例，相同的参考标号用于指定相同的元件。应当理解，尽管使用SoIC封装件的形成作为实例来解释本发明的实施例的概念，但是本发明的实施例可容易地应用于其他接合方法和其中金属焊盘和通孔彼此接合的结构。
图1至图14示出根据本发明的一些实施例的形成SoIC封装件的中间阶段的截面图。图1至图14中示出的步骤还在图28中所示的工艺流程200中示意性地示出。
图1示出形成的封装组件2的截面图。相应工艺在图28所示的工艺流程中示出为步骤202。根据本发明的一些实施例，封装组件2是包括诸如晶体管和/或二极管等的有源器件22以及诸如电容器、电感器、电阻器等的可能的无源器件的器件晶圆。封装组件2可以包括位于其中的多个芯片4，其中，示出一个芯片4。芯片4在下文中可选地称为(器件)管芯。根据本发明的一些实施例，器件管芯4为逻辑管芯，该管芯可以是中央处理单元(CPU)管芯、微控制单元(MCU)管芯、输入-输出(IO)管芯、基带(BB)管芯、应用处理器(AP)管芯等。器件管芯4也可以是诸如动态随机存取存储器(DRAM)管芯或静态随机存取存储器(SRAM)管芯等的存储器管芯。
根据本发明的可选实施例，封装组件2包括无源器件(不具有有源器件)。在后续的讨论中，将器件晶圆作为封装组件2进行讨论。本发明的实施例还可以应用于诸如内插器晶圆的其他类型的封装组件。
根据本发明的一些实施例，晶圆2包括半导体衬底20和形成在半导体衬底20的顶面处的部件。半导体衬底20可以由晶体硅、晶体锗、晶体硅锗和/或诸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等的Ⅲ-Ⅴ族化合物半导体形成。半导体衬底20还可以是块状硅衬底或绝缘体上硅(SOI)衬底。浅沟槽隔离(STI)区(未示出)可以形成在半导体衬底20中以隔离半导体衬底20中的有源区。尽管未示出，但贯通孔可以形成为延伸到半导体衬底20中，并且贯通孔用于电互连位于晶圆2的相对侧上的部件。
根据本发明的一些实施例，晶圆2包括形成在半导体衬底20的顶面上的集成电路器件22。示例性集成电路器件22可以包括互补金属氧化物半导体(CMOS)晶体管、电阻器、电容器、二极管等。在此未示出集成电路器件22的细节。根据可选实施例，晶圆2用于形成内插器，其中，衬底20可以是半导体衬底或介电衬底。
层间电介质(ILD)24形成在半导体衬底20上方并且填充集成电路器件22中的晶体管(未示出)的栅极堆叠件之间的间隔。根据一些实施例，ILD 24由磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、氟掺杂的硅酸盐玻璃(FSG)、正硅酸乙酯(TEOS)等形成。可使用旋涂、可流动化学汽相沉积(FCVD)、化学汽相沉积(CVD)、等离子体增强化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)等来形成ILD 24。
接触插塞28形成在ILD 24中，并且用于将集成电路器件22电连接至上面的金属线34和通孔36。根据本发明的一些实施例，接触插塞28由选自钨、铝、铜、钛、钽、氮化钛、氮化钽、它们的合金和/或它们的多层的导电材料形成。接触插塞28的形成可以包括在ILD 24中形成接触开口，将导电材料填充到接触开口中，并且实施平坦化(诸如化学机械抛光(CMP)工艺)以使接触插塞28的顶面与ILD 24的顶面齐平。
位于ILD 24和接触插塞28上方的是互连结构30。互连结构30包括介电层32以及形成在介电层32中的金属线34和通孔36。在下文中，介电层32可选地称为金属间介电(IMD)层32。根据本发明的一些实施例，至少介电层32中的下部介电层由具有低于约3.0或约2.5的介电常数(k值)的低k介电材料形成。介电层32可以由Black Diamond(应用材料公司的注册商标)、含碳低k介电材料、氢倍半硅氧烷(HSQ)、甲基倍半硅氧烷(MSQ)等形成。根据本发明的可选实施例，介电层32中的一些或全部由诸如氧化硅、碳化硅(SiC)、碳氮化硅(SiCN)、碳氮氧化硅(SiOCN)等非低k介电材料形成。根据本发明的一些实施例，介电层32的形成包括沉积含致孔剂的介电材料以及然后实施固化工艺以驱除致孔剂，并且因此剩余的IMD层32变成多孔的。在IMD层32之间形成可由碳化硅、氮化硅等形成的蚀刻停止层(未示出)，并且为了简明，未示出。
在介电层32中形成金属线34和通孔36。下文中将处于相同层级的金属线34统称为金属层。根据本发明的一些实施例，互连结构30包括通过通孔36互连的多个金属层。金属线34和通孔36可以由铜或铜合金形成，并且它们也可以由其他金属形成。形成工艺可以包括单镶嵌工艺和双镶嵌工艺。在单镶嵌工艺中，首先在介电层32的一个中形成沟槽，接着用导电材料填充沟槽。然后实施诸如CMP工艺的平坦化工艺以去除导电材料的比IMD层的顶面更高的多余部分，从而在沟槽中留下金属线。在双镶嵌工艺中，在IMD层中形成沟槽和通孔开口两者，其中，通孔开口位于沟槽下方并连接至沟槽。然后将导电材料填充到沟槽和通孔开口中以分别形成金属线和通孔。导电材料可以包括扩散阻挡件和位于扩散阻挡件上方的含铜金属材料。扩散阻挡件可以包括钛、氮化钛、钽、氮化钽等。
金属线34包括金属线34A，其有时称为顶部金属线。顶部金属线34A也统称为顶部金属层。相应的介电层32A可以由诸如未掺杂的硅酸盐玻璃(USG)、氧化硅、氮化硅等的非低k介电材料形成。介电层32A也可以由低k介电材料形成，其可以从下面的IMD层32的类似材料中选择。
根据本发明的一些实施例，在顶部金属层上方形成介电层38、40和42。介电层38和42可以由氧化硅、氮氧化硅、碳氧化硅等形成。介电层40由与介电层42的介电材料不同的介电材料形成。例如，介电层40可以由氮化硅、碳化硅等形成。
参考图2，形成通孔开口44和沟槽46。相应工艺在图28所示的工艺流程中示出为步骤204。为了形成通孔开口44和沟槽46，可以在介电层42上方形成光刻胶(未示出)和/或硬掩模(未示出)并将其图案化以帮助形成通孔开口44和沟槽46。根据本发明的一些实施例，实施各向异性蚀刻以形成沟槽46，并且该蚀刻停止在蚀刻停止层40上。然后实施另一各向异性蚀刻以通过蚀刻暴露的蚀刻停止层40和下面的介电层38的部分来形成通孔开口44。根据本发明的一些实施例，不形成蚀刻停止层40，并且在单个介电层中形成通孔开口44和沟槽46。可以使用时间模式实施蚀刻以允许在单个介电层的顶面和底面之间的中间层级处停止蚀刻(用于形成沟槽46)。
图3示出填充导电材料。相应工艺在图28所示的工艺流程中示出为步骤206。首先形成导电扩散阻挡件48。根据本发明的一些实施例，扩散阻挡件48由钛、氮化钛、钽、氮化钽等形成。例如，可以使用原子层沉积(ALD)、物理汽相沉积(PVD)等来形成扩散阻挡件48。扩散阻挡件48包括位于表面介电层42上方的第一部分以及位于沟槽46和通孔开口44的底部和侧壁上的第二部分。
接下来，例如通过电化学镀(ECP)沉积金属材料50。金属材料50填充沟槽46和通孔开口44的剩余部分。金属材料50还包括位于表面介电层42的顶面上方的一些部分。金属材料50可以包括铜或铜合金，或可以在后续的退火工艺中扩散的另一金属材料，从而使得可以形成金属至金属的直接接合。
接下来，如图4所示，实施诸如化学机械抛光(CMP)工艺的平坦化工艺以去除金属材料50和扩散阻挡件48的多余部分，直到暴露介电层42。相应工艺在图28所示的工艺流程中示出为步骤208。扩散阻挡件48和金属材料50的剩余部分包括通孔52和金属焊盘54(包括54A和54B)。图4示出用于接合的金属焊盘。应当理解，金属线也可以与金属焊盘54同时形成。金属焊盘54包括用于接合至器件管芯的金属焊盘54A和用于贯通孔接合的金属焊盘54B。
图16A示出根据本发明的一些实施例的通孔52和金属焊盘54的截面图。金属焊盘54和通孔52的每个包括扩散阻挡件48的部分和由扩散阻挡件48的相应部分环绕的金属材料50的部分。金属材料50可以包括边缘部分和位于边缘部分之间的中间部分。中间部分的顶面50A1高于边缘部分的顶面50A2。根据本发明的一些实施例，金属材料50的顶面50A包括弯曲部分。中间部分的顶面50A1可以是弯曲的或可以是平坦的。边缘部分的顶面50A2可以是连续弯曲的(圆的)。顶面50A的最高点与最低点之间的高度差ΔH可以在约
Figure BDA0001657739690000071
和约
Figure BDA0001657739690000072
之间的范围内，并且可以在约
Figure BDA0001657739690000073
和约
Figure BDA0001657739690000074
之间的范围内。
根据本发明的一些实施例，扩散阻挡件48具有顶部边缘48A，该顶部边缘48A齐平于、稍高于或稍低于金属材料50的顶面50A的最高点，这取决于CMP工艺。边缘表面部分50A2可以低于顶部边缘48A，从而形成凹槽56。根据一些实施例，凹槽深度D1大于约
Figure BDA0001657739690000075
并且可以在约
Figure BDA0001657739690000076
和约
Figure BDA0001657739690000077
之间的范围内，并且可以进一步在约
Figure BDA0001657739690000078
和约
Figure BDA0001657739690000079
之间的范围内。扩散阻挡件48的顶部边缘48A也可以齐平于或稍低于介电层42的顶面。在金属焊盘54的顶视图中，凹槽56可以在金属焊盘54的边缘附近形成环。暴露于凹槽56的扩散阻挡件48的侧壁也可以形成环。
为了实现凹槽56，调整CMP工艺。根据本发明的一些实施例，用于CMP工艺的浆料包括草酸(H2C2O4)和乙酸(CH3COOH)。可以将浆料的pH值调整为低于约4.0，并且可以在约2.0和约4.0之间的范围内，这可以通过将草酸和乙酸的浓度调整到合适的量来实现。根据一些实施例，浆料中草酸的重量百分比在约0.01％和约2％之间的范围内，并且浆料中乙酸的重量百分比在约0.1％和约2％之间的范围内。W草酸/W乙酸的比率可以在约1：1和约1:10之间的范围内，其中，W草酸表示浆料中草酸的重量百分比，以及W乙酸表示浆料中乙酸的重量百分比。此外，浆料可以包括诸如草酸铜螯合物(Cu-C2O4)的草酸螯合物。根据一些实施例，草酸螯合物的重量百分比可以在约0.01％和约0.1％之间的范围内。利用这些工艺条件，可以形成如图16A所示的凹槽56。浆料还可以包括诸如氧化硅颗粒、氧化铝颗粒等的研磨剂。另外，可以调整诸如CMP期间晶圆的温度、晶圆和抛光垫的旋转速度、浆料中的研磨剂等的工艺条件以形成凹槽56。
根据本发明的可选实施例，形成如图16B所示的金属焊盘54和通孔52。金属材料50、扩散阻挡件48和介电层42的顶面是平坦的或大致平坦的(例如，具有小于约
Figure BDA00016577396900000710
的高度差)。根据本发明的一些实施例，用于实现这种轮廓的浆料可以不含乙酸、草酸和草酸螯合物。根据一些实施例，浆料的pH值也在约7.0和约10.0之间的范围内。浆料还可以包括诸如氧化硅颗粒、氧化铝颗粒等的研磨剂。
根据一些实施例器件，器件管芯4还可以包括形成在介电层38(图4)中的诸如铝焊盘或铝铜焊盘的金属焊盘。为了简明，未示出铝焊盘。
根据本发明的一些实施例，在晶圆2中没有诸如聚合物层的有机介电材料。有机介电层通常具有可以为10ppm/℃或更高的高的热膨胀系数(CTE)。这显著大于硅衬底(诸如衬底20)的CTE(约为3ppm/℃)。因此，有机介电层倾向于引起晶圆2的翘曲。晶圆2中不包括有机材料有利地减小晶圆2中的层之间的CTE失配，并且导致翘曲的减少。而且，在晶圆2中不包括有机材料使得可以形成细间距金属线(诸如图11中的72)和高密度接合焊盘，并且导致布线能力的改善。
应当理解，形成在相同的层中并且与金属焊盘54同时形成的金属线可以具有与图16A、图16B、图17A和图17B所示的相应金属焊盘类似的截面图形状。而且，在先前讨论的实施例中，使用双镶嵌工艺来形成金属焊盘54。根据本发明的可选实施例，使用单镶嵌工艺形成金属焊盘54。
图5示出形成晶圆100，晶圆100包括位于其中的器件管芯112。根据本发明的一些实施例，器件管芯112是可为CPU管芯、MCU管芯、IO管芯、基带管芯或AP管芯的逻辑管芯。器件管芯112还可以是存储器管芯。晶圆100包括可以是硅衬底的半导体衬底114。硅贯通孔(TSV)116(有时称为半导体贯通孔或贯通孔)形成为穿透半导体衬底。TSV 116用于将形成在半导体衬底114的前侧(图示的底侧)上的器件和金属线连接至背侧。而且，器件管芯112包括用于连接至器件管芯112中的有源器件和无源器件的互连结构130。互连结构130包括金属线和通孔(未示出)。
器件管芯112可以包括介电层138和142以及位于介电层138和142之间的蚀刻停止层140。在层138、140和142中形成接合焊盘154和通孔152。相应工艺在图28所示的工艺流程中示出为步骤210。根据本发明的一些实施例，诸如管芯112的所有器件管芯均不含诸如聚合物的有机介电材料。介电层138和142、接合焊盘154和通孔152的材料和形成方法可以类似于器件管芯4中的它们的相应部分，并且因此在此不重复细节。
图17A和图17B示出根据一些实施例的接合焊盘154和通孔152。接合焊盘154和通孔152包括扩散阻挡件148和金属材料150。图17A的结构、材料和形成方法可以类似于图16A所示的接合焊盘54和通孔52的结构、材料和形成方法。扩散阻挡件148和金属材料150以及介电层142的顶面/边缘轮廓也可分别类似于图16A中用于扩散阻挡件48、金属材料50和介电层42所示和所讨论的，并且因此在此不再重复。形成凹槽156，并且凹槽156的细节可以与用于凹槽56(图16A)所示和所讨论的大致相同。如果从接合焊盘154的底部观察，凹槽156可以在接合焊盘154的边缘附近形成环，并且扩散阻挡件148的一些侧壁也暴露于凹槽156，并且可以形成环。图17A中所示的结构的形成工艺(包括CMP工艺)可以类似于参考图16A所讨论的。
图17B的结构、材料和形成方法可以分别类似于图16B所示的接合焊盘54和通孔52的结构、材料和形成方法。扩散阻挡件148和金属材料150以及介电层142的顶面/边缘轮廓可分别类似于图16B中用于扩散阻挡件48、金属材料50和介电层42所示和所讨论的，并且因此在此不再重复。在金属材料150中不形成凹槽。
再次参考图5，将晶圆100分割成多个分立的器件管芯112。图6示出器件管芯112(包括112A和112B)与器件管芯4的接合。相应工艺在图28所示的工艺流程中示出为步骤212。器件管芯112A和112B的每个可以形成为具有图5所示的结构(并且使用与所讨论的类似的形成方法)。
器件管芯112A和112B可以彼此相同或者可以彼此不同。例如，器件管芯112A和112B可以是从以上列出的类型中选择的不同类型的管芯。此外，可以使用诸如45nm技术、28nm技术、20nm技术等的不同的技术形成器件管芯112。而且，器件管芯112中的一个可以是数字电路管芯，而另一个可以是模拟电路管芯。管芯4、112A和112B组合起来用作系统。将系统的功能和电路拆分成诸如管芯4、112A和112B的不同管芯可以优化这些管芯的形成，并且可以导致制造成本的降低。
管芯4、112A和112B中的至少一个具有带有如图16A和图17A所示的凹槽56/156的接合焊盘。根据一些实施例，管芯4的接合焊盘54具有凹槽56(图16A)，并且每个器件管芯112A和112B的接合焊盘可以具有图17A所示的结构或图17B所示的结构。根据本发明的可选实施例，管芯4的接合焊盘54具有图16B所示的结构(没有凹槽)，并且器件管芯112A和112B中的一个或两个的接合焊盘154具有如图17A所示的凹槽。在图18至图25中，所示的实施例在接合焊盘54和154中均具有凹槽，并且应当理解，接合焊盘54和154两者中的任一个可以没有凹槽。
可以通过混合接合来实现器件管芯112与管芯4(图6)的接合。例如，通过金属-金属直接接合将接合焊盘154接合至接合焊盘54A。根据本发明的一些实施例，金属-金属直接接合是铜-铜直接接合。接合焊盘154的尺寸可以大于、等于或小于相应接合焊盘54A的尺寸。此外，介电层142通过电介质-电介质接合而接合至表面介电层42，电介质-电介质接合可以是例如生成Si-O-Si键的熔融接合。在相邻的器件管芯112之间留下间隙53。
为了实现混合接合，首先通过将器件管芯112轻压在管芯4上而将器件管芯112预先接合至介电层42和接合焊盘54A。在预先接合所有器件管芯112之后，实施退火以引起接合焊盘54A和相应的上面的接合焊盘154中的金属的相互扩散。根据一些实施例，退火温度可以高于约350℃，并且可以在约350℃和约550℃之间的范围内。根据一些实施例，退火时间可以在约1.5小时和约3.0小时之间的范围内，并且可以在约1.0小时和约2.5小时之间的范围内。通过混合接合，接合焊盘154通过由金属相互扩散引起的直接金属接合而接合至相应的接合焊盘54A。
图18示出预先接合之后和退火之前接合焊盘54和154的截面图。根据一些实施例，接合焊盘54和154具有相同的宽度，并且垂直对准。因此，凹槽56合并至相应的凹槽156。由于所示的凹槽56可以是第一凹槽环的部分，并且所示的凹槽156可以是第二凹槽环的部分，所以第一凹槽环和第二凹槽环可以彼此合并以形成组合的凹槽环。根据可选实施例，接合焊盘54和154中的一个不具有凹槽(如图16B和图17B所示)，并且另一接合焊盘具有凹槽。
图19示出退火之后的接合焊盘54和154的截面图。由于接合焊盘54和154的相互扩散，金属材料50与金属材料150合并。凹槽56和156的形成有利地减少了在接合结构中产生的应力。例如，金属材料50和150的热膨胀系数(CTE)显著不同于介电层42和142的热膨胀系数(CTE)，并且在热循环(诸如预先退火和退火)期间凹槽允许一些空间以用于金属材料的膨胀。因此减小接合结构所受到的应力。
退火之后，接合结构中可能存在一些凹槽56’。由于金属材料的扩散，凹槽56’的形状和尺寸可以不同于凹槽56和156的形状和尺寸。例如，凹槽56’的尺寸可以小于退火之前的凹槽56和156的组合尺寸。凹槽56’的高度可以大于约
Figure BDA0001657739690000111
并且可以在约
Figure BDA0001657739690000112
和约
Figure BDA0001657739690000113
之间的范围内。根据可选实施例，在退火之后，凹槽消失。也可以改变扩散阻挡件48和148的形状以适应凹槽的减小和消除。
图20示出根据一些实施例的预先接合之后且在退火之前的接合焊盘54和154的截面图，其中，接合焊盘54与接合焊盘154垂直未对准。因此，凹槽56与相应的凹槽156未对准。图21示出退火之后的接合焊盘54和154的截面图。由于接合焊盘54和154的相互扩散，金属材料50与金属材料150合并。在截面图中，可以完全地填充或利用减小的尺寸部分地填充面向另一金属焊盘的中间部分的凹槽56和156。可以保留面对相对的介电层42和142的凹槽。应当理解，图19和图21所示的实施例可以存在于相同的封装件上。例如，当发生旋转未对准时，一些接合焊盘对准以产生图19中所示的结构，并且相同封装件中的一些其他接合焊盘可能彼此未对准以产生图21所示的结构。
图22和图23分别示出在退火之前和之后的接合焊盘，其中，接合焊盘54和154对准。接合焊盘54的尺寸不同于(大于或小于)接合焊盘154的尺寸。例如，在所示实例中，接合焊盘154大于接合焊盘54。结果，如图23所示，在接合之后，减小或完全填充凹槽56(图22)的尺寸，而未完全填充凹槽156。
图24和图25分别示出在退火之前和之后的接合焊盘，其中，接合焊盘54和154未对准。接合焊盘54的尺寸不同于(大于或小于)接合焊盘154的尺寸。例如，在所示实例中，接合焊盘154大于接合焊盘54。如图25所示，在接合之后，凹槽56和156(图24)均具有一些填充的部分和一些未填充的其他部分。
返回参考图6，根据一些实施例，在接合工艺之后，可以实施背侧研磨以将器件管芯112削薄至例如，厚度在约15μm和约30μm之间。图6示意性地示出虚线112-BS1，虚线112-BS1是背侧研磨之前的器件管芯112的背面。112-BS2是背侧研磨之后的器件管芯112的背面。通过削薄器件管芯112，减小间隙53的高宽比以实施间隙填充。否则，由于间隙53的高的高宽比，间隙填充可能是困难的。在背侧研磨之后，可以露出TSV 116。可选地，此时不露出TSV 116，并且当存在覆盖TSV 116的衬底的薄层时停止背侧研磨。根据这些实施例，可以在图8所示的步骤中露出TSV 116。根据其中间隙53的高宽比不太高的其他实施例，跳过背侧研磨。
图7示出形成间隙填充层，其中，该间隙填充层包括介电层62和下面的蚀刻停止层60。相应工艺在图28所示的工艺流程中示出为步骤214。蚀刻停止层60由介电材料形成，该介电材料对器件管芯112的侧壁以及介电层42和接合焊盘54B的顶面具有良好的粘附性。根据本发明的一些实施例，蚀刻停止层60由诸如氮化硅的含氮化物材料形成。例如，蚀刻停止层60可以是共形层，例如，其中，水平部分的厚度T1A和垂直部分的厚度T1B彼此大致相等，例如，差值(T1A-T1B)的绝对值小于厚度T1A和T1B两者的约20％或小于约10％。沉积可以包括诸如原子层沉积(ALD)或化学汽相沉积(CVD)的共形沉积方法。当接合焊盘54B具有凹槽56时(图16A)，蚀刻停止层60也延伸到凹槽中。
介电层62由与蚀刻停止层60的材料不同的材料形成。根据本发明的一些实施例，介电层62由氧化硅形成，由TEOS形成，然而还可以使用诸如碳化硅、氮氧化硅、碳氮氧化硅、PSG、BSG、BPSG等的其他介电材料。可以使用CVD、高密度等离子体化学汽相沉积(HDPCVD)、可流动CVD、旋涂等形成介电层62。介电层62完全填充剩余的间隙53(图6)。
参考图8，实施诸如CMP工艺或机械研磨工艺的平坦化工艺以去除间隙填充层60和62的多余部分，从而使得暴露器件管芯112。相应工艺还在图28所示的工艺流程中示出为步骤214。而且，暴露贯通孔116。层60和62的剩余部分统称为(间隙填充)隔离区64。
图9示出蚀刻介电层62以形成开口66。相应工艺在图28所示的工艺流程中示出为步骤216。根据本发明的一些实施例，形成并图案化光刻胶(未示出)，并且使用图案化的光刻胶作为蚀刻掩模来蚀刻介电层62。因此形成开口66，并且开口66向下延伸至蚀刻停止层60，蚀刻停止层60充当蚀刻停止层。根据本发明的一些实施例，介电层62包括氧化物，并且可以通过干蚀刻来实施该蚀刻。蚀刻气体可以包括NF3和NH3的混合物，或HF和NH3的混合物。接下来，对蚀刻停止层60进行蚀刻，从而使得开口66向下延伸至介电接合焊盘54B。根据本发明的一些实施例，蚀刻停止层60由氮化硅形成，并且使用干蚀刻来实施蚀刻。蚀刻气体可以包括CF4、O2和N2的混合物、NF3和O2的混合物、SF6、或SF6和O2的混合物。
图10示出形成填充开口66(图9)并且连接至接合焊盘54B的贯通孔70。相应工艺在图28所示的工艺流程中示出为步骤218。根据本发明的一些实施例，贯通孔70的形成包括实施诸如电化学镀工艺或化学镀工艺的镀工艺。贯通孔70可以包括诸如钨、铝、铜等的金属材料。也可以在金属材料下面形成导电阻挡层(诸如钛、氮化钛、钽、氮化钽等)。实施诸如CMP的平坦化以去除镀的金属材料的多余部分，并且金属材料的剩余部分形成贯通孔70。贯通孔70可以具有大致直的且垂直的侧壁。而且，贯通孔70可以具有锥形轮廓，其顶部宽度略大于相应的底部宽度。
根据可选实施例，不在器件管芯112中预先形成TSV 116。相反，它们在形成隔离区64之后形成。例如，在形成开口66(图8)之前或之后，蚀刻器件管芯112以形成额外的开口(由所示的TSV 116占据)。可以同时填充器件管芯112中的额外的开口和开口66以形成TSV116和贯通孔70。所得到的TSV116可以具有比相应的下部更宽的上部，与图10中所示的相反。
参考图11，形成再分布线(RDL)72和介电层74。相应工艺在图28所示的工艺流程中示出为步骤220。根据本发明的一些实施例，介电层74由诸如氧化硅的氧化物、诸如氮化硅的氮化物等形成。可以使用镶嵌工艺来形成RDL 72，其中，该镶嵌工艺包括蚀刻介电层74以形成开口，将导电阻挡层沉积到开口中，镀诸如铜或铜合金的金属材料，并且实施平坦化以去除金属材料的多余部分。
图12示出形成钝化层、金属焊盘和上面的介电层。相应工艺还在图28所示的工艺流程中示出为步骤220。在介电层74上方形成钝化层76(有时称为钝化-1)，并且在钝化层76中形成通孔78以电连接至RDL 72。金属焊盘80形成在钝化层76上方，并且通过通孔78电连接到至RDL 72。金属焊盘80可以是铝焊盘或铝铜焊盘，并且可以使用其他金属材料。
还如图12所示，在钝化层76上方形成钝化层82(有时称为钝化-2)。钝化层76和82的每个可以是单层或复合层，并且可以由无孔材料形成。根据本发明的一些实施例，钝化层76和82中的一个或两个是包括氧化硅层(未单独示出)和位于氧化硅层上方的氮化硅层(未单独示出)的复合层。钝化层76和82也可以由诸如未掺杂的硅酸盐玻璃(USG)、氮氧化硅等的其他无孔的介电材料形成。
接下来，图案化钝化层82，从而使得钝化层82的一些部分覆盖金属焊盘80的边缘部分，并且通过钝化层82中的开口暴露金属焊盘80的一些部分。然后形成聚合物层84，并且然后进行图案化以暴露金属焊盘80。聚合物层84可以由聚酰亚胺、聚苯并恶唑(PBO)形成。
根据本发明的一些实施例，金属焊盘80下方的结构不含有机材料(诸如聚合物层)，从而使得用于形成位于金属焊盘80下方的结构的工艺可以采用用于形成器件管芯的工艺，并且具有小的间距和线宽的细间距RDL(诸如72)是可能的。
参考图13，形成后钝化互连件(PPI)86，其中，该形成可以包括形成金属晶种层并且在金属晶种层上方形成图案化的掩模层(未示出)，并且在图案化的掩模层中镀PPI 86。然后在蚀刻工艺中去除图案化的掩模层和金属晶种层的与图案化的掩模层重叠的部分。然后形成聚合物层88，其中，聚合物层88可以由PBO、聚酰亚胺等形成。
参考图14，形成凸块下金属(UBM)90，并且UBM 90延伸到聚合物层88中以连接至PPI 86。相应工艺还在图28所示的工艺流程中示出为步骤220。根据本发明的一些实施例，UBM 90中的每个包括阻挡层(未示出)和位于阻挡层上方的晶种层(未示出)。阻挡层可以是钛层、氮化钛层、钽层、氮化钽层或由钛合金或钽合金形成的层。晶种层的材料可以包括铜或铜合金。诸如银、金、铝、钯、镍、镍合金、钨合金、铬、铬合金及它们的组合的其他金属也可以包括在UBM 90中。
还如图14所示，形成电连接件92。相应工艺还在图28所示的工艺流程中示出为步骤220。用于形成UBM 90和电连接件92的形成工艺包括沉积毯式UBM层，形成并图案化掩模(其可以是光刻胶，未示出)，其中，通过掩模中的开口暴露毯式UBM层的部分。在形成UBM 90之后，将所示的封装件放置在镀溶液(未示出)中，并且实施镀步骤以在UBM 90上形成电连接件92。根据本发明的一些实施例，电连接件92包括在后续回流工艺中不熔化的非焊料部分(未示出)。非焊料部分可以由铜形成，并且因此在下文中称为铜凸块，尽管它们可以由其他非焊料材料形成。电连接件92的每个还可以包括从镍层、镍合金、钯层、金层、银层或它们的多层中选择的覆盖层(未示出)。在铜凸块上方形成覆盖层。电连接件92还可以包括焊料帽，其中，焊料帽可以由Sn-Ag合金、Sn-Cu合金、Sn-Ag-Cu合金等形成，并且可以是无铅的或含铅的。在前面的步骤中形成的结构称为复合晶圆94。对复合晶圆94实施管芯切锯(分割)步骤以将复合晶圆94分离成多个封装件96。相应工艺在图28所示的工艺流程中示出为步骤222。
图14中所示的封装件具有面-面的结构，其中，器件管芯112的正面面向器件管芯4的正面。图15示出面-背结构，其中，器件管芯112的正面面向器件管芯4的背面。器件管芯4包括延伸穿过衬底20和介电层17的TSV 16。图15中的虚线区19表示诸如焊料区的可能的电连接件。根据本发明的一些实施例，对TSV 16和介电层17实施CMP。如图25所示，CMP工艺的细节可以类似于参考图16A所讨论的，并且因此形成凹槽156。
图26和图27示出接合焊盘154与TSV 16的接合，图26示出退火之前的结构，而图27示出退火之后的结构。图26中的层49可以是由氧化硅、氮化硅等形成的介电隔离层。可以在TSV 16中形成凹槽56，在退火之后减小或完全消除该凹槽。在退火之后，仍然存在凹槽156。
本发明的实施例具有一些优势特征。通过在接合焊盘中形成凹槽，减小了接合结构中的应力，特别是在热循环中。因此，改善了接合结构的可靠性。
根据本发明的一些实施例，一种方法包括形成第一器件管芯，包括：沉积第一介电层；以及在所述第一介电层中形成第一金属焊盘，其中，第一金属焊盘包括与第一金属焊盘的边缘部分相邻的第一凹槽；形成第二器件管芯，第二器件管芯包括第二介电层以及位于第二介电层中的第二金属焊盘；以及将第一器件管芯接合至第二器件管芯，其中，将第一介电层接合至第二介电层，并且将第一金属焊盘接合至第二金属焊盘。在实施例中，第一金属焊盘包括：扩散阻挡件；以及位于扩散阻挡件的相对部分之间的含铜材料，其中，凹进含铜材料的边缘部分以低于扩散阻挡件的顶部边缘以形成第一凹槽。在实施例中，该接合包括：实施预先退火；并且实施退火，其中，在退火期间，减小第一凹槽。在实施例中，形成第一金属焊盘包括实施平坦化，其中，通过平坦化产生第一凹槽。在实施例中，平坦化包括使用pH值低于约4.0的浆料实施的化学机械抛光(CMP)。在实施例中，使用包括乙酸和铜螯合物的浆料实施CMP。在实施例中，第二金属焊盘包括与第二金属焊盘的边缘相邻的第二凹槽，并且在开始接合时，第一凹槽合并第二凹槽。在实施例中，第二金属焊盘包括与第二金属焊盘的边缘相邻的第二凹槽，并且在开始接合时，第一凹槽与第二凹槽分离，并且在接合之后，保留第一凹槽，并且第二凹槽消失。
根据本发明的一些实施例，一种方法包括：在晶圆的顶面上形成介电层；蚀刻介电层以在介电层中形成沟槽；以及在沟槽中形成第一金属焊盘，其中，第一金属焊盘包括：与介电层接触的扩散阻挡件；以及位于扩散阻挡件的相对部分之间的金属材料，其中，在第一金属焊盘的截面图中，金属材料的顶面包括中间部分和比中间部分低的边缘部分，并且边缘部分低于扩散阻挡件的最近部分的顶部边缘以形成凹槽。在实施例中，该方法还包括将第二金属焊盘接合至第一金属焊盘，其中，至少减小该凹槽的尺寸。在实施例中，该方法还包括形成延伸到凹槽中的介电蚀刻停止层；以及形成穿透介电蚀刻停止层以连接至第一金属焊盘的贯通孔。在实施例中，形成第一金属焊盘包括CMP，并且在CMP期间形成凹槽。在实施例中，使用浆料实施CMP，并且浆料具有在约2.0和约4.0之间的范围内的pH值。在实施例中，金属材料的顶面是弯曲的。
根据本发明的一些实施例，一种器件包括第一器件管芯和第二器件管芯，其中，第一器件管芯包括：第一介电层；以及第一金属焊盘，第一金属焊盘包括：与第一介电层接触的扩散阻挡件；以及位于扩散阻挡件的相对部分之间的金属材料，其中，在第一金属焊盘的截面图中，凹进金属材料的边缘部分以低于扩散阻挡件的最近部分的顶部边缘以形成气隙；其中，第二器件管芯包括：第二介电层，通过熔融接合而接合至第一介电层；以及通过金属-金属直接接合而接合至第一金属焊盘的第二金属焊盘。在实施例中，气隙进一步延伸到第二金属焊盘中。在实施例中，气隙形成在扩散阻挡件的侧壁、金属材料的表面和第二金属焊盘的表面之间。在实施例中，气隙形成在扩散阻挡件的侧壁、金属材料的表面和第二介电层的表面之间。在实施例中，面向气隙的金属材料的表面是圆形的。在实施例中，第一器件管芯还包括第三金属焊盘，该第三金属焊盘包括额外的凹槽，并且该器件还包括延伸到额外的凹槽中的介电蚀刻停止层；位于介电蚀刻停止层上方并与其接触的介电层；以及穿透介电蚀刻停止层和介电层以连接至第三金属焊盘的贯通孔。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的各方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与在此所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，在此他们可以做出多种变化、替换以及改变。

Claims (20)

1.一种形成半导体器件的方法，包括：
形成第一器件管芯，包括：
沉积第一介电层；以及
在所述第一介电层中形成第一金属焊盘和第三金属焊盘，其中，所述第一金属焊盘和所述第三金属焊盘分别包括与所述第一金属焊盘的边缘部分相邻的第一凹槽和与所述第三金属焊盘的边缘部分相邻的第三凹槽；
形成第二器件管芯，包括：
第二介电层；以及
第二金属焊盘，位于所述第二介电层中；以及
将所述第一器件管芯接合至所述第二器件管芯，其中，将所述第一介电层接合至所述第二介电层，并且将所述第一金属焊盘接合至所述第二金属焊盘，
所述方法，还包括：
形成延伸到所述第三金属焊盘的所述第三凹槽中的介电蚀刻停止层；以及
形成穿透所述介电蚀刻停止层以连接至所述第三金属焊盘的贯通孔，所述贯通孔与所述第三凹槽在同一侧。
2.根据权利要求1所述的方法，其中，所述第一金属焊盘包括：
扩散阻挡件；以及
含铜材料，位于所述扩散阻挡件的相对部分之间，其中，凹进所述含铜材料的边缘部分以低于所述扩散阻挡件的顶部边缘以形成所述第一凹槽。
3.根据权利要求1所述的方法，其中，所述接合包括：
实施预先退火；以及
实施退火，其中，在所述退火期间，减小所述第一凹槽。
4.根据权利要求1所述的方法，其中，形成所述第一金属焊盘包括实施平坦化，其中，通过所述平坦化产生所述第一凹槽。
5.根据权利要求4所述的方法，其中，所述平坦化包括使用pH值低于4.0的浆料实施化学机械抛光(CMP)。
6.根据权利要求4所述的方法，其中，所述平坦化包括使用包括乙酸和铜螯合物的浆料实施化学机械抛光(CMP)。
7.根据权利要求1所述的方法，其中，所述第二金属焊盘包括与所述第二金属焊盘的边缘相邻的第二凹槽，并且在开始接合时，所述第一凹槽合并所述第二凹槽。
8.根据权利要求1所述的方法，其中，所述第二金属焊盘包括与所述第二金属焊盘的边缘相邻的第二凹槽，并且在开始所述接合时，所述第一凹槽与所述第二凹槽分离，并且在所述接合之后，保留所述第一凹槽，同时所述第二凹槽消失。
9.一种形成半导体器件的方法，包括：
在晶圆的顶面上形成介电层；
蚀刻所述介电层以在所述介电层中形成第一沟槽和第二沟槽；以及
在所述第一沟槽和所述第二沟槽中分别形成第一金属焊盘和第二金属焊盘，其中，所述第一金属焊盘和所述第二金属焊盘中的每个包括：
扩散阻挡件，接触所述介电层；以及
金属材料，位于所述扩散阻挡件的相对部分之间，其中，在所述第一金属焊盘的截面图中，所述金属材料的顶面包括中间部分和比所述中间部分更低的边缘部分，并且所述边缘部分低于所述扩散阻挡件的最近部分的顶部边缘以形成凹槽，
所述方法，还包括：
形成延伸到所述第二金属焊盘的所述凹槽中的介电蚀刻停止层；以及
形成穿透所述介电蚀刻停止层以连接至所述第二金属焊盘的贯通孔，所述贯通孔与所述凹槽在同一侧。
10.根据权利要求9所述的方法，还包括将第三金属焊盘接合至所述第一金属焊盘，其中，在将所述第三金属焊盘接合至所述第一金属焊盘之后，至少减小所述第一金属焊盘的所述凹槽的尺寸。
11.根据权利要求10所述的方法，其中，所述第一金属焊盘与所述第三金属焊盘通过实施退火接合。
12.根据权利要求9所述的方法，其中，形成所述第一金属焊盘包括化学机械抛光(CMP)，并且在所述化学机械抛光期间形成所述第一金属焊盘的所述凹槽。
13.根据权利要求12所述的方法，其中，使用浆料实施所述化学机械抛光，并且所述浆料具有在2.0和4.0之间的范围内的pH值。
14.根据权利要求9所述的方法，其中，所述金属材料的顶面是弯曲的。
15.一种半导体器件，包括：
第一器件管芯，包括：
第一介电层；以及
第一金属焊盘，包括：
扩散阻挡件，接触所述第一介电层；以及
金属材料，位于所述扩散阻挡件的相对部分之间，
其中，在所述第一金属焊盘的截面图中，从所述扩散阻挡件的最近部分的顶部边缘凹进所述金属材料的边缘部分以形成气隙；以及
第三金属焊盘，其中所述第一金属焊盘与所述第三金属焊盘的顶面共平面，其中，所述第三金属焊盘包括附加扩散阻挡件和附加金属材料，其中，所述附加金属材料的附加边缘部分从所述附加扩散阻挡件的顶部附加边缘凹进以形成附加凹槽；
第二器件管芯，包括：
第二介电层，接合至所述第一介电层；以及
第二金属焊盘，通过金属-金属直接接合而接合至所述第一金属焊盘，
介电蚀刻停止层，延伸到所述第三金属焊盘的所述附加凹槽中；以及
贯通孔，穿透所述介电蚀刻停止层以连接至所述第三金属焊盘，所述贯通孔与所述附加凹槽在同一侧。
16.根据权利要求15所述的半导体器件，其中，
所述气隙进一步延伸到所述第二金属焊盘中。
17.根据权利要求15所述的半导体器件，其中，所述气隙形成在所述扩散阻挡件的侧壁、所述金属材料的表面和所述第二金属焊盘的表面之间。
18.根据权利要求15所述的半导体器件，其中，所述气隙形成在所述扩散阻挡件的侧壁、所述金属材料的表面和所述第二介电层的表面之间。
19.根据权利要求15所述的半导体器件，其中，所述金属材料的面向所述气隙的表面是圆形的。
20.根据权利要求15所述的半导体器件，其中，所述器件还包括：
介电层，位于所述介电蚀刻停止层上方并与所述介电蚀刻停止层接触；以及
所述贯通孔，穿透所述介电蚀刻停止层和所述介电层以连接至所述第三金属焊盘。
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Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9793243B2 (en) * 2014-08-13 2017-10-17 Taiwan Semiconductor Manufacturing Company, Ltd. Buffer layer(s) on a stacked structure having a via
JP2016219660A (ja) * 2015-05-22 2016-12-22 ソニー株式会社 半導体装置、製造方法、固体撮像素子、および電子機器
CN112164688B (zh) * 2017-07-21 2023-06-13 联华电子股份有限公司 芯片堆叠结构及管芯堆叠结构的制造方法
DE102018124695A1 (de) * 2017-11-15 2019-05-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrieren von Passivvorrichtungen in Package-Strukturen
US11296044B2 (en) * 2018-08-29 2022-04-05 Invensas Bonding Technologies, Inc. Bond enhancement structure in microelectronics for trapping contaminants during direct-bonding processes
EP3667745B1 (en) * 2018-12-10 2023-03-22 IMEC vzw Method for obtaining light emitting diodes reconstituted over a carrier substrate
US11049844B2 (en) * 2019-07-01 2021-06-29 International Business Machines Corporation Semiconductor wafer having trenches with varied dimensions for multi-chip modules
US11211348B2 (en) * 2019-08-22 2021-12-28 Wuhan Xinxin Semiconductor Manufacturing Co., Ltd. First wafer, fabricating method thereof and wafer stack
KR20210025156A (ko) 2019-08-26 2021-03-09 삼성전자주식회사 반도체 장치 및 그 제조방법
US11264343B2 (en) * 2019-08-30 2022-03-01 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad structure for semiconductor device and method of forming same
US11114360B1 (en) * 2019-09-24 2021-09-07 Xilinx, Inc. Multi-die device structures and methods
US11251100B2 (en) * 2019-09-25 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure having an anti-arcing pattern disposed on a passivation layer and method of fabricating the semiconductor structure
US11211371B2 (en) 2019-10-18 2021-12-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
DE102020114141B4 (de) 2019-10-18 2024-03-28 Taiwan Semiconductor Manufacturing Co., Ltd. Integriertes schaltungspackage und verfahren
US11387222B2 (en) 2019-10-18 2022-07-12 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit package and method
TWI735353B (zh) * 2019-10-18 2021-08-01 台灣積體電路製造股份有限公司 積體電路封裝及其製作方法
TWI707441B (zh) * 2020-02-27 2020-10-11 力成科技股份有限公司 扇出型封裝之重佈線層結構及其製法
DE102020128855A1 (de) * 2020-05-21 2021-11-25 Taiwan Semiconductor Manufacturing Co., Ltd. Chiplets-3d-soic-systemintegrations- und herstellungsverfahren
US11462495B2 (en) 2020-05-21 2022-10-04 Taiwan Semiconductor Manufacturing Co., Ltd. Chiplets 3D SoIC system integration and fabrication methods
KR20210151569A (ko) 2020-06-05 2021-12-14 삼성전자주식회사 반도체 장치 및 이를 포함하는 반도체 패키지
TWI778406B (zh) * 2020-08-26 2022-09-21 矽品精密工業股份有限公司 電子封裝件及其製法
US20220189839A1 (en) * 2020-12-15 2022-06-16 Intel Corporation Inter-component material in microelectronic assemblies having direct bonding
US11728312B2 (en) * 2021-01-22 2023-08-15 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor packaging and methods of forming same
US11894241B2 (en) * 2021-01-28 2024-02-06 Taiwan Semiconductor Manufacturing Co., Ltd. Heterogeneous bonding structure and method forming same
US11830806B2 (en) * 2021-04-29 2023-11-28 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and method of manufacturing the same
US11735616B2 (en) * 2021-12-29 2023-08-22 Nanya Technology Corporation Optical semiconductor device with integrated dies

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101261984A (zh) * 2007-03-08 2008-09-10 育霈科技股份有限公司 半导体组件封装结构及其方法
CN104051288A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 用于混合晶圆接合的方法
CN104900543A (zh) * 2014-03-06 2015-09-09 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法
CN104916605A (zh) * 2014-03-12 2015-09-16 台湾积体电路制造股份有限公司 具有锥形端通孔的封装件

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07112041B2 (ja) 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
US6063306A (en) * 1998-06-26 2000-05-16 Cabot Corporation Chemical mechanical polishing slurry useful for copper/tantalum substrate
ATE452422T1 (de) * 2002-09-25 2010-01-15 Seimi Chem Kk Poliermittelzusammensetzung und polierverfahren
US20050090104A1 (en) * 2003-10-27 2005-04-28 Kai Yang Slurry compositions for chemical mechanical polishing of copper and barrier films
JP2007305667A (ja) * 2006-05-09 2007-11-22 Toshiba Corp 半導体装置及びその製造方法
US7750488B2 (en) * 2006-07-10 2010-07-06 Tezzaron Semiconductor, Inc. Method for bonding wafers to produce stacked integrated circuits
JP2011000948A (ja) 2009-06-18 2011-01-06 Nishikawa Rubber Co Ltd ガラスランの型成形部
JP5187284B2 (ja) * 2009-06-26 2013-04-24 ソニー株式会社 半導体装置の製造方法
US8482132B2 (en) * 2009-10-08 2013-07-09 International Business Machines Corporation Pad bonding employing a self-aligned plated liner for adhesion enhancement
US8508954B2 (en) * 2009-12-17 2013-08-13 Samsung Electronics Co., Ltd. Systems employing a stacked semiconductor package
US9142533B2 (en) * 2010-05-20 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate interconnections having different sizes
US8901736B2 (en) * 2010-05-28 2014-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. Strength of micro-bump joints
JP5682327B2 (ja) * 2011-01-25 2015-03-11 ソニー株式会社 固体撮像素子、固体撮像素子の製造方法、及び電子機器
US8779588B2 (en) * 2011-11-29 2014-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structures for multi-chip packaging
US8698308B2 (en) * 2012-01-31 2014-04-15 Taiwan Semiconductor Manufacturing Company, Ltd. Bump structural designs to minimize package defects
US9153565B2 (en) * 2012-06-01 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Image sensors with a high fill-factor
FR2993400A1 (fr) * 2012-07-12 2014-01-17 St Microelectronics Crolles 2 Structure integree tridimensionnelle apte a detecter une elevation de temperature
US9299630B2 (en) 2012-07-30 2016-03-29 General Electric Company Diffusion barrier for surface mount modules
US20140175614A1 (en) * 2012-12-20 2014-06-26 Industrial Technology Research Institute Wafer stacking structure and method of manufacturing the same
US9443796B2 (en) * 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US9437572B2 (en) * 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
JP2016018879A (ja) * 2014-07-08 2016-02-01 株式会社東芝 半導体装置および半導体装置の製造方法
JP2016219660A (ja) * 2015-05-22 2016-12-22 ソニー株式会社 半導体装置、製造方法、固体撮像素子、および電子機器
US9881884B2 (en) 2015-08-14 2018-01-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure and method for forming the same
KR102423813B1 (ko) * 2015-11-27 2022-07-22 삼성전자주식회사 반도체 소자
US9691733B1 (en) * 2016-07-28 2017-06-27 United Microelectronics Corp. Bonded semiconductor structure and method for forming the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101261984A (zh) * 2007-03-08 2008-09-10 育霈科技股份有限公司 半导体组件封装结构及其方法
CN104051288A (zh) * 2013-03-15 2014-09-17 台湾积体电路制造股份有限公司 用于混合晶圆接合的方法
CN104900543A (zh) * 2014-03-06 2015-09-09 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制备方法
CN104916605A (zh) * 2014-03-12 2015-09-16 台湾积体电路制造股份有限公司 具有锥形端通孔的封装件

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