TWI658521B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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Publication number
TWI658521B
TWI658521B TW107109351A TW107109351A TWI658521B TW I658521 B TWI658521 B TW I658521B TW 107109351 A TW107109351 A TW 107109351A TW 107109351 A TW107109351 A TW 107109351A TW I658521 B TWI658521 B TW I658521B
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Taiwan
Prior art keywords
metal pad
dielectric layer
metal
layer
dielectric
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TW107109351A
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English (en)
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TW201923918A (zh
Inventor
陳明發
Ming-Fa Chen
陳憲偉
Hsien-Wei Chen
葉松峯
Sung-Feng Yeh
邱文智
Wen-Chih Chiou
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台灣積體電路製造股份有限公司
Taiwan Semiconductor Manufacturing Co., Ltd.
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Application filed by 台灣積體電路製造股份有限公司, Taiwan Semiconductor Manufacturing Co., Ltd. filed Critical 台灣積體電路製造股份有限公司
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Publication of TW201923918A publication Critical patent/TW201923918A/zh

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Abstract

一種半導體裝置的形成方法，所述方法包含形成第一裝 置晶粒，此包含沈積第一介電層，以及在第一介電層中形成第一金屬墊。第一金屬墊包含凹陷。所述方法更包含形成第二裝置晶粒，所述第二裝置晶粒包含第二介電層以及在第二介電層中的第二金屬墊。將第一裝置晶粒接合至第二裝置晶粒，其中將第一介電層接合至第二介電層，且將第一金屬墊接合至第二金屬墊。

Description

半導體裝置及其形成方法
本發明的實施例是有關於一種半導體裝置及其形成方法。
積體電路的封裝已變得愈發複雜，其中較多裝置晶粒被封裝在同一封裝中以達成較多功能。舉例而言，系統整合晶片(System on Integrate Chip，SoIC)已被開發成在同一封裝中包含諸如處理器以及記憶體塊的多個裝置晶粒。SoIC可包含使用不同技術形成的裝置晶粒，且可具有不同功能接合至同一裝置晶粒，從而因此形成系統。此可節省製造成本並最佳化裝置效能。
本發明的一實施例提供一種半導體裝置的形成方法，包括形成第一裝置晶粒，包括沈積第一介電層；以及在所述第一介電層中形成第一金屬墊，其中所述第一金屬墊包括鄰近於所述第一金屬墊的邊緣部分的第一凹陷；形成第二裝置晶粒，所述第二裝置晶粒包括第二介電層；以及第二金屬墊，其在所述第二介電 層中；以及將所述第一裝置晶粒接合至所述第二裝置晶粒，其中將所述第一介電層接合至所述第二介電層，且將所述第一金屬墊接合至所述第二金屬墊。
本發明的一實施例提供一種半導體裝置的形成方法，包括在晶圓的頂部表面上形成介電層；蝕刻所述介電層以在所述介電層中形成溝渠；以及在所述溝渠中形成第一金屬墊，其中所述第一金屬墊包括擴散障壁，其接觸所述介電層；以及金屬材料，其在所述擴散障壁的相對部分之間，其中在所述第一金屬墊的橫截面圖中，所述金屬材料的頂部表面包括中間部分，以及低於所述中間部分的邊緣部分，且所述邊緣部分低於所述擴散障壁的最近部分的頂部邊緣以形成凹陷。
本發明的一實施例提供一種半導體裝置，包括第一裝置晶粒，所述第一裝置晶粒包括第一介電層；以及第一金屬墊，所述第一金屬墊包括擴散障壁，其接觸所述第一介電層；以及金屬材料，其在所述擴散障壁的相對部分之間，其中在所述第一金屬墊的橫截面圖中，所述金屬材料的邊緣部分自所述擴散障壁的最近部分的頂部邊緣凹陷以形成氣隙；以及第二裝置晶粒，所述第二裝置晶粒包括第二介電層，其接合至所述第一介電層；以及第二金屬墊，其藉由金屬至金屬直接接合而接合至所述第一金屬墊。
2‧‧‧封裝組件/裝置晶圓
4、112、112A、112B‧‧‧晶片/裝置晶粒
16、116‧‧‧直通矽晶穿孔(TSV)
17、32、32A、38、42、74、138、142‧‧‧介電層/金屬間介電(IMD)層
19‧‧‧虛線區
20、114‧‧‧半導體基底
22‧‧‧主動裝置/積體電路裝置
24‧‧‧層間介電質(ILD)
28‧‧‧接觸插塞
30、130‧‧‧內連線結構
34‧‧‧上覆金屬線
34A‧‧‧頂部金屬線
36、52、152‧‧‧通孔
40、140‧‧‧介電層/蝕刻終止層
44‧‧‧通孔開口
46‧‧‧溝渠
48、148‧‧‧擴散障壁
48A‧‧‧頂部邊緣
49‧‧‧層
50、150‧‧‧金屬材料
50A‧‧‧金屬材料的頂部表面
50A1‧‧‧中間部分的頂部表面
50A2‧‧‧邊緣部分的頂部表面/邊緣表面部分
53‧‧‧間隙
54、54A、54B、80、154‧‧‧金屬墊/接合墊
56、56'、156‧‧‧凹陷
60‧‧‧蝕刻終止層/間隙填充層
62‧‧‧介電層/間隙填充層
64‧‧‧隔離區
66‧‧‧開口
70‧‧‧穿孔
72‧‧‧重佈線(RDL)
76、82‧‧‧鈍化層
78‧‧‧通孔
84、88‧‧‧聚合物層
86‧‧‧後鈍化內連線(PPI)
90‧‧‧凸塊下金屬(UBM)
92‧‧‧電連接件
94‧‧‧複合晶圓
96‧‧‧封裝
100‧‧‧晶圓
112-BS1、112-BS2‧‧‧虛線
200‧‧‧製程流程
202、204、206、208、210、212、214、216、218、220、222‧‧‧ 步驟
D1‧‧‧凹陷深度
T1A、T1B‧‧‧厚度
△H‧‧‧高度差
結合附圖閱讀以下詳細說明，能最佳地理解本揭露的各個態樣。應注意，根據行業中的標準慣例，各種特徵未按比例繪製。 實際上，為論述清楚起見，可任意地增大或減小各種特徵的尺寸。
圖1至圖14為根據一些實施例的封裝的中間製造階段的橫截面圖。
圖15示出根據一些實施例的藉由面對背接合形成的封裝的橫截面圖。
圖16A以及圖16B至圖27示出根據一些實施例的金屬接合件的橫截面圖。
圖28示出用於形成根據一些實施例的封裝的製程流程。
以下揭露內容提供用於實施本發明的不同特徵的不同實施例或實例。下文描述組件以及配置的特定實例以簡化本揭露。當然，此等組件以及配置僅僅為實例且並不意欲為限制性的。舉例而言，在以下描述中，第一特徵形成在第二特徵上方或上可包含第一特徵與第二特徵直接接觸地形成的實施例，且還可包含額外特徵可在第一特徵與第二特徵之間形成，使得第一特徵與第二特徵可能並不直接接觸的實施例。另外，本揭露可在各種實例中重複參考標號及/或字母。此重複是出於簡化以及清楚的目的，且本身並不指示所論述的各種實施例及/或組態之間的關係。
此外，為便於描述，諸如「在……之下」、「下方」、「下部」、「上覆」、「上部」等的空間相對術語可在本文中用於描述一個元件或特徵與另一元件或特徵的關係，如圖式中所說明。除了圖式中所描繪的定向之外，空間相對術語亦意欲涵蓋裝置在使用或操作中的不同定向。設備可以其他方式定向(旋轉90度或處於 其他定向)，且本文中所使用的空間相對描述詞同樣可各別地被理解。
根據各種實施例提供系統整合晶片(SoIC)封裝以及形成所述封裝的方法。根據一些實施例說明SoIC封裝的中間形成階段。論述一些實施例的一些變化。在各種視圖以及說明性實施例內，相似參考標號用於指定相似元件。應瞭解，儘管將SoIC封裝的形成用作實例來解釋本揭露實施例的概念，但本揭露的實施例易於適用於金屬墊與通孔彼此接合的其他接合方法以及結構。
圖1至圖14說明根據本揭露的一些實施例的SoIC封裝的中間形成階段的橫截面圖。圖1至圖14中所示的步驟亦在圖28中所示的製程流程200中示意性地加以反映。
圖1說明封裝組件2在形成時的橫截面圖。所對應的製程在圖28中所示的製程流程中說明為步驟202。根據本揭露的一些實施例，封裝組件2為包含諸如電晶體及/或二極體的主動裝置22，且可能包含諸如電容器、電感器、電阻器等的被動裝置的裝置晶圓。封裝組件2中可包含多個晶片4，其中示出晶片4中的一者。晶片4在下文中被替代地稱作(裝置)晶粒。根據本揭露的一些實施例，裝置晶粒4為邏輯晶粒，其可為中央處理單元(Central Processing Unit，CPU)晶粒、微控制單元(Micro Control Unit，MCU)晶粒、輸入輸出(input-output，IO)晶粒、基頻(BaseBand，BB)晶粒、應用程式處理器(Application processor，AP)晶粒等。裝置晶粒4亦可為記憶體晶粒，諸如動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)晶粒或靜態隨機存取記憶體(Static Random Access Memory，SRAM)晶粒。
根據本揭露的替代實施例，封裝組件2包含被動裝置(無主動裝置)。在後續論述中，裝置晶圓被論述為封裝組件2。本揭露的實施例亦可應用於諸如中介晶圓(interposer wafer)的其他類型的封裝組件。
根據本揭露的一些實施例，晶圓2包含半導體基底20，以及形成於半導體基底20的頂部表面處的特徵。半導體基底20可由結晶矽、結晶鍺、結晶矽鍺及/或III-V化合物半導體形成，所述III-V化合物半導體諸如GaAsP、AlInAs、AlGaAs、GaInAs、GaInP、GaInAsP等。半導體基底20亦可為塊狀矽基底或絕緣層上矽(Silicon-On-Insulator，SOI)基底。淺溝渠隔離(Shallow Trench Isolation，STI)區(未示出)可形成於半導體基底20中，以隔離半導體基底20中的主動區。儘管未示出，但穿孔可形成為延伸至半導體基底20中，且穿孔用於將晶圓2的相對側上的特徵相互電耦合。
根據本揭露的一些實施例，晶圓2包含積體電路裝置22，其形成於半導體基底20的頂部表面上。例示性積體電路裝置22可包含互補金屬氧化物半導體(Complementary Metal-Oxide Semiconductor，CMOS)電晶體、電阻器、電容器、二極體等。本文中並不說明積體電路裝置22的細節。根據替代實施例，晶圓2用於形成中介，其中基底20可為半導體基底或介電基底。
層間介電質(Inter-Layer Dielectric，ILD)24形成於半導體基底20上方，並填充積體電路裝置22中的電晶體(未示出)的閘極堆疊之間的空間。根據一些實施例，層間介電質24由磷矽酸鹽玻璃(Phospho Silicate Glass，PSG)、硼矽酸鹽玻璃(Boro Silicate Glass，BSG)、硼摻雜磷矽酸鹽玻璃(Boron-doped Phospho Silicate Glass，BPSG)、氟摻雜矽酸鹽玻璃(Fluorine-doped Silicate Glass，FSG)、原矽酸四乙酯(Tetra Ethyl Ortho Silicate，TEOS)等形成。可使用旋轉塗佈(spin coating)、流動式化學氣相沈積(Flowable Chemical Vapor Deposition，FCVD)、化學氣相沈積(Chemical Vapor Deposition，CVD)、電漿增強式化學氣相沈積(Plasma Enhanced Chemical Vapor Deposition，PECVD)、低壓化學氣相沈積(Low Pressure Chemical Vapor Deposition，LPCVD)等來形成層間介電質24。
接觸插塞28形成於層間介電質24中，且用於將積體電路裝置22電連接至上覆金屬線34以及通孔36。根據本揭露的一些實施例，接觸插塞28由選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金及/或多層的導電材料形成。接觸插塞28的形成可包含在層間介電質24中形成接觸開口、將導電材料填充至接觸開口中，以及執行平坦化(諸如化學機械研磨(Chemical Mechanical Polish，CMP)製程)，以使接觸插塞28的頂部表面與層間介電質24的頂部表面齊平。
在層間介電質24以及接觸插塞28上方設有內連線結構30。內連線結構30包含介電層32，以及形成於介電層32中的金屬線34與通孔36。介電層32在下文中被替代地稱作金屬間介電(Inter-Metal Dielectric，IMD)層32。根據本揭露的一些實施例，介電層32至少較下部的介電層由具有低於約3.0或約2.5介電常數(k值)的低k介電材料形成。介電層32可由黑鑽(Black Diamond，應用材料的註冊商標)、含碳低k介電材料、聚矽氧烷(Hydrogen SilsesQuioxane，HSQ)、甲基矽倍半氧烷(MethylSilsesQuioxane，MSQ)等形成。根據本揭露的替代實施例，介電層32中的一些或全部由非低k介電材料形成，所述材料諸如氧化矽、碳化矽(SiC)、碳氮化矽(SiCN)、碳氧氮化矽(SiOCN)等。根據本揭露的一些實施例，介電層32的形成包含沈積含致孔劑的介電材料，並接著執行固化製程以移除致孔劑，且因此剩餘介電層32變得多孔。可由碳化矽、氮化矽等形成的蝕刻終止層(未示出)形成於IMD層32之間，且為簡單起見並未示出。
金屬線34以及通孔36形成於介電層32中。處在同一層級處的金屬線34在下文中被統稱為金屬層。根據本揭露的一些實施例，內連線結構30包含藉由通孔36互連的多個金屬層。金屬線34以及通孔36可由銅或銅合金形成，且其亦可由其他金屬形成。形成製程可包含單鑲嵌製程以及雙鑲嵌製程。在單鑲嵌製程中，首先在介電層32中的一者中形成溝渠，繼而用導電材料填充溝渠。接著執行諸如化學機械研磨製程的平坦化製程，以移除導電材料的高於IMD層的頂部表面的多餘部分，從而在溝渠中留下金屬線。在雙鑲嵌製程中，在IMD層中形成溝渠以及通孔開口兩者，其中通孔開口在溝渠之下且連接至溝渠。接著將導電材料填充至溝渠以及通孔開口中，以分別形成金屬線以及通孔。導電材料可包含擴散障壁以及在擴散障壁上方的含銅金屬材料。擴散障壁可包含鈦、氮化鈦、鉭、氮化鉭等。
金屬線34包含金屬線34A，其有時被稱作頂部金屬線。頂部金屬線34A亦被統稱為頂部金屬層。各別介電層32A可由諸如未摻雜矽酸鹽玻璃(Un-doped Silicate Glass，USG)、氧化矽、氮化 矽等的非低k介電材料形成。介電層32A亦可由低k介電材料形成，所述介電材料可選自底層IMD層32的類似材料。
根據本揭露的一些實施例，介電層38、40以及42形成於頂部金屬層上方。介電層38以及42可由氧化矽、氮氧化矽、氧碳化矽等形成，介電層40由不同於介電層42的介電材料的介電材料形成。舉例而言，介電層42可由氮化矽、碳化矽等形成。
參考圖2，形成通孔開口44以及溝渠46。所對應的製程在圖28中所示的製程流程中說明為步驟204。為形成通孔開口44以及溝渠46，可形成光阻(未示出)及/或硬式罩幕(hard mask)(未示出)並將其圖案化在介電層42上方，以形成通孔開口44以及溝渠46。根據本揭露的一些實施例，執行非等向性蝕刻(anisotropic etch)以形成溝渠46，以及蝕刻終止層40上的蝕刻終止(etch stop)。接著執行另一非等向性蝕刻，以藉由蝕刻曝露出的蝕刻終止層40以及介電層38的底層部分來形成通孔開口44。根據本揭露的一些實施例，並未形成蝕刻終止層40，且通孔開口44以及溝渠46形成於單個介電層中。可使用時間模式來執行蝕刻，以允許所述蝕刻(用於形成溝渠46)在所述單個介電層的頂部表面與底部表面之間的中間層級處終止。
圖3說明填充導電材料。所對應的製程在圖28中所示的製程流程中說明為步驟206。首先形成導電擴散障壁48。根據本揭露的一些實施例，擴散障壁48由鈦、氮化鈦、鉭、氮化鉭等形成。可使用例如原子層沈積(Atomic Layer Deposition，ALD)、物理氣相沈積(Physical Vapor Deposition，PVD)等來形成擴散障壁48。擴散障壁48包括在表面介電層42上方的第一部分，以及在溝渠46 與通孔開口44的底部以及側壁上的第二部分。
接下來，例如藉由電化學電鍍(Electro-Chemical Plating，ECP)來沈積金屬材料50。金屬材料50填充溝渠46以及通孔開口44的剩餘部分。金屬材料50更包含在表面介電層42的頂部表面上方的一些部分。金屬材料50可包含銅或銅合金，或可在後續退火製程中擴散的另一金屬材料，從而使得可形成金屬至金屬(metal-to-metal)直接接合。
接下來，如圖4中所示，執行諸如化學機械研磨(CMP)製程的平坦化製程，以移除金屬材料50以及擴散障壁48的多餘部分，直至曝露出介電層42為止。所對應的製程在圖28中所示的製程流程中說明為步驟208。擴散障壁48以及金屬材料50的剩餘部分包含通孔52以及金屬墊54(包含54A以及54B)。圖4說明用於接合的金屬墊。應瞭解，金屬線亦可同時形成為金屬墊54。金屬墊54包含用於接合至裝置晶粒的金屬墊54A，以及用於穿孔焊接的金屬墊54B。
圖16A說明根據本揭露的一些實施例的通孔52以及金屬墊54的橫截面圖。金屬墊54以及通孔52中的每一者包含擴散障壁48的一部分，以及由擴散障壁48的各別部分環繞的金屬材料50的一部分。金屬材料50可包含邊緣部分以及在邊緣部分之間的中間部分。中間部分的頂部表面50A1高於邊緣部分的頂部表面50A2。根據本揭露的一些實施例，金屬材料50的頂部表面50A包含彎曲部分。中間部分的頂部表面50A1可為彎曲的或可為平坦的。邊緣部分的頂部表面50A2可為連續彎曲的(曲面)。頂部表面50A的最高點與最低點之間的高度差△H可在約100Å與約500Å之間的範圍 內，且可在約100Å與約200Å之間的範圍內。
根據本揭露的一些實施例，擴散障壁48具有頂部邊緣48A，所述頂部邊緣與金屬材料50的頂部表面50A的最高點可齊平、略微高於所述最高點或略微低於所述最高點，其取決於化學機械研磨製程。邊緣表面部分50A2可低於頂部邊緣48A，從而使得形成凹陷56。根據一些實施例，凹陷深度D1大於約100Å，且可在約100Å與約500Å之間的範圍內，且可進一步在約100Å與約200Å之間的範圍內。擴散障壁48的頂部邊緣48A亦可與介電層42的頂部表面齊平或略微低於所述頂部表面。在接合墊54的俯視圖中，凹陷56可形成接近接合墊54的邊緣的環。擴散障壁48的曝露於凹陷56的側壁亦可形成環。
為達成凹陷56，調整化學機械研磨製程。根據本揭露的一些實施例，用於化學機械研磨製程的漿料包含草酸(H2C2O4)以及乙酸(CH3COOH)。將漿料的pH值調整為低於約4.0，且可在約2.0與約4.0之間的範圍內，可藉由將草酸以及乙酸的濃度調整至適當量來達成所述範圍。根據一些實施例，漿料中的草酸的重量百分比在約0.01%百分比與約2%百分比之間的範圍內，且漿料中的乙酸的重量百分比在約0.1%百分比與約2%百分比之間的範圍內。WOxalic/Wacetic的比率可在約1：1與約1：10之間的範圍內，其中WOxalic表示漿料中的草酸的重量百分比，且Wacetic表示漿料中的乙酸的重量百分比。此外，漿料可包含諸如Cu-草酸螯合物(Cu-C2O4)的草酸螯合物。根據一些實施例，草酸螯合物的重量百分比可在約0.01%與約0.1%之間的範圍內。在此等製程條件下，可形成如圖16A中所示的凹陷56。漿料亦可包含諸如氧化矽粒子、氧化鋁粒子 等的磨料。另外，可調整諸如晶圓在化學機械研磨期間的溫度、晶圓以及研磨墊的旋轉速度、漿料中的磨料等的製程條件來形成凹陷56。
根據本揭露的替代實施例，形成如圖16B中所示的金屬墊54以及通孔52。金屬材料50、擴散障壁48以及介電層42的頂部表面是平坦的或實質上上平坦的(例如，高度差小於約20Å)。根據本揭露的一些實施例，用於達成此輪廓的漿料可不含乙酸、草酸以及草酸螯合物。根據一些實施例，漿料的pH值亦在約7.0與約10.0之間的範圍內。漿料亦可包含諸如氧化矽粒子、氧化鋁粒子等的磨料。
裝置晶粒4亦可包含諸如鋁或鋁銅墊的金屬墊，根據一些實施例所述金屬墊可形成於介電層38(圖4)中。為簡單起見，並未示出鋁墊。
根據本揭露的一些實施例，晶圓2中不存在諸如聚合物層的有機介電材料。有機介電層通常具有高熱膨脹係數(Coefficient of Thermal Expansion，CTE)，其可為10ppm/C°或更高。此明顯大於矽基底(諸如基底20)的熱膨脹係數，矽基底的熱膨脹係數約為3ppm/C°。因此，有機介電層往往會導致晶圓2發生翹曲。不在晶圓2中包含有機材料能有利地減小晶圓2中的層之間的熱膨脹係數失配，並減少翹曲。並且，不在晶圓2中包含有機材料使得能夠形成細小間距金屬線(諸如圖10中的72)以及高密度接合墊，並改良佈線能力。
應瞭解，與金屬墊54形成於同一層中且同時形成的金屬線可具有與如圖16A、圖16B、圖17A以及圖17B中所示的各別金屬 墊類似的橫截面圖形狀。並且，在先前所論述實施例中，使用雙鑲嵌製程來形成金屬墊54。根據本揭露的替代實施例，金屬墊54藉由使用單鑲嵌製程來形成。
圖5說明形成晶圓100，所述晶圓中包含裝置晶粒112。根據本揭露的一些實施例，裝置晶粒112為邏輯晶粒，其可為中央處理單元晶粒、微控制單元晶粒、輸入輸出晶粒、基頻晶粒或應用程式處理器晶粒。裝置晶粒112亦可為記憶體晶粒。晶圓100包含半導體基底114，其可為矽基底。有時被稱作直通半導體穿孔或穿孔的直通矽晶穿孔(Through-Silicon Via，TSV)116形成為穿過半導體基底。直通矽晶穿孔116用於將形成於半導體基底114的前側(所示底側)上的裝置以及金屬線連接至背側。並且，裝置晶粒112包含用於連接至裝置晶粒112中的主動裝置以及被動裝置的內連線結構130。內連線結構130包含金屬線以及通孔(未示出)。
裝置晶粒112可包含介電層138以及142，以及在介電層138與142之間的蝕刻終止層140。接合墊154以及通孔152形成於層138、140以及142中。所對應的製程在圖28中所示的製程流程中說明為步驟210。根據本揭露的一些實施例，諸如晶粒112的所有裝置晶粒皆不含諸如聚合物的有機介電材料。介電層138以及142、接合墊154以及通孔152的材料以及形成方法可類似於裝置晶粒4中的對應部分，且因此本文中不再重複所述細節。
圖17A以及圖17B說明根據一些實施例的接合墊154以及通孔152。接合墊154以及通孔152包含擴散障壁148以及金屬材料150。圖17A的結構、材料以及形成方法可類似於如圖16A中所示的接合墊54以及通孔52的結構、材料以及形成方法。擴散障壁148 以及金屬材料150以及介電層142的頂部表面/邊緣輪廓亦可分別類似於圖16A中針對擴散障壁48、金屬材料50以及介電層42所示出並論述的頂部表面/邊緣輪廓，因此本文中不再重複。形成了凹陷156，且凹陷156的細節可實質上與針對凹陷56(圖16A)所示出並論述的細節相同。若自接合墊154的底部檢視，則凹陷156可形成接近接合墊154的邊緣的環，且擴散障壁148的一些側壁亦曝露於凹陷156且可形成環。圖17A中所示結構的形成製程(包含CMP製程)可類似於參考圖16A所論述的形成製程。
圖17B的結構、材料以及形成方法分別類似於如圖16B中所示的接合墊54以及通孔52。擴散障壁148以及金屬材料150以及介電層142的頂部表面/邊緣輪廓可分別類似於圖16B中針對擴散障壁48、金屬材料50以及介電層42所示出並論述的頂部表面/邊緣輪廓，且因此本文中不再重複。金屬材料150中未形成凹陷。
返回參考圖5，晶圓100被單體化成多個離散裝置晶粒112。圖6示除將裝置晶粒112(包含112A以及112B)接合至裝置晶粒4。所對應的製程在圖28中所示的製程流程中說明為步驟212。裝置晶粒112A以及112B中的每一者可形成為具有如圖5的結構(且使用如所論述的類似形成方法)。
裝置晶粒112A以及112B可彼此相同或可彼此不同。舉例而言，裝置晶粒112A以及112B可為選自上文所列類型的不同類型的晶粒。此外，可使用諸如45奈米(nanometer，nm)技術、28nm技術、20nm技術等的不同技術來形成裝置晶粒112。並且，裝置晶粒112中的一者可為數位電路晶粒，而另一者可為類比電路晶粒。晶粒4、112A以及112B的組合能充當系統。將系統的功能以及 電路分裂成諸如晶粒4、112A以及112B的不同晶粒可最佳化此等晶粒的形成，且可減少製造成本。
晶粒4、112A以及112B中的至少一者具有具如圖16A以及圖17A中所示的凹陷56/156的接合墊。根據一些實施例，晶粒4的接合墊54具有凹陷56(圖16A)，且裝置晶粒112A以及112B中的每一者的接合墊可具有圖17A中所示的結構或圖17B中所示的結構。根據本揭露的替代實施例，晶粒4的接合墊54具有圖16B中所示的結構(無凹陷)，且裝置晶粒112A以及112B中的一者或兩者的接合墊154具有如圖17A中所示的凹陷。在圖18至圖25中，如所示出的實施例在接合墊54以及154兩者中皆具有凹陷，且應瞭解，接合墊54以及154兩者中的任一者亦可不含凹陷。
可藉由混合式接合來達成裝置晶粒112至晶粒4的接合(圖6)。舉例而言，藉由金屬至金屬直接接合將接合墊154接合至接合墊54A。根據本揭露的一些實施例，金屬至金屬直接接合為銅至銅直接接合。接合墊154的大小可大於、等於或小於各別接合墊54A的大小。此外，藉由介電質至介電質接合將介電層142接合至表面介電層42，所述接合可為融合接合，例如生成了Si-O-Si接合件。間隙53保留在相鄰裝置晶粒112之間。
為達成混合式接合，首先藉由抵著晶粒4輕微按壓裝置晶粒112來將裝置晶粒112預接合至介電層42以及接合墊54A。在預接合所有裝置晶粒112之後，執行退火以使得接合墊54A以及對應上覆接合墊154中的金屬發生相互擴散(inter-diffusion)。根據一些實施例，退火溫度可高於約350℃，且可在約350℃與約550℃之間的範圍內。根據一些實施例，退火時間可在約1.5小時與約3.0小時 之間的範圍內，且可在約1.0小時與約2.5小時之間的範圍內。藉由混合式接合，能藉由由金屬相互擴散所引起的直接金屬接合將接合墊154接合至對應接合墊54A。
圖18示出接合墊54以及154在預接合之後且在退火之前的橫截面圖。根據一些實施例，接合墊54以及154具有相同寬度，且豎直對準。因此，凹陷56結合至各別凹陷156。由於所說明凹陷56可為第一凹陷環的部分，且所說明凹陷156可為第二凹陷環的部分，因此第一以及第二凹陷環可彼此結合以形成組合凹陷環。根據替代實施例，接合墊54以及154中的一者並不具有凹陷(如圖16B以及圖17B中所示)，而另一接合墊具有凹陷。
圖19說明接合墊54以及154在退火之後的橫截面圖。由於接合墊54與154發生相互擴散，金屬材料50與金屬材料150結合。凹陷56以及156的形成能有利地減少接合結構中生成的應力。舉例而言，金屬材料50以及150的熱膨脹係數(CTE)明顯不同於介電層42以及142的熱膨脹係數，其凹陷為金屬材料在熱循環(諸如預退火以及退火)期間的膨脹提供一定空間。因此，接合結構遭受的應力得到減少。
在退火之後，接合結構中可存在一些凹陷56'。由於金屬材料發生擴散，凹陷56'的形狀以及大小可不同於凹陷56以及156的形狀以及大小。舉例而言，凹陷56'的大小可小於凹陷56以及156在退火之前的組合大小。凹陷56'的高度可大於約50Å，且可在約50Å與約500Å之間的範圍內。根據替代實施例，在退火之後，凹陷消失。擴散障壁48以及148的形狀亦可發生改變以適應凹陷的減小以及消除。
圖20示出根據一些實施例的接合墊54以及154在預接合之後且在退火之前的橫截面圖，其中接合墊54並不與接合墊154豎直地對準。因此，凹陷56並不與對應凹陷156對準。圖21示出接合墊54以及154在退火之後的橫截面圖。由於接合墊54與154發生相互擴散，金屬材料50與金屬材料150結合。在橫截面圖中，面向另一金屬墊的中間部分的凹陷56以及156可被完全填充，或可被部分填充成具有減小的大小。面向對置介電層42以及142的凹陷可繼續存在。應瞭解，圖19以及圖21中所示的實施例可存在於同一封裝上。舉例而言，當發生旋轉未對準時，一些接合墊得到對準從而帶來圖19中所示的結構，且同一封裝中的一些其他接合墊可彼此未對準，從而帶來圖21中所示的結構。
圖22以及圖23分別示出在退火前後的接合墊，其中接合墊54以及154是對準的。接合墊54的大小不同於(大於或小於)接合墊154的大小。舉例而言，在所說明實例中，接合墊154大於接合墊54。結果，如圖23中所示，在接合之後，凹陷56(圖22)的大小減小或被完全填充，而凹陷156未被完全填充。
圖24以及圖25分別示出在退火前後的接合墊，其中接合墊54以及154未對準。接合墊54的大小不同於(大於或小於)接合墊154的大小。舉例而言，在所說明實例中，接合墊154大於接合墊54。如圖25中所示，在接合之後，凹陷56以及156(圖24)兩者的一些部分皆被填充，且一些其他部分未被填充。
返回參考圖6，根據一些實施例，在接合製程之後，可執行背側磨削以將裝置晶粒112薄化至例如介於約15μm與約30μm之間的厚度。圖6示意地說明虛線112-BS1，其為裝置晶粒112在背 側磨削之前的背表面。112-BS2為裝置晶粒112在背側磨削之後的背表面。藉由薄化裝置晶粒112，間隙53的縱橫比(aspect ratio)減小，以便執行間隙填充。否則，由於間隙53的原本較高縱橫比，間隙填充可較困難。在背側磨削之後，直通矽晶穿孔116可顯露出來。替代地，此時直通矽晶穿孔116未顯露出來，且當存在覆蓋直通矽晶穿孔116的薄基底層時，停止背側磨削。根據此等實施例，直通矽晶穿孔116可在圖8中所示的步驟中顯露出來。根據間隙53的縱橫比並不過高的其他實施例，跳過背側磨削。
圖7說明形成間隙填充層，其包含介電層62以及底層蝕刻終止層60。所對應的製程在圖28中所示的製程流程中說明為步驟214。蝕刻終止層60由對裝置晶粒112的側壁以及介電層42與接合墊54B的頂部表面具有良好黏附性的介電材料形成。根據本揭露的一些實施例，蝕刻終止層60由諸如氮化矽的含氮化物材料形成。蝕刻終止層60可為保形層，例如水平部分的厚度T1A與豎直部分的厚度T1B大體上彼此相等，例如厚度T1A與T1B兩者的差(T1A-T1B)具有小於約20百分比或小於約10百分比的絕對值。沈積可包含諸如原子層沈積(ALD)或化學氣相沈積(CVD)的保形沈積方法。當接合墊54B具有凹陷56(圖16A)時，蝕刻終止層60亦延伸至凹陷中。
介電層62由不同於蝕刻終止層60的材料的材料形成。根據本揭露的一些實施例，介電層62由氧化矽形成，所述氧化矽可由原矽酸四乙酯形成，同時亦可使用諸如碳化矽、氮氧化矽、碳氧氮化矽、磷矽酸鹽玻璃、硼矽酸鹽玻璃、硼摻雜磷矽酸鹽玻璃等的其他介電材料。可使用化學氣相沈積、高密度電漿化學氣相 沈積(High-Density Plasma Chemical Vapor Deposition，HDPCVD)、流動式化學氣相沈積、旋塗式塗佈等形成介電層62。介電層62完全填充剩餘間隙53(圖6)。
參考圖8，執行諸如化學機械研磨製程或機械磨削製程的平坦化製程，以移除間隙填充層60以及62的多餘部分，從而使得曝露出裝置晶粒112。各別製程亦在圖28中所示的製程流程中說明為步驟214。並且，曝露出穿孔116。層60以及62的剩餘部分被統稱為(間隙填充)隔離區64。
圖9說明蝕刻介電層62以形成開口66。所對應的製程在圖28中所示的製程流程中說明為步驟216。根據本揭露的一些實施例，形成並圖案化光阻(未示出)，並將經圖案化光阻作為蝕刻罩幕來蝕刻介電層62。因此，形成了開口66，且其向下延伸至充當蝕刻終止層的蝕刻終止層60。根據本揭露的一些實施例，介電層62包括氧化物，且可藉由乾式蝕刻來執行所述蝕刻。蝕刻氣體可包含NF3與NH3的混合物或HF與NH3的混合物。接下來，對蝕刻終止層60進行蝕刻，從而使得開口66向下延伸至介電接合墊54B。根據本揭露的一些實施例，蝕刻終止層60由氮化矽形成，且使用乾式蝕刻來執行所述蝕刻。蝕刻氣體可包含CF4、O2與N2的混合物、NF3與O2、SF6的混合物或SF6與O2的混合物。
圖10說明形成穿孔70，其填充開口66(圖9)且連接至接合墊54B。所對應的製程在圖28中所示的製程流程中說明為步驟218。根據本揭露的一些實施例，形成穿孔70包含執行諸如電化學電鍍製程或無電電鍍製程的電鍍製程。穿孔70可包含諸如鎢、鋁、銅等的金屬材料。亦可在金屬材料之下形成導電障壁層(諸如鈦、 氮化鈦、鉭、氮化鉭等)。執行諸如化學機械研磨的平坦化，以移除經電鍍金屬材料的多餘部分，且金屬材料的剩餘部分形成穿孔70。穿孔70可具有實質上筆直且豎直的側壁。並且，穿孔70可具有逐漸變窄的輪廓，其中頂部寬度略微大於各別底部寬度。
根據替代實施例，並不在裝置晶粒112中預形成直通矽晶穿孔116。實情為，在形成隔離區64之後形成直通矽晶穿孔116。舉例而言，在形成開口66(圖8)之前或之後，蝕刻裝置晶粒112以形成額外開口(由所說明直通矽晶穿孔116佔用)。可同時填充裝置晶粒112中的額外開口以及開口66，以形成貫通直通矽晶穿孔116以及穿孔70。所得直通矽晶穿孔116的上部部分寬於下部部分，與圖10中所示的直通矽晶穿孔116相反。
參考圖11，形成重佈線(redistribution line，RDL)72以及介電層74。所對應製程在圖28中所示的製程流程中說明為步驟220。根據本揭露的一些實施例，介電層74由諸如氧化矽的氧化物、諸如氮化矽的氮化物等形成。可使用鑲嵌製程形成重佈線72，所述製程包含蝕刻介電層74以形成開口，將導電障壁層沈積至開口中，電鍍諸如銅或銅合金的金屬材料，以及執行平坦化以移除金屬材料的多餘部分。
圖12說明形成鈍化層、金屬墊以及上覆介電層。所對應的製程亦在圖28中所示的製程流程中說明為步驟220。鈍化層76(有時被稱作鈍化-1)形成於介電層74上方，且通孔78形成於鈍化層76中以電連接至重佈線72。金屬墊80形成於鈍化層76上方，且藉由通孔78電耦合至重佈線72。金屬墊80可為鋁墊或鋁銅墊，且可使用其他金屬材料。
亦如圖12中所示，鈍化層82(有時被稱作鈍化-2)形成於鈍化層76上方。鈍化層76以及82中的每一者可為單層或複合層，且可由無孔材料形成。根據本揭露的一些實施例，鈍化層76以及82中的一者或兩者為複合層，其包含氧化矽層(未單獨示出)以及在氧化矽層上方的氮化矽層(未單獨示出)。鈍化層76以及82亦可由諸如未摻雜矽酸鹽玻璃(Un-doped Silicate Glass，USG)、氮氧化矽等的其他無孔介電材料形成。
接下來，圖案化鈍化層82，從而使得鈍化層82的一些部分覆蓋金屬墊80的邊緣部分，且藉由鈍化層82中的開口曝露出金屬墊80的一些部分。接著形成聚合物層84，且接著進行圖案化以曝露出金屬墊80。聚合物層84可由聚醯亞胺、聚苯并噁唑(polybenzoxazole，PBO)等形成。
根據本揭露的一些實施例，結構底層金屬墊80不含有機材料(諸如聚合物層)，從而使得用於形成結構底層金屬墊80的製程可採用用於形成裝置晶粒的製程，從而使得達成製成具有較小間距以及線寬的細小間距RDL(諸如72)。
參考圖13，形成後鈍化內連線(Post-Passivation Interconnect，PPI)86，此可包含形成金屬晶種層，以及在金屬晶種層上方形成經圖案化罩幕層(未示出)，並在經圖案化罩幕層中電鍍鈍化內連線86。接著在蝕刻製程中移除經圖案化罩幕層以及金屬晶種層的由經圖案化罩幕層交疊的部分。接著形成聚合物層88，其可由聚苯并噁唑、聚醯亞胺等形成。
參考圖14，形成凸塊下金屬(Under-Bump Metallurgies，UBM)90，且凸塊下金屬90延伸至聚合物層88中以連接至PPI 86。所對應的製程亦在圖28中所示的製程流程中說明為步驟220。根據本揭露的一些實施例，凸塊下金屬90中的每一者包含障壁層(未示出)以及在障壁層上方的晶種層(未示出)。障壁層可為鈦層、氮化鈦層、鉭層、氮化鉭層，或由鈦合金或鉭合金形成的層。晶種層的材料可包含銅或銅合金。諸如銀、金、鋁、鈀、鎳、鎳合金、鎢合金、鉻、鉻合金以及其組合的其他金屬亦可包含在凸塊下金屬90中。
亦如圖14中所示，形成電連接件92。所對應的製程亦在圖28中所示的製程流程中說明為步驟220。用於形成凸塊下金屬90以及電連接件92的形成製程包含沈積毯覆式凸塊下金屬層，形成並圖案化罩幕(其可為光阻，未示出)，其中藉由罩幕中的開口曝露出毯覆式凸塊下金屬層的部分。在形成凸塊下金屬90之後，將所說明封裝置放於電鍍溶液(未示出)中，且執行電鍍步驟以在凸塊下金屬90上形成電連接件92。根據本揭露的一些實施例，電連接件92包含非焊料部分(未示出)，所述部分在後續回焊製程中並不熔融。非焊料部分可由銅形成，且因此在下文中被稱為銅凸塊，但所述部分亦可由其他非焊料材料形成。電連接件92中的每一者亦可包含選自鎳層、鎳合金、鈀層、金層、銀層或其多層的頂蓋層(未示出)。頂蓋層形成於銅凸塊上方。電連接件92可更包含焊蓋，其可由錫銀合金、錫銅合金、錫銀銅合金等形成，且可不含鉛或含鉛。形成於前述步驟中的結構被稱為複合晶圓94。對複合晶圓94執行晶粒據割(單體化)步驟，以將複合晶圓94分離成多個封裝96。所對應的製程在圖28中所示的製程流程中說明為步驟222。
圖14中所示的封裝具有面對面結構，其中裝置晶粒112的前表面面向裝置晶粒4的前表面。圖15示出面對背(face-to-back)結構，其中裝置晶粒112的前表面面向裝置晶粒4的背表面。裝置晶粒4包含直通矽晶穿孔16，其延伸穿過基底20以及介電層17。圖15中的虛線區19表示諸如焊料區的可能電連接件。根據本揭露的一些實施例，對直通矽晶穿孔16以及介電層17執行化學機械研磨。化學機械研磨製程的細節可類似於參考圖16A所論述的細節，且因此形成了凹陷156，如圖25中所示。
圖26以及圖27說明接合具有直通矽晶穿孔16的接合墊154，其中圖26說明退火之前的結構，且圖27說明退火之後的結構。圖26中的層49可為介電隔離層，其可由氧化矽、氮化矽等形成。凹陷56可形成於直通矽晶穿孔16中，所述凹陷在退火之後減小或被完全消除。凹陷156在退火之後可仍存在。
本揭露的實施例具有一些有利特徵。藉由在接合墊中形成凹陷，能尤其在熱循環中減少接合結構中的應力。因此，改良了接合結構的可靠性。
根據本揭露的一些實施例，一種半導體裝置的形成方法包含：形成第一裝置晶粒，此包括沈積第一介電層，以及在第一介電層中形成第一金屬墊，其中第一金屬墊包括鄰近於第一金屬墊的邊緣部分的第一凹陷；形成第二裝置晶粒，所述第二裝置晶粒包括第二介電層；以及在第二介電層中的第二金屬墊；以及將第一裝置晶粒接合至第二裝置晶粒，其中將第一介電層接合至第二介電層，且將第一金屬墊接合至第二金屬墊。在實施例中，第一金屬墊包括：擴散障壁；以及在擴散障壁的相對部分之間的含 銅材料，其中含銅材料的邊緣部分凹陷到低於擴散障壁層的頂部邊緣以形成第一凹陷。在實施例中，所述接合包括：執行預退火；以及執行退火，其中在退火期間，第一凹陷減小。在實施例中，形成第一金屬墊包括執行平坦化，其中第一凹陷由所述平坦化生成。在實施例中，所述平坦化包括使用具有pH值低於約4.0的漿料執行的化學機械研磨(CMP)。在實施例中，使用包含乙酸以及銅螯合物的漿料來執行CMP。在實施例中，第二金屬墊包括鄰近於第二金屬墊的邊緣的第二凹陷，且在接合開始之時將第一凹陷接合至第二凹陷。在實施例中，第二金屬墊包括鄰近於第二金屬墊的邊緣的第二凹陷，且第一凹陷在接合開始之時與第二凹陷分離，並且在接合之後，第一凹陷繼續存在而第二凹陷消失。
根據本揭露的一些實施例，一種半導體裝置的形成方法包含：在晶圓的頂部表面上形成介電層；蝕刻介電層以在介電層中形成溝渠；以及在溝渠中形成第一金屬墊，其中第一金屬墊包括：接觸介電層的擴散障壁；以及在擴散障壁的相對部分之間的金屬材料，其中在第一金屬墊的橫截面圖中，金屬材料的頂部表面包括中間部分以及低於中間部分的邊緣部分，且邊緣部分低於擴散障壁的最近部分的頂部邊緣以形成凹陷。在實施例中，所述方法更包含將第二金屬墊接合至第一金屬墊，其中凹陷的大小至少減小。在實施例中，所述方法更包含形成延伸至凹陷中的介電蝕刻終止層；以及形成穿過介電蝕刻終止層的穿孔以連接至第一金屬墊。在實施例中，形成第一金屬墊包括化學機械研磨，且凹陷是在化學機械研磨期間形成。在實施例中，使用漿料來執行化學機械研磨，且所述漿料具有在約2.0與約4.0之間的範圍內的pH 值。在實施例中，金屬材料的頂部表面是彎曲的。
根據本揭露的一些實施例，一種半導體裝置包含：第一裝置晶粒，其包括第一介電層，以及第一金屬墊，所述第一金屬墊包括接觸第一介電層的擴散障壁，以及在擴散障壁的相對部分之間的金屬材料，其中在第一金屬墊的橫截面圖中，金屬材料的邊緣部分相比擴散障壁的最近部分的頂部邊緣凹陷以形成氣隙；以及第二裝置晶粒，其包括藉由融合接合而接合至第一介電層的第二介電層，以及藉由金屬至金屬直接接合而接合至第一金屬墊的第二金屬墊。在實施例中，氣隙進一步延伸至第二金屬墊中。在實施例中，氣隙形成於擴散障壁的側壁、金屬材料的表面與第二金屬墊的表面之間。在實施例中，氣隙形成於擴散障壁的側壁、金屬材料的表面與第二介電層的表面之間。在實施例中，金屬材料的面向氣隙的表面是曲面。在實施例中，第一裝置晶粒更包括第三金屬墊，所述第三金屬墊包括額外凹陷，且裝置更包含延伸至額外凹陷中的介電蝕刻終止層；在介電蝕刻終止層上方且接觸所述介電蝕刻終止層的介電層；以及穿過介電蝕刻終止層以及介電層以連接至第三金屬墊的穿孔。
前文概述若干實施例的特徵，從而使得熟習此項技術者可較好地理解本發明的態樣。熟習此項技術者應瞭解，其可易於使用本發明作為設計或修改用於進行本文中所引入的實施例的相同目的及/或達成相同優勢的其他製程以及結構的基礎。熟習此項技術者亦應認識到，此類等效構造並不脫離本發明的精神以及範疇，且其可在不脫離本發明的精神以及範疇的情況下在本文中進行各種改變、替代以及更改。

Claims (9)

  1. 一種半導體裝置的形成方法，包括：形成第一裝置晶粒，包括：沈積第一介電層；以及在所述第一介電層中形成第一金屬墊，其中所述第一金屬墊包括鄰近於所述第一金屬墊的邊緣部分的第一凹陷；形成第二裝置晶粒，所述第二裝置晶粒包括：第二介電層；以及第二金屬墊，其在所述第二介電層中；以及將所述第一裝置晶粒接合至所述第二裝置晶粒，其中將所述第一介電層接合至所述第二介電層，且將所述第一金屬墊接合至所述第二金屬墊，所述接合包括：執行預退火；以及執行退火，其中在所述退火期間，所述第一凹陷減小。
  2. 如申請專利範圍第1項所述的方法，其中所述第一金屬墊包括：擴散障壁；以及含銅材料，其在所述擴散障壁的相對部分之間，其中所述含銅材料的邊緣部分凹陷到低於所述擴散障壁的頂部邊緣以形成所述第一凹陷。
  3. 如申請專利範圍第1項所述的方法，其中所述形成所述第一金屬墊包括執行平坦化，其中所述第一凹陷由所述平坦化生成。
  4. 一種半導體裝置的形成方法，包括：在晶圓的頂部表面上形成介電層；蝕刻所述介電層以在所述介電層中形成溝渠；以及在所述溝渠中形成第一金屬墊，其中所述第一金屬墊包括：擴散障壁，其接觸所述介電層；以及金屬材料，其在所述擴散障壁的相對部分之間，其中在所述第一金屬墊的橫截面圖中，所述金屬材料的頂部表面是彎曲的且包括中間部分以及低於所述中間部分的邊緣部分，且所述邊緣部分低於所述擴散障壁的最近部分的頂部邊緣以形成凹陷。
  5. 如申請專利範圍第4項所述的方法，更包括：形成延伸至所述凹陷中的介電蝕刻終止層；以及形成穿過所述介電蝕刻終止層的穿孔以連接至所述第一金屬墊。
  6. 一種半導體裝置，包括：第一裝置晶粒，所述第一裝置晶粒包括：第一介電層；以及第一金屬墊，所述第一金屬墊包括：擴散障壁，其接觸所述第一介電層；以及金屬材料，其在所述擴散障壁的相對部分之間，其中在所述第一金屬墊的橫截面圖中，所述金屬材料的邊緣部分自所述擴散障壁的最近部分的頂部邊緣凹陷以形成氣隙，所述金屬材料面向所述氣隙的表面是曲面；以及第二裝置晶粒，所述第二裝置晶粒包括：第二介電層，其接合至所述第一介電層；以及第二金屬墊，其藉由金屬至金屬直接接合而接合至所述第一金屬墊。
  7. 如申請專利範圍第6項所述的裝置，其中所述氣隙進一步延伸至所述第二金屬墊中。
  8. 如申請專利範圍第6項所述的裝置，其中所述氣隙形成於所述擴散障壁的側壁、所述金屬材料的表面與所述第二金屬墊的表面之間。
  9. 如申請專利範圍第6項所述的裝置，其中所述第一裝置晶粒更包括第三金屬墊，所述第三金屬墊包括額外凹陷，且所述裝置更包括：介電蝕刻終止層，其延伸至所述額外凹陷中；介電層，其在所述介電蝕刻終止層上方且接觸所述介電蝕刻終止層；以及穿孔，其穿過所述介電蝕刻終止層以及所述介電層以連接至所述第三金屬墊。
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