CN104051288A - 用于混合晶圆接合的方法 - Google Patents

用于混合晶圆接合的方法 Download PDF

Info

Publication number
CN104051288A
CN104051288A CN201310485415.8A CN201310485415A CN104051288A CN 104051288 A CN104051288 A CN 104051288A CN 201310485415 A CN201310485415 A CN 201310485415A CN 104051288 A CN104051288 A CN 104051288A
Authority
CN
China
Prior art keywords
semiconductor crystal
crystal wafers
metal pad
pad layer
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201310485415.8A
Other languages
English (en)
Other versions
CN104051288B (zh
Inventor
刘丙寅
刘人诚
陈晓萌
黄信华
林宏桦
赵兰璘
蔡嘉雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN104051288A publication Critical patent/CN104051288A/zh
Application granted granted Critical
Publication of CN104051288B publication Critical patent/CN104051288B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H01L21/187—Joining of semiconductor bodies for junction formation by direct bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03616—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0383—Reworking, e.g. shaping
    • H01L2224/03845—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05655—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/08112—Disposition the bonding area being at least partially embedded in the surface of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08121—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the connected bonding areas being not aligned with respect to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08147—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a bonding area disposed in a recess of the surface of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8003—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area
    • H01L2224/80035—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area by heating means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/8093—Reshaping
    • H01L2224/80935—Reshaping by heating means, e.g. reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)

Abstract

公开一种用于混合晶圆接合的方法。在一个实施例中，公开了一种方法，包括：在至少两个半导体衬底之上的介电层中形成金属焊盘层；对半导体衬底执行化学机械抛光，以暴露金属焊盘层的表面，并且平坦化介电层，以在每个半导体衬底上形成接合表面；对至少两个半导体衬底执行氧化工艺，以氧化金属焊盘层，形成金属氧化物；执行蚀刻以去除金属氧化物，使金属焊盘层的表面从至少两个半导体衬底中的每个的介电层的接合表面凹陷；使至少两个半导体衬底的接合表面在物理上接触；以及执行热退火，以在半导体衬底的金属焊盘之间形成接合。公开了附加方法。

Description

用于混合晶圆接合的方法
相关申请
本申请涉及于2013年3月15日提交的名为“Methods for Hybrid WaferBonding”的代理案号为TSM13-0210P的第61/793,766号美国临时专利申请，其申请还全部结合于此作为参考。
技术领域
实施例总体涉及衬底之间的接合的使用，衬底包括但不限于半导体衬底。使用相应金属区的轮廓匹配在衬底之间形成接合，以形成良好成对表面，并且在低处理温度下使用低热压力在金属区之间实现牢固的接合连接。晶圆接合的使用可应用至多种器件，其中，接合包括3D IC并且特别是CMOS图像传感器器件的两个衬底。
背景技术
用于晶圆接合的新改进在3D IC结构中日益重要。在晶圆接合时，在不需要中介衬底或器件的情况下，两个半导体晶圆被接合到一起以形成三维堆叠件。在需要两种不同晶圆类型的应用中，该方法可以提供在一个封装中具有两个功能器件的单个器件。在一个特定应用中，CMOS图像传感器、包括图像传感器阵列的衬底可以被接合到电路晶圆上，以提供包括在与传感器阵列相同的电路板区域中实现图像传感器所需的所有电路的3DIC系统，在单个封装的集成电路器件中提供完整图像传感方案。
先前已知的晶圆接合方法包括氧化物-氧化物或者熔融接合、以及使用热压接合的金属到金属接合，在高压下并且使用高温执行该热压接合。这些现有方法在器件上引入高机械应力和热应力，或者不能提供所需的金属到金属连接。
发明内容
为了解决现有技术中所存在的问题，根据本发明的一个方面，提供了一种方法，包括：在至少两个半导体衬底之上的介电层中形成金属焊盘层；对所述半导体衬底执行化学机械抛光，以暴露所述金属焊盘层的表面，并且平坦化所述介电层，以在每个所述半导体衬底上形成接合表面；对所述至少两个半导体衬底执行氧化工艺，以氧化所述金属焊盘层，从而形成金属氧化物；执行蚀刻，以去除所述金属氧化物，从所述至少两个半导体衬底的每一个的所述介电层的所述接合表面中暴露出所述金属焊盘层的表面；将所述至少两个半导体衬底的所述接合表面物理接触；以及执行热退火，以在所述半导体衬底的所述金属焊盘层之间形成接合。
在所述方法中，形成所述金属焊盘层包括：形成选自主要包括铜、铝、铜铝、镍、铝锗及它们的合金的组中的一种。
在所述方法中，形成所述金属焊盘层包括：形成铜。
在所述方法中，对所述半导体衬底执行氧化工艺包括：执行湿式氧化。
在所述方法中，对所述至少两个半导体衬底执行氧化工艺包括：执行选自主要包括O2等离子体、热氧化和原位蒸气生成氧化的组中的一种。
在所述方法中，执行蚀刻以去除所述金属氧化物包括：使用稀释HF执行蚀刻。
在所述方法中，执行蚀刻以去除所述金属氧化物包括：使用主要包括稀释HF、HCl、HCOOH和柠檬酸蚀刻剂的组中的一种。
在所述方法中，进一步包括：在低于250℃的温度下执行所述蚀刻。
在所述方法中，在高于100℃并且低于400℃的温度下执行退火。
在所述方法中，在高于250℃的温度下执行所述退火。
在所述方法中，在去除氧化物之后，所述金属焊盘在所述半导体衬底的所述接合表面下面凹陷小于约10埃。
在所述方法中，去除所述氧化物之后的所述至少两个半导体衬底的所述金属焊盘的表面轮廓满足预定轮廓匹配参数。
根据本发明的另一方面，提供了一种接合半导体晶圆的方法，包括：在至少两个半导体晶圆上的介电层中形成金属焊盘层；对所述至少两个半导体晶圆的每一个执行CMP工艺，以暴露所述金属焊盘层，并且平坦化所述介电层，以在所述至少两个半导体晶圆的每一个上形成接合面；对所述至少两个半导体晶圆的每一个执行氧化工艺，以在所述金属焊盘层中形成金属氧化物；对所述至少两个半导体晶圆的每一个执行氧化物蚀刻工艺，以去除所述金属氧化物，暴露每个所述金属焊盘层的凹陷表面；确定每个所述金属焊盘层的所述凹陷表面满足轮廓匹配标准；响应于所述确定，将所述至少两个半导体晶圆上的所述接合面以面对面关系对准；将所述至少两个半导体晶圆的所述接合面物理接触；以及随后，退火所述至少两个半导体晶圆；其中，接合发生在所述至少两个半导体晶圆的所述介电层之间和所述金属焊盘层之间。
在所述方法中，所述轮廓匹配标准包括：从所述介电层的表面到所述金属焊盘层的平坦表面的凹陷深度小于或等于10埃。
在所述方法中，所述轮廓匹配标准包括：确定一个半导体晶圆的从所述介电层的表面到所述金属焊盘层的平坦表面的单位为埃的凹陷深度加上20小于另一个半导体晶圆的从所述介电层的表面到所述金属焊盘层的平坦表面的单位为埃的凹陷深度。
根据本发明的又一方面，提供了一种晶圆接合的方法，包括：在至少两个半导体晶圆上的介电层中形成铜焊盘层；对所述至少两个半导体晶圆的每一个的所述介电层执行CMP工艺，以暴露所述铜焊盘层，并且平坦化所述介电层，以在所述至少两个半导体晶圆的每一个上形成接合面；对所述至少两个半导体晶圆的每一个执行氧化工艺，以在所述铜焊盘层中形成铜氧化物至预定深度；对所述至少两个半导体晶圆的每一个执行氧化物蚀刻工艺，以去除所述铜氧化物，暴露每个所述铜焊盘层的凹陷平坦表面；将所述至少两个半导体晶圆上的所述接合面以面对面关系对准；将所述至少两个半导体晶圆的所述接合面物理接触；以及热退火所述至少两个半导体晶圆；其中，接合发生在所述至少两个半导体晶圆的所述介电层之间和所述铜焊盘层之间。
在所述方法中，对所述至少两个半导体晶圆的每一个执行氧化工艺包括：执行O2等离子体工艺。
在所述方法中，对所述至少两个半导体晶圆的每一个执行氧化物蚀刻工艺包括：执行稀释HF蚀刻工艺。
在所述方法中，执行所述退火包括：在高于100℃的温度下执行退火。
在所述方法中，执行所述退火包括：在高于250℃的温度下执行退火。
附图说明
为了更完整地理解在此描述的示例性实施例及其优点，现在结合附图对以下说明书作出参考，其中：
图1在横断面视图中示出用于说明实施例的一部分衬底；
图2A和图2B在横断面视图中示出中间处理步骤下的顶部和底部衬底；
图3A和图3B在横断面视图中示出附加工艺步骤之后的图2A和图2B的顶部和底部衬底；
图4A和图4B在横断面视图中示出附加工艺步骤之后的图3A和图3B的顶部和底部衬底；
图5在另一个横断面视图中示出接合工艺中的图4A和图4B的顶部和底部衬底；
图6在另一个横断面视图中示出退火工艺中的图5A的顶部和底部衬底；
图7在横断面视图中示出在实施例中应用的轮廓匹配参数；
图8在流程图中示出方法实施例的步骤；以及
图9在比较表中示出使用形成示例性结构的实施例获得的结果。
除非另外指出，不同图中的相应数字和符号通常是指相应部分。绘制附图的目的在于清楚地示出实施例的相关方面并且无需按比例绘制。
具体实施方式
下面，详细讨论本发明各实施例的制造和使用。然而，应该理解，实施例提供了许多可以在各种具体环境中实现的可应用的概念。所讨论的具体实施例仅仅示出了制造和使用本发明的具体方式，而不用于限制说明书或所附权利要求的范围。
越来越多地使用通过制造3D器件来在半导体器件中提供更高的集成的晶圆接合。实施例提供用于金属与金属接合的方法，在两个衬底之间的界面处提供牢固的连接。在一些实施例中，衬底是半导体衬底，而在一些实施例中，衬底是半导体晶圆。在一个实施例中，至少一个衬底包括图像传感器阵列。在一个实施例中，衬底包括提供金属连接和通孔连接的施体晶圆，该施体晶圆可以被接合到另一个器件晶圆上，并且然后可以使用机械磨削或CMP方法磨掉施体晶圆的衬底，留下接合到器件晶圆上的金属层。在一个实施例中，可以接合多个晶圆以形成具有多个层的3D IC结构。
在实施例中，使用化学机械工艺（CMP）暴露两个衬底的接合表面上的金属焊盘，并且平坦化这两个表面。然后，通过氧化暴露的金属焊盘形成金属氧化物层。在实施例中，在氧化工艺过程中，小心地控制工艺条件。在氧化工艺之后，使用良好控制的蚀刻工艺从金属焊盘中去除金属氧化物，暴露出表面。在多种实施例中，使用湿式蚀刻工艺。所使用的氧化工艺和湿式蚀刻工艺的控制给金属焊盘提供非常匹配的表面轮廓。然后，两个衬底以面对面关系对准，并且相应的金属焊盘相互接近，同时两个衬底的周围介电材料相互接触。熔融接合可能发生在接触的介电层之间。使用退火工艺使金属焊盘之间产生接合并且增强介电层之间的接合，执行混合接合工艺。因为金属焊盘具有在特定参数内的匹配的表面轮廓，所以金属焊盘甚至在相对低的工艺温度下并且在不需要高机械压力的情况下形成牢固的接合。
在多种实施例中，用于金属焊盘的金属是铜（Cu）、铝（Al）、铜铝（AlCu）、镍（Ni）、铝锗（AlGe）以及这些金属的合金。金属焊盘被形成为介电材料中的镶嵌结构。多种实施例中的介电材料选自诸如SiO2的氧化物、诸如SiN的氮化物、氮氧化物（SiON）、以及在半导体器件中使用的高k电介质。
在一个实施例中，使用镶嵌或双镶嵌金属化方案，形成由介电材料包围的铜金属焊盘。在化学机械抛光（CMP）和平坦化之后，衬底经历氧化工艺。在一个示例性实施例中，使用O2等离子体形成氧化铜。在可选实施例中，使用其他氧化工艺。可以使用诸如，原位水汽生成（ISSG）的蒸汽氧化工艺。
然后，通过湿式蚀刻工艺执行铜氧化物去除。在一个实施例中，使用稀释HF蚀刻。在可选实施例中，湿式蚀刻选自包括浓度为2%的DHF、HCl、HCOOH、柠檬酸的氧化物蚀刻剂。在一些实施例中，蚀刻工艺的温度小于250℃。
在去除氧化铜之后，对于衬底的铜焊盘轮廓匹配进行检查。焊盘可以从介电材料的表面稍微凹陷。在良好控制的蚀刻工艺之后形成氧化铜减少或消除由CMP工艺得到的非均匀表面，诸如，凹陷。工艺的控制允许在铜焊盘的表面上产生稍微凸起或凹入并且非常均匀的表面。
通过使用实施例方法，铜焊盘具有几乎均匀的表面。铜焊盘的凹陷深度在顶部衬底上的铜焊盘和底部衬底上的相应铜焊盘之间良好地匹配。通过良好匹配的铜焊盘轮廓选择的顶部和底部衬底开始对准，并且然后接触，介电层进行物理接触并且顶部和底部衬底的铜焊盘稍微间隔开。衬底的介电表面充分接触。介电层的熔融接合可以开始。一旦衬底开始进行物理接触，就执行相对低温度退火。在退火期间，各个铜焊盘形成无缝接合。介电层之间的接合将继续，或者接合强度在退火期间将继续增加。当铜焊盘的表面轮廓很好地匹配并且金属焊盘凹陷深度在特定预定范围内时，形成牢固的接合。这被称为“无缝”接合，其中，横跨接合界面的铜材料看起来是均匀的。还在混合接合工艺（hybrid bonding process）中接合介电表面。
图1在横断面视图中示出一部分衬底100。衬底可以是半导体衬底，诸如，硅、砷化镓、锗或者铟衬底。如在本领域中已知的，在衬底100之上形成多个金属层和介电层。在实施例中，在衬底100的上表面处示出一层金属101。使用诸如，单或双镶嵌工艺的镶嵌工艺形成金属101。在形成金属101的导体之后，使用化学机械抛光（CMP）工艺去除在电镀工艺之后留下的任何装载过多的金属，并且CMP还对电介质103的表面实行抛光以形成接合表面。图1中的金属和电介质的剩余下层可以形成用于半导体器件的布线图案。可以使用诸如105的通孔形成金属层之间的垂直连接。虽然未示出，但是还可以在衬底100上形成诸如晶体管的有源器件。在另一个实施例中，例如，衬底100可以包括图像传感器器件，以形成CMOS图像传感器衬底。
还如图1中所示，CMP之后的金属焊盘101的上表面将是不均匀的。即使用于平坦化金属101的CMP工艺经常改进，但导致出现凹陷区域、小丘或高区域的效果，诸如，凹陷或过抛光仍然存在。虽然使用添加增加均匀性的虚拟金属图案，改变砂浆成分，以及其他补偿方法来改进CMP结果，但是CMP工艺在金属焊盘101上仍旧无法产生非常均匀的表面。例如，区域109示出CMP凹陷效果。
图2A和图2B在横断面视图中示出顶部衬底200和底部衬底300，以示出示例性实施例方法。在图2中，示出在CMP工艺之后的中间处理步骤下的衬底200。焊盘205由金属形成。在示例性实施例中，金属是铜。层间电介质203被示出在金属焊盘层205下面。电介质207被示出包围金属焊盘205。如图1中所示，由于CMP效果，导致金属焊盘205的表面是不规则的。电介质207的表面形成用于顶部衬底的接合表面208。
类似地，在图2B中，示出在CMP之后的相同中间处理步骤下的底部衬底300。金属焊盘305被示出具有相似但是稍微不同的不规则表面。还示出电介质307和层间电介质303。电介质307的表面308形成用于底部衬底300的接合表面。
图3A和图3B示出在对金属焊盘205执行氧化工艺之后的顶部衬底200和底部衬底300。在一个实施例中，金属焊盘是铜，并且氧化209和309形成氧化铜。氧化工艺可以是O2等离子体工艺、热氧化工艺、原位水汽生成氧化工艺（ISSG）、或其他氧化工艺。在方法实施例中，控制氧化工艺以从顶面形成特定深度的氧化物层。然而，要注意到：一部分衬底300具有在电介质307的表面之上延伸的氧化物层309。参考以上图2B，金属305的相同部分也在焊盘307的表面之上延伸。从而，在对铜305进行氧化时图案被重复。
图4A和图4B在横断面视图中示出附加工艺之后的顶部衬底200和底部衬底。在图4A和图4B中，示出在执行了从衬底去除氧化铜层的氧化物蚀刻之后的衬底200和300。在一个实施例中，使用浓度约为2%的稀释HF蚀刻溶液。多种可选实施例包括HCL、HCOOH、以及柠檬酸蚀刻剂。在实施例中，蚀刻工艺被严格控制从而去除金属氧化物到受控的深度。在图4A中，顶部衬底200的凹陷深度被示出为“TD”，其是从介电层的上表面到金属焊盘的顶面的距离。类似地，在图4B中，底部衬底300的凹陷深度被示出为“BD”。
图5在横断面视图中示出顶部衬底200和底部衬底300的对准和接触接合。在该阶段，顶面被翻转，并且使接合表面与衬底300的接合表面面对面定向，部件对准，并且顶部衬底和底部衬底被移动以在介电层之间物理接触。图5中示出接合界面215。熔融接合可以在触点处的相应的介电层之间开始。虽然很接近，但是在工艺中的这个阶段中铜焊盘205和305是稍微间隔开的。然而，已经发现：如以下所述，如果金属焊盘的表面轮廓和/或凹陷深度满足特定标准，则在金属焊盘之间实现牢固的接合。
图6在另一个横断面视图中示出应用至衬底200和300的实施例方法的附加工艺步骤。在图6中，对已经接触的顶部衬底200和底部衬底300执行退火。如图6中所示，接合铜焊盘205和305并且形成无缝接合。使用实施例方法形成的焊盘到焊盘接合具有足够的接合强度来支持剩余工艺步骤。
退火温度可以在约100℃和约400℃之间变化。退火的时间可以从几秒、几分钟到几个小时，所获得的接合强度将随着附加退火时间而增加。要注意的是：如上所述，虽然实施例不要求使用超高真空，但是如果大气压不受控制，在蚀刻工艺之后金属焊盘倾向于氧化，使用低真空或者使用惰性气体来净化退火室可以用于防止或减少在完成氧化物蚀刻工艺之后的不期望的金属氧化物的形成。
当金属焊盘良好匹配时，实施例的轮廓匹配提供出色的金属焊盘与金属焊盘接合。图7在横断面视图中示出顶部衬底200和底部衬底300。它们中的每个都具有在所示的电介质的表面下面的相应凹陷或焊盘深度。顶部深度TD是从金属焊盘的表面到顶部衬底200的电介质表面的距离，底部深度BD是从底部衬底300上的电介质的表面到金属焊盘305的表面的距离。在一个方法实施例中，如图7中所示，如果单位为埃的顶部深度TD+20小于单位为埃的底部深度BD，则确定衬底具有用于形成焊盘到焊盘接合的良好轮廓匹配。这是轮廓匹配参数的一个实施例。可以使用其他轮廓匹配参数形成附加方法实施例。例如，在另一个实施例中，如果顶部和底部衬底的凹陷深度TD和BD被确定为小于10埃，则该对衬底满足轮廓匹配标准。在典型实施例中，样本衬底基于使用原子力显微镜（AFM）在金属焊盘处测量的凹陷或突出的量被划分为多组，并且该对顶部和底部衬底被接合。“A”组被限定为具有从-260埃到-20埃的凹陷（其中，0埃是氧化物蚀刻之后的理想水平的平坦表面）。第二组“B”被限定为具有在-30埃至+10埃之间的凹陷或突出。第三组“C”被限定为具有在-10埃至+10埃之间的凹陷或突出。通过从多组选择顶部和底部衬底，在A组衬底之间、以及A组和B组衬底之间执行成功接合。通过使用顶部和底部衬底中的匹配轮廓，混合接合工艺在没有机械压力的情况下并且在低温下形成牢固的接合。
图8在流程图中示出方法实施例的步骤。在步骤801，至少两个衬底经过CMP工艺从而暴露金属焊盘并且平坦化电介质的接合表面。在步骤803，执行受控氧化工艺，以将金属焊盘氧化至特定深度。在步骤805，执行受控蚀刻，以去除金属氧化物，在电介质表面下面凹陷的金属焊盘上留下均匀表面。在步骤807，为了满足良好接合的预定标准的轮廓匹配而检验衬底。在一个实施例中，标准在于，顶部深度（从顶部衬底的接合面电介质的上表面到顶部衬底的金属焊盘的表面的凹陷距离，单位为埃）+20小于底部深度（从底部衬底上的接合面电介质的顶面到底部衬底上的金属焊盘的表面的凹陷距离，单位为埃）。一旦识别出轮廓匹配的合适衬底，在步骤809，以面对面关系对准所选出的顶部和底部衬底。在步骤811，衬底在低温或室温下物理接触。电介质表面可以在工艺的这个阶段开始熔融接合。在步骤813，执行相对低温退火。例如，退火可以在从40℃至超过250℃并且高达400℃的温度内变化，并且退火时间可以从几秒到几分钟并且多达几小时地变化。在退火期间实现金属焊盘到金属焊盘接合。由此实施例的混合接合工艺在各个介电层之间并且在各个金属焊盘之间形成接合，并且接合具有足够的接合强度来支持在实现器件时使用的剩余工艺。
在示例性实施例中，金属焊盘是铜。在附加实施例中，金属焊盘可以选自铜（Cu）、铝（Al）、铝铜（AlCu）、镍（Ni）、铝锗（AlGe）、以及这些金属的合金。多种实施例中的介电材料是SiO2，氮化物，诸如SiN、氮氧化硅（SiON）和/或在半导体器件中使用的高k电介质。
在示例性实施例中，使用稀释HF湿式蚀刻。在可选实施例中，湿式蚀刻选自氧化物蚀刻剂，包括浓度为2%的DHF、HCl、大于2%的HCOOH、以及柠檬酸。在多种实施例中，蚀刻工艺的温度低于250℃。
图9在包括SEM图像的表中表示在没有实施例的轮廓匹配的情况下执行的晶圆接合与使用实施例的两个实例之间的比较。在第一实例中，在CMP之后，凹陷水平被示出为70埃（顶部衬底）和260埃（底部衬底）。图9中所示的焊盘表面的轮廓是粗糙且不平坦的，并且不满足实施例的轮廓匹配标准。用于该实例的SEM图像示出顶面和底表面的铜焊盘之间的可见缝隙。即，铜金属焊盘之间的接合未成功地形成。
相比之下，图9中所示的另外两个实例示出使用实施例方法形成铜焊盘中的无缝接合。在中间列中，示出具有小凹陷的实例，顶面和底表面在电介质表面的10埃内，并且如SEM图中所示，在顶面和底表面的铜焊盘之间形成无缝接合。最后，第三列示出使用实施例提供的宽工艺窗口。在第三列中，凹陷包括顶部衬底的7埃至30埃的凹陷。然而，底部衬底是+/-10埃。如SEM图像中所示，对于图9中的第三列，该配对也产生了铜焊盘之间的无缝接合。
实施例的使用优选在相对低工艺温度下提供牢固的电介质接合和金属焊盘接合。与先前使用的热压接合技术形成鲜明对比，可能导致氧化物破裂和分层以及介电层上的侵蚀效果的半导体衬底上的压力被减少或消除。低温处理防止由于材料之间的热膨胀系数（CTE）失配导致的问题，这些问题可能导致分层和破裂。为了热压金属接合使介电层凹陷以暴露介电层之上的铜焊盘的需要也通过使用实施例被消除。由于现有方法中的蚀刻工艺导致的介电层的侵蚀被减少或消除。
在一个实施例中，一种方法包括：在至少两个半导体衬底之上的介电层中形成金属焊盘层；对半导体衬底执行化学机械抛光以暴露金属焊盘层的表面，并且平坦化介电层以在每个半导体衬底上形成接合表面；对至少两个半导体衬底执行氧化工艺以氧化金属焊盘层，形成金属氧化物；执行蚀刻以去除金属氧化物，使金属焊盘层的表面从至少两个半导体衬底中的每个的介电层的接合表面凹陷；使至少两个半导体衬底的接合表面物理接触；以及执行热退火，以在半导体衬底的金属焊盘之间形成接合。
在进一步实施例中，以上方法包括：形成选自主要由铜、铝、铜铝、镍、铝锗、及其合金构成的组中的金属。在又一个方法实施例中，以上方法包括：形成铜。在另一个实施例中，以上方法包括：执行热氧化。在还有的另一个实施例中，在以上方法中执行氧化工艺，该氧化工艺包括O2等离子体、热氧化、以及原位蒸汽发生原位水汽生成氧化中的一种。
在还有的另一个实施例中，在以上方法中，执行蚀刻包括：使用稀释HF执行蚀刻。在还有的另一个实施例中，执行去除金属氧化物的蚀刻，其蚀刻剂包括稀释HF、HCl、HCOOH、以及柠檬酸蚀刻剂中的一种。在还有的另一个实施例中，执行以上方法，并且进一步包括：在低于250℃的温度下执行蚀刻。在还有的另一个实施例中，在以上方法中，在高于100℃的温度下执行退火。在还有的进一步实施例中，在以上方法中，在高于250℃的温度下执行退火。在另一个实施例中，在以上方法中，其中，在氧化物去除之后，金属焊盘在半导体衬底的接合表面下面的凹陷小于10埃。
在还有的另一个实施例中，在以上方法中，其中，氧化物去除之后的至少两个半导体衬底的金属焊盘的表面轮廓满足预定轮廓匹配参数。
在另一个实施例中，一种接合半导体晶圆的方法包括：在至少两个半导体晶圆上的介电层中形成金属焊盘层；对至少两个半导体晶圆中的每个执行CMP工艺，以暴露金属焊盘层，并且平坦化介电层，以在至少两个半导体晶圆中的每个上形成接合面；对至少两个半导体晶圆中的每个执行氧化工艺，以在金属焊盘层中形成到预定深度的金属氧化物；对至少两个半导体晶圆中的每个执行氧化物蚀刻工艺，以去除金属氧化物，暴露每个金属焊盘层的凹陷的平坦表面；确定每个金属焊盘层的平坦表面满足轮廓匹配标准；响应于该确定，使至少两个半导体晶圆上的接合面以面对面关系对准；使至少两个半导体晶圆的接合面物理上接触；以及随后退火至少两个半导体晶圆；其中，接合发生在各个介电层之间和至少两个半导体晶圆的各个金属焊盘层之间。
在还有的进一步方法实施例中，以上方法包括：其中，轮廓匹配标准包括：从介电层的表面到金属焊盘层的平坦表面的凹陷深度小于或等于10埃。在还有的另一个实施例中，在以上方法中，其中轮廓匹配标准包括：确定单位为埃的从介电层的表面到金属焊盘层的平坦表面的半导体晶圆之一的凹陷深度加上20小于单位为埃的从介电层的表面到金属焊盘层的平坦表面的所述半导体晶圆中的另一个凹陷深度。
在还有的另一个实施例中，一种方法包括：在至少两个半导体晶圆上的介电层中形成铜焊盘层；对至少两个半导体晶圆中的每个执行CMP工艺，以暴露铜焊盘层，并且平坦化介电层，以在至少两个半导体晶圆中的每个上形成接合面；对至少两个半导体晶圆中的每个执行氧化工艺，以在铜焊盘层中形成到预定深度的铜氧化物；对至少两个半导体晶圆中的每个执行氧化物蚀刻工艺，以去除铜氧化物，暴露每个铜焊盘层的凹陷的平坦表面；使至少两个半导体晶圆上的接合面以面对面关系对准；使至少两个半导体晶圆的接合面在物理上接触；以及热退火至少两个半导体晶圆；其中，接合发生在各个介电层之间以及至少两个半导体晶圆的各个铜焊盘层之间。
在还有的另一个实施例中，在以上方法中，对至少两个半导体晶圆中的每个执行氧化工艺包括：执行O2等离子体工艺。在还有的另一个实施例中，在以上方法中，对至少两个半导体晶圆中的每个执行氧化物蚀刻工艺包括执行稀释HF蚀刻工艺。在还有的另一个方法中，执行退火包括在高于100℃的温度下执行退火。在还有的另一个实施例中，在以上方法中，执行退火包括在高于250℃的温度下执行退火。
虽然已经详细地描述了示例性实施例，但是应该理解，可以在不脱离由所附权利要求限定的申请的精神和范围的情况下，在此作出多种改变、替换和更改。
而且，本申请的范围不旨在限于工艺、机器、制造以及在说明书中描述的事物、手段、方法和步骤的组合的特定实施例。本领域普通技术人员从本公开可以容易地想到，根据本公开可以利用执行与在此描述的相应实施例基本相同的功能或者实现与其基本相同的结果的当前存在或随后开发的工艺、机器、制造、事物、手段、方法或步骤的组合。从而，所附权利要求旨在包括在这样的工艺、机器、制造、事物、手段、方法或步骤的组合的范围内。

Claims (10)

1.一种方法，包括：
在至少两个半导体衬底之上的介电层中形成金属焊盘层；
对所述半导体衬底执行化学机械抛光，以暴露所述金属焊盘层的表面，并且平坦化所述介电层，以在每个所述半导体衬底上形成接合表面；
对所述至少两个半导体衬底执行氧化工艺，以氧化所述金属焊盘层，从而形成金属氧化物；
执行蚀刻，以去除所述金属氧化物，从所述至少两个半导体衬底的每一个的所述介电层的所述接合表面中暴露出所述金属焊盘层的表面；
将所述至少两个半导体衬底的所述接合表面物理接触；以及
执行热退火，以在所述半导体衬底的所述金属焊盘层之间形成接合。
2.根据权利要求1所述的方法，其中，形成所述金属焊盘层包括：形成选自主要包括铜、铝、铜铝、镍、铝锗及它们的合金的组中的一种。
3.根据权利要求1所述的方法，其中，形成所述金属焊盘层包括：形成铜。
4.根据权利要求1所述的方法，其中，对所述半导体衬底执行氧化工艺包括：执行湿式氧化。
5.根据权利要求1所述的方法，其中，对所述至少两个半导体衬底执行氧化工艺包括：执行选自主要包括O2等离子体、热氧化和原位蒸气生成氧化的组中的一种。
6.根据权利要求1所述的方法，其中，执行蚀刻以去除所述金属氧化物包括：使用稀释HF执行蚀刻。
7.根据权利要求1所述的方法，其中，执行蚀刻以去除所述金属氧化物包括：使用主要包括稀释HF、HCl、HCOOH和柠檬酸蚀刻剂的组中的一种。
8.根据权利要求7所述的方法，进一步包括：在低于250℃的温度下执行所述蚀刻。
9.一种接合半导体晶圆的方法，包括：
在至少两个半导体晶圆上的介电层中形成金属焊盘层；
对所述至少两个半导体晶圆的每一个执行CMP工艺，以暴露所述金属焊盘层，并且平坦化所述介电层，以在所述至少两个半导体晶圆的每一个上形成接合面；
对所述至少两个半导体晶圆的每一个执行氧化工艺，以在所述金属焊盘层中形成金属氧化物；
对所述至少两个半导体晶圆的每一个执行氧化物蚀刻工艺，以去除所述金属氧化物，暴露每个所述金属焊盘层的凹陷表面；
确定每个所述金属焊盘层的所述凹陷表面满足轮廓匹配标准；
响应于所述确定，将所述至少两个半导体晶圆上的所述接合面以面对面关系对准；
将所述至少两个半导体晶圆的所述接合面物理接触；以及
随后，退火所述至少两个半导体晶圆；
其中，接合发生在所述至少两个半导体晶圆的所述介电层之间和所述金属焊盘层之间。
10.一种晶圆接合的方法，包括：
在至少两个半导体晶圆上的介电层中形成铜焊盘层；
对所述至少两个半导体晶圆的每一个的所述介电层执行CMP工艺，以暴露所述铜焊盘层，并且平坦化所述介电层，以在所述至少两个半导体晶圆的每一个上形成接合面；
对所述至少两个半导体晶圆的每一个执行氧化工艺，以在所述铜焊盘层中形成铜氧化物至预定深度；
对所述至少两个半导体晶圆的每一个执行氧化物蚀刻工艺，以去除所述铜氧化物，暴露每个所述铜焊盘层的凹陷平坦表面；
将所述至少两个半导体晶圆上的所述接合面以面对面关系对准；
将所述至少两个半导体晶圆的所述接合面物理接触；以及
热退火所述至少两个半导体晶圆；
其中，接合发生在所述至少两个半导体晶圆的所述介电层之间和所述铜焊盘层之间。
CN201310485415.8A 2013-03-15 2013-10-16 用于混合晶圆接合的方法 Active CN104051288B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201361793766P 2013-03-15 2013-03-15
US61/793,766 2013-03-15
US13/927,477 US8802538B1 (en) 2013-03-15 2013-06-26 Methods for hybrid wafer bonding
US13/927,477 2013-06-26

Publications (2)

Publication Number Publication Date
CN104051288A true CN104051288A (zh) 2014-09-17
CN104051288B CN104051288B (zh) 2017-09-08

Family

ID=51267249

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201310485415.8A Active CN104051288B (zh) 2013-03-15 2013-10-16 用于混合晶圆接合的方法

Country Status (2)

Country Link
US (1) US8802538B1 (zh)
CN (1) CN104051288B (zh)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104347349A (zh) * 2013-07-24 2015-02-11 台湾积体电路制造股份有限公司 清洗用于混合接合的衬底表面的机制
CN104979226A (zh) * 2015-06-24 2015-10-14 武汉新芯集成电路制造有限公司 一种铜的混合键合方法
CN105280509A (zh) * 2015-09-10 2016-01-27 武汉新芯集成电路制造有限公司 一种基于低熔点铜共晶金属的晶圆混合键合方法
CN107993928A (zh) * 2017-11-20 2018-05-04 长江存储科技有限责任公司 一种抑制晶圆混合键合中铜电迁移的方法
CN109786348A (zh) * 2017-11-15 2019-05-21 台湾积体电路制造股份有限公司 形成具有凹槽的金属接合件
CN112470272A (zh) * 2018-07-26 2021-03-09 伊文萨思粘合技术公司 针对混合接合的后cmp处理
CN111933533B (zh) * 2020-08-17 2021-06-04 长江存储科技有限责任公司 半导体封装结构及其制造方法
CN113035729A (zh) * 2021-03-10 2021-06-25 联合微电子中心有限责任公司 混合键合方法及键合用衬底

Families Citing this family (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
TWI540710B (zh) * 2012-06-22 2016-07-01 Sony Corp A semiconductor device, a method for manufacturing a semiconductor device, and an electronic device
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US9728453B2 (en) 2013-03-15 2017-08-08 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for hybrid wafer bonding integrated with CMOS processing
US9443796B2 (en) 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
FR3011679B1 (fr) * 2013-10-03 2017-01-27 Commissariat Energie Atomique Procede ameliore d'assemblage par collage direct entre deux elements, chaque element comprenant des portions de metal et de materiaux dielectriques
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9536848B2 (en) * 2014-10-16 2017-01-03 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
CN106876419B (zh) 2015-12-10 2019-07-30 中芯国际集成电路制造(上海)有限公司 Cmos图像传感器及其形成方法
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
US10796936B2 (en) 2016-12-22 2020-10-06 Invensas Bonding Technologies, Inc. Die tray with channels
CN117878055A (zh) 2016-12-28 2024-04-12 艾德亚半导体接合科技有限公司 堆栈基板的处理
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
KR20190092584A (ko) 2016-12-29 2019-08-07 인벤사스 본딩 테크놀로지스 인코포레이티드 집적된 수동 컴포넌트를 구비한 접합된 구조체
WO2018147940A1 (en) 2017-02-09 2018-08-16 Invensas Bonding Technologies, Inc. Bonded structures
US10629577B2 (en) 2017-03-16 2020-04-21 Invensas Corporation Direct-bonded LED arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10529634B2 (en) 2017-05-11 2020-01-07 Invensas Bonding Technologies, Inc. Probe methodology for ultrafine pitch interconnects
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10163864B1 (en) 2017-08-16 2018-12-25 Globalfoundries Inc. Vertically stacked wafers and methods of forming same
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US10658313B2 (en) 2017-12-11 2020-05-19 Invensas Bonding Technologies, Inc. Selective recess
US11011503B2 (en) 2017-12-15 2021-05-18 Invensas Bonding Technologies, Inc. Direct-bonded optoelectronic interconnect for high-density integrated photonics
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US10886249B2 (en) 2018-01-31 2021-01-05 Ams International Ag Hybrid wafer-to-wafer bonding and methods of surface preparation for wafers comprising an aluminum metalization
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US11244916B2 (en) 2018-04-11 2022-02-08 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
WO2019241367A1 (en) 2018-06-12 2019-12-19 Invensas Bonding Technologies, Inc. Interlayer connection of stacked microelectronic components
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
WO2019241417A1 (en) 2018-06-13 2019-12-19 Invensas Bonding Technologies, Inc. Tsv as pad
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US20200075533A1 (en) 2018-08-29 2020-03-05 Invensas Bonding Technologies, Inc. Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
CN113330557A (zh) 2019-01-14 2021-08-31 伊文萨思粘合技术公司 键合结构
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11393780B2 (en) 2019-07-26 2022-07-19 Sandisk Technologies Llc Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same
US11515273B2 (en) 2019-07-26 2022-11-29 Sandisk Technologies Llc Bonded assembly containing oxidation barriers, hybrid bonding, or air gap, and methods of forming the same
US11139272B2 (en) 2019-07-26 2021-10-05 Sandisk Technologies Llc Bonded assembly containing oxidation barriers and/or adhesion enhancers and methods of forming the same
US10770424B1 (en) * 2019-08-13 2020-09-08 Nanya Technology Corporation Semiconductor structure and method of manufacturing thereof
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
GB2589329B (en) * 2019-11-26 2022-02-09 Plessey Semiconductors Ltd Substrate bonding
US11610993B2 (en) 2019-12-06 2023-03-21 Tokyo Electron Limited 3D semiconductor apparatus manufactured with a plurality of substrates and method of manufacture thereof
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
WO2021133741A1 (en) 2019-12-23 2021-07-01 Invensas Bonding Technologies, Inc. Electrical redundancy for bonded structures
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
FR3110769B1 (fr) * 2020-05-19 2022-06-24 Commissariat Energie Atomique Procédé de traitement d'un circuit électronique pour un collage moléculaire hybride
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
KR20220030685A (ko) 2020-09-03 2022-03-11 삼성전자주식회사 반도체 패키지
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
KR20220033619A (ko) 2020-09-08 2022-03-17 삼성전자주식회사 반도체 패키지
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
KR20220126539A (ko) 2021-03-09 2022-09-16 삼성전자주식회사 반도체 패키지
US11876077B2 (en) * 2021-03-12 2024-01-16 Nanya Technology Corporation Semiconductor device and method of manufacturing the same
CN115602651A (zh) 2021-07-09 2023-01-13 联华电子股份有限公司（Tw） 接合半导体结构及其制作方法
US20230075263A1 (en) * 2021-09-09 2023-03-09 Tokyo Electron Limited Wafer bonding method using selective deposition and surface treatment
US20240071984A1 (en) * 2022-08-23 2024-02-29 Tokyo Electron Limited Next generation bonding layer for 3d heterogeneous integration

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080205027A1 (en) * 2007-02-22 2008-08-28 Stmicroelectronics (Crolles 2) Sas Assembly of two parts of an integrated electronic circuit
WO2012010662A2 (fr) * 2010-07-21 2012-01-26 Commissariat à l'énergie atomique et aux énergies alternatives Procede d'assemblage par collage direct entre deux elements comprenant des portions de cuivre et de materiaux dielectriques
US20120252189A1 (en) * 2011-03-31 2012-10-04 S.O.I.Tec Silicon On Insulator Technologies Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2947481B1 (fr) * 2009-07-03 2011-08-26 Commissariat Energie Atomique Procede de collage cuivre-cuivre simplifie

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080205027A1 (en) * 2007-02-22 2008-08-28 Stmicroelectronics (Crolles 2) Sas Assembly of two parts of an integrated electronic circuit
WO2012010662A2 (fr) * 2010-07-21 2012-01-26 Commissariat à l'énergie atomique et aux énergies alternatives Procede d'assemblage par collage direct entre deux elements comprenant des portions de cuivre et de materiaux dielectriques
US20120252189A1 (en) * 2011-03-31 2012-10-04 S.O.I.Tec Silicon On Insulator Technologies Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10727097B2 (en) 2013-07-24 2020-07-28 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for cleaning substrate surface for hybrid bonding
CN104347349B (zh) * 2013-07-24 2018-03-09 台湾积体电路制造股份有限公司 清洗用于混合接合的衬底表面的机制
CN104347349A (zh) * 2013-07-24 2015-02-11 台湾积体电路制造股份有限公司 清洗用于混合接合的衬底表面的机制
CN104979226A (zh) * 2015-06-24 2015-10-14 武汉新芯集成电路制造有限公司 一种铜的混合键合方法
CN105280509A (zh) * 2015-09-10 2016-01-27 武汉新芯集成电路制造有限公司 一种基于低熔点铜共晶金属的晶圆混合键合方法
US10854574B2 (en) 2017-11-15 2020-12-01 Taiwan Semiconductor Manufacturing Company, Ltd. Forming metal bonds with recesses
US10685935B2 (en) 2017-11-15 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Forming metal bonds with recesses
CN109786348A (zh) * 2017-11-15 2019-05-21 台湾积体电路制造股份有限公司 形成具有凹槽的金属接合件
CN109786348B (zh) * 2017-11-15 2021-03-16 台湾积体电路制造股份有限公司 形成具有凹槽的金属接合件
CN107993928B (zh) * 2017-11-20 2020-05-12 长江存储科技有限责任公司 一种抑制晶圆混合键合中铜电迁移的方法
CN107993928A (zh) * 2017-11-20 2018-05-04 长江存储科技有限责任公司 一种抑制晶圆混合键合中铜电迁移的方法
CN112470272A (zh) * 2018-07-26 2021-03-09 伊文萨思粘合技术公司 针对混合接合的后cmp处理
CN111933533B (zh) * 2020-08-17 2021-06-04 长江存储科技有限责任公司 半导体封装结构及其制造方法
CN113035729A (zh) * 2021-03-10 2021-06-25 联合微电子中心有限责任公司 混合键合方法及键合用衬底

Also Published As

Publication number Publication date
CN104051288B (zh) 2017-09-08
US8802538B1 (en) 2014-08-12

Similar Documents

Publication Publication Date Title
CN104051288A (zh) 用于混合晶圆接合的方法
US11694925B2 (en) Diffusion barrier collar for interconnects
US8617689B2 (en) Bonding of substrates including metal-dielectric patterns with metal raised above dielectric and structures so formed
US11244916B2 (en) Low temperature bonded structures
US20200126941A1 (en) Semiconductor device for bonding conductive layers exposed from surfaces of respective interconnection layers
US9865545B2 (en) Plurality of substrates bonded by direct bonding of copper recesses
CN107993928B (zh) 一种抑制晶圆混合键合中铜电迁移的方法
US20130020704A1 (en) Bonding surfaces for direct bonding of semiconductor structures
CN107316840B (zh) 混合接合半导体晶片的3dic结构与方法
CN105140144A (zh) 一种介质加压热退火混合键合方法
CN106711131A (zh) 半导体封装件及其形成方法
CN109390305A (zh) 一种键合晶圆及其制备方法
US20140061901A1 (en) Precise-Aligned Lock-And-Key Bonding Structures
CN105097777A (zh) 一种半导体器件及其制备方法
CN114446772A (zh) 制造键合衬底叠层的方法
CN112397394B (zh) 半导体结构及其制造方法
CN104900543A (zh) 一种半导体器件及其制备方法
US9997396B2 (en) Deep trench isolation structure and method for improved product yield
US9754911B2 (en) IC structure with angled interconnect elements
TWI835746B (zh) 用於混合接合的化學機械拋光
CN112563227B (zh) 半导体结构及其制造方法
US20240178170A1 (en) Conductive buffer layers for semiconductor die assemblies and associated systems and methods
TW201921587A (zh) 用於混合接合的化學機械拋光

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant