TW201921587A - 用於混合接合的化學機械拋光 - Google Patents

用於混合接合的化學機械拋光

Info

Publication number
TW201921587A
TW201921587A TW107133206A TW107133206A TW201921587A TW 201921587 A TW201921587 A TW 201921587A TW 107133206 A TW107133206 A TW 107133206A TW 107133206 A TW107133206 A TW 107133206A TW 201921587 A TW201921587 A TW 201921587A
Authority
TW
Taiwan
Prior art keywords
conductive structure
substrate
conductive
layer
dielectric
Prior art date
Application number
TW107133206A
Other languages
English (en)
Other versions
TWI835746B (zh
Inventor
二世 蓋烏斯 吉爾曼 方騰
肯卓瑟卡 曼達拉普
賽普里恩 艾米卡 烏佐
傑瑞米 阿弗烈德 提爾
Original Assignee
美商英帆薩斯邦德科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商英帆薩斯邦德科技有限公司 filed Critical 美商英帆薩斯邦德科技有限公司
Publication of TW201921587A publication Critical patent/TW201921587A/zh
Application granted granted Critical
Publication of TWI835746B publication Critical patent/TWI835746B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/0346—Plating
    • H01L2224/03462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/036—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/0361—Physical or chemical etching
    • H01L2224/03616—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05547—Structure comprising a core and a coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H01L2224/05557—Shape in side view comprising protrusions or indentations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06152—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry being non uniform, i.e. having a non uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0615—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H01L2224/06154—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry covering only portions of the surface to be connected
    • H01L2224/06155—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2746—Plating
    • H01L2224/27462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/276—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/2761—Physical or chemical etching
    • H01L2224/27616—Chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29186—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/3001—Structure
    • H01L2224/3003—Layer connectors having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3012—Layout
    • H01L2224/3013—Square or rectangular array
    • H01L2224/30131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/301—Disposition
    • H01L2224/3012—Layout
    • H01L2224/3015—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/305—Material
    • H01L2224/30505—Layer connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/30—Structure, shape, material or disposition of the layer connectors prior to the connecting process of a plurality of layer connectors
    • H01L2224/3051—Function
    • H01L2224/30515—Layer connectors having different functions
    • H01L2224/30517—Layer connectors having different functions including layer connectors providing primarily mechanical bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8003—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area
    • H01L2224/80035—Reshaping the bonding area in the bonding apparatus, e.g. flattening the bonding area by heating means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80345—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/8093—Reshaping
    • H01L2224/80935—Reshaping by heating means, e.g. reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80909—Post-treatment of the bonding area
    • H01L2224/80948—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/83896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83905—Combinations of bonding methods provided for in at least two different groups from H01L2224/838 - H01L2224/83904
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

技術及方法之代表性實施包括用於混合接合的化學機械拋光。所揭示之方法包括：在基板上沈積且圖案化介電層以在該介電層中形成開口，在該介電層上方且在該些開口之第一部分內沈積障壁層，及在該障壁層上方且在該些開口之未由該障壁層佔據之第二部分內沈積導電結構，該些開口之該第二部分中之該導電結構的至少一部分耦接或接觸該基板內之電路。另外，該導電結構經拋光以顯露該障壁層之沈積於該介電層上方且未沈積於該些開口之該第二部分中的部分。此外，該障壁層係藉由選擇性拋光來拋光以在該介電層上或在該介電層處顯露接合表面。

Description

用於混合接合的化學機械拋光
以下描述係關於積體電路（「IC」）之拋光。更特定言之，以下描述係關於用於IC之混合接合的機械拋光。
優先權要求及相關申請案之交叉參考
本申請案主張2018年9月17日提交之題為「用於混合接合的化學機械拋光（CHEMICAL MECHANICAL POLISHING FOR HYBRID BONDING）」之美國非臨時申請案第16/133,299號及2018年9月13日提交之題為「用於混合接合的化學機械拋光（CHEMICAL MECHANICAL POLISHING FOR HYBRID BONDING）」之美國臨時申請案第62/730,936號及2017年9月24日提交之題為「用於混合接合的化學機械拋光（CHEMICAL MECHANICAL POLISHING FOR HYBRID BONDING）」之美國臨時申請案第62/562,449號的權益，其中之每一者特此以全文引用之方式併入。
混合接合為適用於接合諸如晶粒及晶圓之微電子組件且形成電連接之技術。一種混合接合技術為可購自Xperi公司之子公司-Invensas Bonding Technologies公司（先前被稱為Ziptronix公司）的「直接接合互連（Direct Bond Interconnect）（DBI®）」（例如，參見美國專利第7,485,968號，其全部併入本文中）。一般而言，使兩種介電質（各自位於各別基板上）接合在一起以在低溫或環境溫度下形成接合，而不藉由諸如黏著劑之介入材料。
作為此接合程序之部分，或在此接合程序之後，導電結構（諸如銅墊、柱、基板通孔或凸塊）可散置於IC之介電層內。每一基板上之導電特徵可經對準以在兩個基板之間提供電界面。
用於形成接合表面以形成混合接合之習知技術可包括在基板（例如，主動半導體晶粒或其類似者）上形成絕緣層（例如，氧化物）。絕緣層可經圖案化以形成開口，且障壁層可形成於絕緣層上方及經圖案化開口內。另外，導電結構（例如Cu等等）可形成於開口中且通常亦形成於絕緣層上方。該導電結構之一部分可接著藉由化學機械平坦化（chemical-mechanical planarization；CMP）製程移除，且上覆於絕緣層之障壁層可進一步藉由CMP製程移除。以此方式，其餘導電結構及絕緣層之表面可經製備以使得導電結構可與另一基板之導電結構形成電連接，且絕緣層可與另一基板之絕緣層形成混合（亦即，機械）接合。
然而，當使用此類習知技術時，氧化物圓化及導電結構凹陷可能發生。氧化物圓化可能導致每一基板之銅元件之間的氧化物接合中出現間隙。另外，導電結構凹陷可能致使銅接合失敗。此類缺陷之原因可能歸因於在CMP製程期間此類材料經不均勻地磨損，因此影響接合表面之品質。因而，需要改良表面之平坦化及導電結構凹陷，此又會改良混合接合技術之良率及可靠性。
揭示了用於混合接合之化學機械拋光的各種具體實例及技術。具體實例包含防止或移除在晶粒上發現之介電質侵蝕（或圓化）及導電結構凹陷之存在的技術，從而產生較均一且一致的平坦接合表面。
一種方法可包括：在基板上沈積且圖案化介電層以在該介電層中形成開口，在該介電層上方且在該些開口之一部分內沈積障壁層，及在該障壁層上方且在該些開口之至少一部分內沈積導電結構，該導電結構之至少一部分耦接或接觸該基板內之電路。另外，該導電結構可經拋光以顯露該障壁層之沈積於該介電層上方且未沈積於該些開口中的部分，使得該導電結構在由該障壁層之沈積於該介電層上方且未沈積於該些開口中的該些部分界定之平面下方不會凹進多於第一預定量。此外，該障壁層係藉由選擇性拋光來拋光以在該介電層上或在該介電層處顯露接合表面，使得該介電層之鄰近於該導電結構的該表面不會圓化多於第二預定量。另外，在製備導電結構之接合表面之後，導電結構可凹進不多於第三預定量。在提供多個導電結構之情況下，其可具有相同或不同大小，且可以一或多個規則圖案配置，每一配置可具有相同或類似大小之結構及/或在鄰近結構之間具有相同或不同間距。舉例而言，導電結構可各自大於5微米，且以間距為1.2或更大之圖案配置。
在第一具體實例中，該些開口之該第二部分中之該導電結構的至少一部分耦接至或接觸該基板內之電路。另外，該方法可包括將基板之接合表面與另一基板之接合表面接合。舉例而言，在藉由在低於400℃之溫度下對接合結構退火來進行接合之後，可在該基板及另一基板之導電部分之間形成電連接。另外，可使用不藉由黏著劑之直接接合技術來接合基板之接合表面與另一基板之接合表面。此外，接合表面及導電結構可具有小於2 nm均方根（root mean square；RMS）之表面粗糙度，或在另一具體實例中具有小於1 nm RMS之表面粗糙度。另外，在一個具體實例中，介電層表面粗糙度可小於1 nm RMS。
在第二具體實例中，對導電結構拋光可包括維持均一的導電結構移除速率。另外，對導電結構拋光可由反應性液體漿料控制。
在第三具體實例中，對障壁層拋光可包括移除在開口外部之任何過多障壁層。另外，對障壁層拋光可包括同時移除導電材料之至少一部分、障壁層之至少一部分，及介電層之至少一部分。與對障壁層拋光相關聯之移除速率可控制導電結構之深度及介電層之鄰近於障壁層及/或導電結構的部分之傾斜度。
在第四具體實例中，與對障壁層拋光相關聯之選擇性可控制導電結構之深度及介電層之傾斜度。舉例而言，選擇性可為兩種不同材料之移除速率的比率。導電結構與介電層之選擇性可為導電結構之移除速率除以介電層之移除速率的比率。
在第五具體實例中，選擇性可包括修改金屬層參數，該些金屬層參數包括障壁金屬類型、障壁金屬厚度或障壁金屬之侵蝕速率中的至少一者。舉例而言，障壁金屬類型可包括與Cabot EPOCH C8902銅漿料一起使用之鈦或與Dow ACuPLANE™ LK393一起使用之鈦或鉭（或基於此類元素中之任一種的化合物）中的至少一者。選擇性可藉由修改拋光消耗品來實現，該些拋光消耗品包括拋光墊、漿料類型、流動速率、漿料稀釋度、拋光壓力或調節盤類型中之至少一者。舉例而言，拋光墊可包括SubaTM 500或DOW IC1000TM 型襯墊中之一者。另外，選擇性可包括修改拋光參數，該些拋光參數包括壓板速度、晶圓載體速度、漿料流速、向下力或襯墊調節類型中之至少一者。舉例而言，提高漿料流速可減少導電材料之凹陷，或降低漿料流速可增加導電材料之凹陷。在一個具體實例中，在對200 mm導電結構拋光之內容背景中，可應用此類漿料流速。
在第六具體實例中，一或多個接合結構可包括在一或多個接合結構之前側及後側兩者處經曝光的連續導電結構。在一個具體實例中，一或多個接合結構可包括接合基板。另外，一或多個接合結構之前側及後側兩者可經平坦化，使得對應於一或多個接合結構之前側及後側中之每一者的表面不會凹進多於預定量。
可使用方塊流程圖說明所揭示之程序中的一些，包括圖形流程圖及/或文字流程圖。描述所揭示程序的次序並不意欲被解釋為限制，且可以任何次序組合任何數目個所描述之程序區塊以實施該些程序或替代程序。另外，可在不脫離本文中所描述之主題之精神及範圍的情況下自程序刪除某些個別區塊。另外，在不脫離本文中所描述之主題的範圍之情況下，所揭示程序可在任何合適之製造或處理設備或系統，以及任一硬體、軟體、韌體或其組合中實施。
在下文使用複數個實例來更詳細地解釋實施。儘管在此處且在下文論述各種實施及實例，但其他實施及實例可藉由組合個別實施及實例之特徵及元件而來成為可能。
概述
揭示了用於混合接合之化學機械拋光（chemical mechanical polishing；CMP）的技術之各種具體實例。介電層可包括介電質侵蝕（或介電層之表面之圓化），且導電結構可包括凹陷，其皆歸因於CMP，且其皆可能負面地影響接合。所揭示之技術改良了介電層之平坦化及導電結構凹陷之控制。
在各種具體實例中，使用本文中所揭示之技術可改良用於接合技術之堆疊程序，且增加堆疊結構之可靠性及良率。使用不藉由黏著劑之表面至表面直接接合技術堆疊且接合（諸如「ZIBOND®」）及/或混合接合（諸如「直接接合互連（Direct Bond Interconnect）（DBI®）」）的晶粒可能特別受益，此等晶粒皆可購自Invensas Bonding Technologies公司（先前被稱為Ziptronix公司）、Xperi Technologies公司（例如，參見美國專利第6,864,585號及第7,485,968號，其全部併入本文中），此等晶粒可能易受介電質侵蝕及導電結構凹陷影響（其對平直度嚴格受控之界面具有高需求）。介電層之表面之平坦化可用以減少介電質侵蝕（及/或介電層之圓化）。控制導電結構凹陷可改良兩個表面緊密接合以及確保導電結構在接合界面之上恰當地接觸的能力。
在製造用於混合接合之晶圓時，可改良混合接合（包括良率及可靠性兩者）之因素包括：1）使介電層或基板之表面平坦化，及2）使導電結構凹陷之量最小化。舉例而言，可藉由在後續接合操作之前形成平坦介電質接合表面同時介電質侵蝕最小且所關注導電結構之凹陷（亦即，凹進）受控來改良混合接合。
在一個具體實例中，電鍍障壁及/或導電層可以均一方式施加。舉例而言，電鍍障壁或導電層之非均一性可比基板之邊緣排除小至多7%。另外，較佳將障壁層或導電層之非均一性限制為比基板或晶圓之邊緣排除小至多3%。
若成形之導電層具有較差均一性，則對基板拋光可能導致所關注導電結構中之凹陷缺陷過多，此係因為導電結構之一些部分中之較長拋光時間（移除過多導電結構所需）可能導致已顯露障壁層之基板之其他部分中的過度拋光。
舉例而言，若移除基板中心周圍之障壁層上方之導電結構之一部分的拋光時間為300秒，且可能需要額外120秒來移除靠近基板之周邊之其餘導電結構之一部分，則額外120秒可解釋為過度拋光時間。120秒過度拋光時間（或藉由120/300*100計算之40%過度拋光時間）可用以移除靠近基板之周邊的導電層。
以此方式，在基板之中心處或周圍（例如，其中可定位有導電結構）之凹進的第一預定量可高於在基板之周邊處或周圍之凹進的第一預定量。在一個具體實例中，第一預定量之凹進可在基板上為均一的，且在移除障壁層之前可小於60 nm。在另一具體實例中，在移除障壁層之前，第一預定量之凹進可小於40 nm。可自表面（諸如障壁層之表面、接合表面或如兩個接合表面之間的界面所界定之接合平面）量測凹進。
類似地，過度拋光障壁層或介電層可增加介電層之鄰近於障壁層之部分中的介電層之介電質侵蝕。因而，在一個具體實例中，導電結構或障壁層之過度拋光時間可小於30%之過度拋光時間。在一個具體實例中，導電結構或障壁層之過度拋光時間可小於10%之過度拋光時間。作為實例，對導電結構拋光以顯露障壁層所需之時間可為300秒以包括10%之過度拋光時間。詳言之，障壁層之過度拋光可少於10%之過度拋光時間。
在一個具體實例中，可使用拋光程序來控制導電結構中之凹進且在導電結構中形成第二預定量之凹進。另外，在具體實例中，在已自介電層之表面移除障壁層之後，介電層及在開口（或鑲嵌腔）內之導電結構以及障壁層之移除速率可極其類似。
在另一具體實例中，在1至10 nm之範圍內之導電結構凹陷可足以達成可接受的DBI接合表面。銅化學機械拋光（chemical mechanical polishing；CMP）及障壁金屬CMP可用以達成介電層之接合表面之平坦化及/或使導電結構凹陷之量最小化。舉例而言，銅CMP及障壁CMP步驟可各自藉由調整消耗品（諸如襯墊、漿料等等）及拋光參數來修改。以此方式，介電層、導電層/結構（諸如銅）之部分及障壁金屬之移除速率可經調整以滿足總CMP程序之要求，從而達成介電層之表面之平坦化及/或最佳導電結構凹陷。在一個具體實例中，在包括介電層之銅互連技術之內容背景中，可應用銅CMP及障壁金屬CMP。
如早先所描述，導電結構中之第一預定量之凹進係在對導電層拋光以曝光基板上之障壁層之後形成。類似地，導電層中之第二預定量之凹進可在自基板或介電層之表面移除障壁層之後形成。可藉由CMP方法移除障壁層，且在其他具體實例中，可藉由例如反應性離子蝕刻（reactive ion etching；RIE）法或甚至濕式蝕刻法選擇性地移除障壁層。
然而，導電結構中之第二預定量之凹進可在基板或介電層上為均一的，且可小於30 nm。此外，第二預定量之凹進可小於15 nm。第二預定量之凹進可小於第一預定量之凹進。在一個具體實例中，在使適當表面平坦化之後，可清潔且製備平坦化接合表面以供接合操作。舉例而言，接合表面製備步驟可包括將接合表面曝光至氧或氮電漿（或此兩者）。在一個具體實例中，曝光可在空氣中或在真空內進行。接合表面製備步驟可包括在導電結構中形成第三預定量之凹進。在一些應用中，在障壁移除步驟之後，可藉由保護層塗佈接合表面以用於基板單一化程序。在單一化步驟之後，可典型地藉由濕洗技術自接合表面移除保護層。保護層清潔步驟可包括將接合表面曝光至包含氧之電漿物種。此等後續程序步驟可修改所關注導電結構中之凹進，新的凹進為第三預定量之凹進。第三預定量之凹進或凹陷可在1至20 nm之範圍內，且較佳小於10 nm。在一個具體實例中，第一預定量之凹進可大於第三預定量之凹進。
介電層可包含氧化物、氮化物或矽之碳化物、鑽石、類鑽碳（diamond like carbons；DLC）、低介電常數材料、玻璃、陶瓷材料、玻璃陶瓷、聚合材料及/或其組合之一或多個層。在一個具體實例中，介電層可沈積於包括晶圓或晶粒（諸如直接或間接帶隙半導體材料）之基板上。另外或替代地，接合表面可包括形成於介電材料基板上之介電層或具有嵌入式晶粒或導電層之封裝。
在本描述之內容背景中，術語導電結構可指任何導電材料層，且導電結構凹陷可指與所關注導電結構相關聯之任何凹陷。如本文中所描述，導電層可首先形成於障壁上，繼之以產生連續或非連續導電結構之移除程序。此外，導電結構可包含諸如銅、鎳、鈷、金、錫及類似者及/或基於此類元素之任何合金的材料。
在一個具體實例中，接合結構（包括藉由介電層及導電結構分層之基板）可包括不同材料，其中基板、介電層、障壁層及/或導電結構中之每一者或任一者可包括不同熱膨脹係數或楊氏模數。因而，接合結構可包括類似或不同材料。此外，接合結構中之一者可包括以下各者中之一者：主動、被動（諸如電容器、電感器、電阻器等等）、光學（例如雷射、發光二極體等等）或機械裝置及/或諧振腔或其組合。
然而，在一個具體實例中，介電層可形成或修改為包括一或多個開口以容納在均一或不同間距處具有類似或不同尺寸或甚至非均一置放的一或多個導電結構（或襯墊）。作為實例，介電層之接合表面可包括一或多個腔或開口，導電襯墊可在該一或多個腔或開口內。導電襯墊之寬度可大於溝槽之寬度之50%。在一個具體實例中，襯墊之寬度可在2至200微米之範圍內，且一對襯墊之間距可在襯墊之寬度之1至8倍的範圍內變化。在另一具體實例中，襯墊之寬度可在5與50 um之範圍內變化，且襯墊之間距可在襯墊之寬度之1.2至5倍的範圍內變化。在一些具體實例中，所關注之襯墊或導電結構可在下方或橫向地電連接至另一導電層。
圖1處展示了微電子元件100之介電質侵蝕及導電結構凹陷的剖面圖。第一晶圓102可包括基底層103（圖中未按比例展示）（諸如半導體）以及具有表示介電質侵蝕之彎曲表面的介電層104之部分。在一個具體實例中，介電層104可為氧化物層，在此情況下介電質侵蝕亦可被稱作氧化物圓化。另外，第一晶圓102可包括具有表示導電結構凹陷之典型凹面彎曲表面的導電結構106。此外，等分接合平面之凹進108可作為介電層104之介電質侵蝕及導電結構106之導電結構凹陷的結果而產生。
圖2展示導電結構形成之程序200。如在步驟A處所展示，介電層104可包括形成於表面204上之一或多個腔202（或開口）。腔之寬度可在0.3微米至大於50微米之間變化。腔之深度可在0.3微米至大於20微米之範圍內，且可為延伸穿過基板之導電通孔之部分或延伸至該導電通孔。在一些具體實例中，腔可包含穿基板腔（thru-substrate cavity），諸如穿過基底之部分103（圖中未按比例展示）。在步驟B處，表面204可內襯有層206，諸如障壁層及/或晶種層。舉例而言，取決於腔202之深度，層206之厚度（諸如障壁層）可在1與100 nm之間變化。在一個具體實例中，障壁層206之厚度可在3與50 nm之間。另外，作為障壁層之層206可由鉭、鈦、鎳、釕、鈷及鎢或其類似者、合金或化合物及/或其衍生物構成。在一個具體實例中，層206可充當障壁且充當晶種層以用於形成導電結構106之層。
在步驟C處，導電結構106可形成於層206上方及/或層206內。在形成導電層106之後，可接著諸如藉由CMP移除材料之部分，以形成導電結構。另外，應瞭解，儘管在步驟C至E處未明確地展示層206，然而，層206可包括於導電結構106之側下方及/或直至該些側。
在步驟D及E處，展示材料之移除之效應，其可包括基板104之表面之平坦化、介電質侵蝕及導電結構凹陷。步驟D及E處之實例提供介電質侵蝕（或「圓化」）之兩個實例結果，其可使用曲率半徑與介電質侵蝕之形狀相關聯的圓之一部分模型化，以描述侵蝕之量值。舉例而言，步驟D處之介電質侵蝕可由具有較小曲率半徑208之圓表示，而步驟E處之介電質侵蝕可由具有較大曲率半徑210之圓表示。曲率半徑208及210之大小可描述介電質104與導電結構106之相交點處之圓化的陡峭度（包括方法之陡峭度），及歸因於侵蝕而在相交點處產生之間隙數。應注意，在此描述中，具有曲率半徑208或210之圓用以使介電質104與導電結構106之相交點處的侵蝕之部分（或介電質與導電結構之間的障壁）模型化，且可能未必表示介電質104之總圓化。曲率半徑208及210之大小可為關於緊密接合之潛在問題之可能性的指示符。曲率半徑愈小，介電質侵蝕愈小。因而，介電層104之介電質侵蝕（或圓化）可防止與相對表面緊密接觸。在另一方法中，經侵蝕介電層及障壁層之截距相對於介電性表面之間的角度之補充之正切為介電質侵蝕之度量（介電質侵蝕角度）。介電質侵蝕愈小，該介電質侵蝕角度之值愈小。對於不存在介電質侵蝕之理想狀況，介電質侵蝕角度之值為零，且介電質侵蝕角度之正切因此為0。可使用其他幾何描述性形容詞來描述介電質侵蝕；一般而言，介電質侵蝕角度較佳小於30度且較佳小於10或甚至1度，其中介電質侵蝕角度之正切接近0。在一個具體實例中，介電質侵蝕（介電質侵蝕角度之正切）小於5 nm/微米，且較佳小於1 nm/微米。
步驟D亦說明導電結構可與介電質104齊平或相對於介電質104以小於凹進108之量局部凹進（亦即，其中導電結構106之表面最接近介電質104之表面）。相比之下，步驟E說明導電結構相對於介電質104局部突出（亦即，其中導電結構106之表面最接近介電質104之表面），同時亦相對於接合表面以凹進108凹進。
在CMP期間移除之材料可包括導電層及結構106之部分、障壁層（諸如層206）之部分，及/或介電層104之表面之部分。在一個具體實例中，（介電質侵蝕208及/或210之）曲率半徑愈大，介電層104至另一經製備之表面之接合出現缺陷之可能性愈大。因而，較小曲率半徑或較小介電質侵蝕可指示相對接合層或表面之間出現缺陷之可能性較小。
圖3展示堆疊晶圓102及306之剖面圖300，其展示過多介電質侵蝕及導電結構凹陷。如所展示，第一晶圓102可包括基底層103（圖中未按比例展示）、展示介電質侵蝕之第一介電層302及展示導電結構凹陷之第一導電結構304。另外，第二晶圓306可包括第二介電層308及第二導電結構310。當第一晶圓102與第二晶圓306堆疊時，可在第一晶圓102與第二晶圓306之間產生間隙312。間隙312可由導電結構凹陷及/或介電質侵蝕208及210產生。在一個具體實例中，間隙312可防止第一介電層302與第二介電層308之間的緊密表面至表面接合。在一個具體實例中，在較高溫度下，可建立第一導電結構304與第二導電結構310之間的緊密接觸，但介電質308及302之接合表面之間的連續緊密的表面至表面接觸係不大可能的。
相比之下，圖4展示根據本文所描述之一或多個具體實例之具有減少之介電質侵蝕及減少之導電結構凹陷之微電子組件400的剖面圖。第一晶圓102包括基底層103（圖中未按比例展示）、具有最小介電質侵蝕之直接地或間接地在基底層103上之介電層402及具有最小導電結構凹陷或自平面或表面（諸如接合界面或平坦接合介電表面）凹進之導電結構404。作為使用本文中所揭示之技術之結果，凹進406係最小的（尤其是與前述圖式中所展示之凹進108相比）。在一個具體實例中，凹進406可能實質上不存在。舉例而言，介電層402之介電質侵蝕及導電結構404之導電結構凹陷可能不存在，從而導致凹進406不存在。在一個具體實例中，介電層402之接合表面之特徵可為實質上平坦，且導電層中之凹進較佳小於5 nm。可在低於150℃之溫度下接合具有此等類型之表面特質的基板。
在一些具體實例中，可藉由使用電鍍浴來實現形成（例如，電鍍）導電層，電鍍浴包括可用以確保無空隙填充之超填充添加劑。在其他具體實例中，可藉由各種方法之組合形成導電層，該些方法包括原子層沈積、無電電鍍、濺鍍、蒸鍍、雷射沈積及類似者。另外，可在室溫與低於250℃之間的溫度下熱處理導電層預定量之時間。在一個具體實例中，在低於100℃之溫度下熱處理導電層。導電層可形成於晶種表面（諸如層206，圖中未示）上方。另外，在一個具體實例中，可達成在介電層402之表面之上均一塗佈導電層，使得導電層之非均一性比介電層402之邊緣排除小至多7%。在另一具體實例中，導電層之非均一性可比介電層104之邊緣排除小至多3%。
另外，導電層之厚度可在0.3至200 um之範圍內。在一個具體實例中，導電層之厚度可在0.3至20 um之範圍內。導電層可形成為導電結構404，諸如雙金屬鑲嵌結構、跡線、基板通孔（through substrate via；TSV），及類似者。此外，任何非所要材料（待移除）可構成用於導電結構404之材料之不合需要部分、障壁層之不合需要部分，及/或介電層402之不合需要部分。
基於（介電層402之）介電質侵蝕之曲率半徑，介電質402之表面與導電結構404（或與鄰近層，諸如開口內之障壁）的相交點可小於導電結構404之深度之10%。在減少圓化侵蝕之實例中，導電結構404及障壁層之拋光壓力可在0.3至5 psi之間變化，且任何過度拋光時間可保持低於30%以控制導電結構凹陷及/或使介電質侵蝕（或圓化）最小化。此外，導電結構及障壁層之拋光壓力可在0.5至3 psi之間變化，且任何過度拋光時間可保持低於10%以控制導電結構凹陷及/或使介電質侵蝕最小化。
在一個具體實例中，介電層402之開口（包括導電襯墊、溝槽及/或腔）可經組態以具有均一、不同或非均一的尺寸、間距及佈局。在一個具體實例中，導電襯墊可大於溝槽之寬度之50%，溝槽亦可包括任何障壁層或其他導電或絕緣層。另外，導電襯墊之寬度可在2至200 um之範圍內，且一對襯墊之間距可在襯墊之寬度之1.1至8倍的範圍內變化。在另一具體實例中，導電襯墊之寬度可在5至40 um之範圍內，且一對襯墊之間距可在襯墊之寬度之1.2至5倍的範圍內變化。此外，第一晶圓102或晶粒之特定區內之導電結構的局部週期性可不同於第一基板102（例如，晶圓、面板或晶粒）上之導電結構之各別分組的週期性。
圖5展示根據具體實例之堆疊晶粒、晶圓或其類似者的剖面圖。堆疊組件可包含如所展示之兩個晶粒之微電子總成500，但可按給定設計之需要或要求堆疊更多晶粒。如所展示，第一基板102可包括第一基底層103、第一介電層502及第一導電結構504。另外，第二基板306可包括第二介電層506及第二導電結構508。作為使用本文中所揭示之技術之結果，介電質侵蝕510及導電結構凹陷512可減少或甚至幾乎被消除。因而，介電層502之表面可可靠地緊密接合至介電層506之表面，及/或導電結構508之表面可緊密接合至導電結構504之表面。
詳言之，第一介電層502及第二介電層506之接合表面可為平坦（如無介電質侵蝕510所展示）或接近平坦的（不影響混合接合之最小量的介電質侵蝕）。另外，第一導電結構504及第二導電結構508之表面可為平坦（如最小或不存在的導電結構凹陷512所展示）或接近平坦的（不影響混合接合之最小量的導電結構凹陷）。
在各種具體實例中，導電結構凹陷或凹進512可存在，且可較佳成預定最小量。舉例而言，可在退火或操作期間預測導電結構504及508之一些膨脹。因而，預定最小量之凹陷512或凹進可為一個或兩個導電結構504及508之膨脹提供空間，此可防止壓力，包括介電層502及506在退火期間之分層。此外，基板102及106中之至少一者上或中之至少一個導電結構可以接合形式在由經接合介電層界定之接合界面之上延伸，同時另一基板中之對應導電結構在接合之後可保持略微凹進。然而，導電結構在接合期間或之後的組合膨脹會導致結構相接觸。
另外，如圖5中所展示，堆疊晶圓可包括在經接合堆疊晶圓（包括例如第一晶圓102及第二晶圓306）之多於一個表面處曝光的導電結構。可清潔此類堆疊晶圓或基板之後表面，且在導電結構中具有預定量之凹進且典型地又具有第三預定凹進的該表面經製備以用於接合操作。在導電層中具有所需預定凹進的另一經製備之表面可接合至預接合基板102或306之經清潔及製備的後側。在一個具體實例中，可使用本發明所揭示之技術將底部基板與多個基板（2至100個）連續堆疊。在低於300℃下且在較佳低於200℃下熱處理堆疊基板在30至180分鐘之間變化之時間。可在每一接合步驟之後應用熱處理，或可在完成所有接合以同時使整個堆疊退火後應用熱處理。在一些應用中，要求較低的接合溫度可能導致熱處理時間較長，以便確保導電結構在接合界面之上接觸。在一些應用中，製備相對基板兩者之接合表面以用於接合操作，在其他狀況下，在堆疊操作之前僅製備兩個配合基板之接合表面中之一者。
如圖5中所展示，導電結構504及508中之任一者或兩者可為基板通孔（through substrate via；TSV），且此類TSV可設置於具有不延伸穿過基板之其他導電結構之基板上，該些導電結構諸如跡線、接觸墊。
在各種實施中，可使用銅拋光CMP來減少導電結構凹陷。在實施銅拋光CMP之前但在形成導電層之後，導電層之表面可具備障壁金屬（諸如發現於層206上）。此額外障壁層可藉由在開始任何CMP之前用較硬障壁層填充銅層中之凹進來進一步確保平坦度。
實例實施
以具有大體均一導電層表面（例如，圖2C）之晶圓開始，銅及障壁層CMP之特徵可在於：1. 以均一導電材料移除速率以及最小過度拋光時間對導電層執行之第一拋光步驟，其用以形成具有如自障壁層之頂部表面量測到之第一量之凹進的導電結構；2. 藉由塗覆高選擇性障壁漿料從而以最小過度拋光時間對障壁金屬拋光來執行的第二拋光步驟，其用以形成如自介電層之頂部表面或自由介電層之頂部表面界定之接合平面量測到之第二預定凹進的導電結構。介電質具有最小介電質侵蝕，使得介電質侵蝕角度小於10度且較佳小於5度。第二預定凹進亦較佳小於第一預定凹進。
在一個具體實例中，對於銅拋光，反應性液體漿料（諸如Dow ACuPLANE™ LK393銅漿料及Cabot EPOCH C8902銅漿料）可用於銅拋光。舉例而言，反應性液體漿料Cabot EPOCH C8902漿料之使用可能不利地與障壁材料（例如，TiN、TaN等等）發生反應，使得當部分地曝光底層障壁材料（例如，在晶圓102之邊緣處）時，銅拋光可能顯著減少。因此，當選擇適當導電層移除漿料時，應考慮障壁層之性質。
障壁金屬拋光步驟（諸如用於層206之障壁材料）可自晶圓（諸如晶圓102）之表面移除任何過多障壁金屬，且可用以控制銅DBI襯墊之最終凹陷值。在一個具體實例中，障壁金屬拋光可用以校正在銅拋光步驟之後存在之任何非均一性。然而，應瞭解，如上文所指示，銅拋光步驟之焦點為在基板之上形成均一或幾乎均一凹進的導電結構，同時維持障壁金屬在基板之上儘可能地均一。
障壁金屬拋光步驟可同時移除各種類型之材料以在導電結構中形成第二預定凹進，該些材料包括但不限於導電材料（諸如用於導電結構106之導電材料）、金屬障壁材料（諸如層206之障壁材料）及固體介電材料（諸如在介電層402中使用之氧化矽）。障壁金屬拋光步驟之相對移除速率可控制導電結構404之表面至介電層402之表面上的相對凹進（諸如導電結構中之第二預定凹進），及/或介電質之傾斜度（諸如介電質侵蝕角度）。
舉例而言，導電結構404之表面之凹陷改變的速率（如本文中由具有表示導電結構凹陷之彎曲表面的導電結構404所展示）及介電質侵蝕之圓化增加的速率（如本文中例如由可能導致曲率半徑較小或介電質侵蝕角度之斜率較淺的介電質侵蝕208及可能導致曲率半徑較大之介電質侵蝕210所展示）可由各別材料（諸如導電材料及/或介電材料）之選擇性控制。此類選擇性可包括兩種不同材料之移除速率之比率。舉例而言，導電材料（諸如銅）與介電材料（諸如氧化物）之選擇性可為導電材料之移除速率除以介電材料之移除速率的比率。因而，控制選擇性可能影響導電結構之表面與介電性表面的相對深度（導電結構凹陷），及傾斜度（介電質侵蝕角度）。
相對於選擇性，達成一組所要表面形貌特徵之方式可為調整選擇性，使得該組所要特徵皆可在某一拋光時間間隔內達成。舉例而言，此同時最佳化可包括建構使用不同選擇率之所關注特徵（諸如，導電結構凹陷（或凹進）及介電質侵蝕（或圓化））之時間演進曲線圖。此曲線圖可用以判定所應用之程序是否在單一時間間隔內達成所要效能。此曲線圖可允許對資料進行可視映射，使得（效能之）進程及缺陷可易於看出，且可進行關於應如何修改選擇性（以達成所要結果）之判定。
可關於選擇性修改之參數可包括晶圓之金屬層參數、拋光消耗品及/或拋光參數。可自訂之障壁金屬層參數（諸如金屬氮化物）包括障壁金屬類型、障壁金屬厚度，及/或障壁金屬之侵蝕速率（例如在銅拋光期間）。可調整之拋光（使用CMP）消耗品包括拋光墊、漿料類型（拋光漿料、漿料混合物）、漿料流動速率、漿料稀釋度及/或調節盤類型。可調整之拋光參數（諸如主要CMP工具參數）包括壓板速度、晶圓載體速度、漿料流速、施加至晶圓之向下力，及/或襯墊調節參數。在各種具體實例中，可調整金屬層參數、拋光消耗品及/或拋光參數以得到所要結果，包括最小化或消除介電質侵蝕及導電結構凹陷。
金屬層參數
在一個具體實例中，障壁金屬之類型可能影響障壁金屬與銅拋光之選擇性。舉例而言，鈦（Ti）可能對於Cabot EPOCH C8902銅漿料不具有良好選擇性，而鉭（Ta）可能對於Cabot EPOCH C8902銅漿料具有良好選擇性。另外，Dow ACuPLANE™ LK393漿料可能對於Ti、Ta及作為障壁材料之其氮化物具有良好選擇性。選擇對於銅拋光具有良好選擇性之障壁金屬可有助於防止過多障壁金屬侵蝕、不可恢復之導電結構凹陷，及介電質侵蝕。
另外，障壁金屬之厚度可用以減少最終導電結構凹陷。舉例而言，若銅拋光程序導致導電結構凹陷（第一預定凹進）之層級較高，則可使障壁層較厚以幫助容納額外凹陷而不會增加最終結構之顯著介電質侵蝕。在一個實例中，對於間距為10 um之3至5 um直徑通孔且基於Ti之障壁金屬之厚度至多為80 nm的DBI圖案，可實現此情形。在銅拋光步驟之後，導電結構中之第一預定凹進為30至50 nm，較厚Ti障壁在與Dow LK393障壁漿料組合使用時可產生合適DBI表面。另外，當銅拋光凹陷（第一預定凹進）為10至20 nm時，可使用較薄25nm Ta障壁來達成有利結果。
拋光CMP消耗品
在CMP程序期間，可使用一或多個襯墊或子襯墊（subpad）。此類一或多個子襯墊可比主要拋光墊更軟，且在拋光操作期間，可藉由研磨材料連續地再調節拋光之表面以刷新拋光表面，從而防止拋光表面上釉。在一個具體實例中，可使用具有子襯墊之拋光墊對導電結構拋光。因而，為了減少經拋光導電結構（諸如導電結構406）中之缺陷，障壁層拋光墊可比用於導電結構之拋光墊更硬。
為了達成較大平坦化，較硬CMP襯墊可改良平坦化基板之能力。舉例而言，可使用SubaTM 500型襯墊來進行障壁拋光。另外，亦可使用DOW IC1000TM 型襯墊對多種DBI圖案拋光，包括寬度自小於0.2至超過200微米變化且間距在0.5至8之間變化之導電結構。
在一個具體實例中，為了控制導電結構404及障壁層206中之凹陷之預定量，可使用較硬CMP襯墊對導電結構404及障壁層206兩者拋光。襯墊之硬度計硬度可在肖氏D標尺45與90之間的範圍內。在一個具體實例中，硬度計硬度可大於49。
然而，可使用拋光漿料及漿料混合物來改良平坦化。舉例而言，各種材料之移除速率可能受障壁漿料類型及混合物影響。藉由水或其他化學品稀釋拋光漿料例如可降低介電材料及障壁金屬拋光速率，同時使銅移除速率相對較高。因而，此稀釋可適用於控制導電結構凹陷，諸如在導電結構404之表面在介電層402之表面上方突出時（參見圖6之實例）。
另外，可藉由減少經添加至漿料之氧化劑（諸如過氧化氫（H2O2））之量來控制銅移除速率。舉例而言，當使用Dow ACuPLANE™ LK393障壁漿料時，可藉由減少經添加至漿料之H2O2來降低銅移除速率而不實質上降低介電層移除速率或障壁金屬移除速率。在一個具體實例中，導電結構移除速率之降低可降低多達五（5）倍，而不實質上降低介電層移除速率或障壁金屬速率。此外，在拋光程序期間，可將與漿料類型相容之調節盤施加至拋光墊之表面，以維持導電層及障壁層之可預測均一移除速率。
拋光參數
關於調整壓板速度，較低速度可自降低之銅移除速率增加突出。並且，襯墊之較高速度可致使拋光期間之加熱較多，從而提高導電材料移除速率。介電層402及障壁材料206之移除速率可隨著工作台速度變高而提高。因而，晶圓載體速度可設定成比工作台速度慢6至10轉/分鐘（revolution per minute；RPM）。
可另外使用漿料流速來控制移除速率。舉例而言，可使用低漿料流速來降低氧化物拋光速率，同時維持導電材料移除速率。舉例而言，可使用Dow ACuPLANE™ LK393漿料之40 ml/min流速對間距為直徑2倍之1至5 um直徑銅特徵之DBI表面拋光。在一個具體實例中，壓印SubaTM 500襯墊上之Dow ACuPLANE™ LK393漿料之40 ml/min流速可達到3至10 nm之穩態導電結構凹陷。亦可達成凹陷與漿料流速之相反關係。舉例而言，提高漿料流速可減少導電結構凹陷，且降低漿料流速可增加導電結構凹陷。
關於施加至晶圓之向下力，當使用LK393漿料時，所有材料之移除速率隨著向下力增加而提高。在一個具體實例中，當已移除銅主體層時，向下力可能影響導電結構凹陷。舉例而言，較大向下力可增加導電結構凹陷（第一預定凹進），此有可能係由與較大向下力相關聯之加熱增加造成。另外，可使用晶圓之水漂效應來控制導電結構凹陷之量。
額外實例具體實例
圖6展示根據具體實例之晶圓102之層的剖面圖600。如所展示，晶圓102包括基板層602、介電層604、障壁層606及導電結構608。應瞭解，基板層602可同樣存在於前述圖式中之任一者上。舉例而言，介電層104、302、308、402、502及506可各自沈積於個別基板（諸如基板層602）或基板之層合物上。
在各種具體實例中，基板602及介電層604可由具有類似熱膨脹係數（coefficient of thermal expansion；CTE）之類似材料構成，而在其他具體實例中，基板602及介電層604可由不同材料構成。另外，導電結構608之CTE可高於介電層604之CTE。舉例而言，導電結構608之CTE可比介電層604之CTE大十（10）倍。
在一個具體實例中，介電層604可沈積於基板層602上且經圖案化以形成開口610。當然，應瞭解，可形成任何數目個開口（包括例如開口610）。此類開口可進一步具有多種寬度、長度、深度及對應間距。另外，障壁層606可沈積於介電層604上及開口610內。在一些具體實例中，可藉由原子層沈積、電漿濺鍍及/或化學氣相沈積來塗佈障壁層606。此外，導電結構608可沈積於障壁層606上方及開口610內，如上文（例如，在圖2中）所描述。在一個具體實例中，導電結構608可直接耦接至介電層604及/或基板層602內之電路或導電結構（圖中未示）或與該電路或導電結構接觸。
如所展示，在障壁層606及/或導電層608之沈積之後，障壁層606及導電層608兩者可包括不均勻表面。在一個具體實例中，介電層604亦可包括彎曲或不均勻表面。可使用後續拋光步驟（如本文中所揭示）使障壁層606之部分及導電層608之部分平坦化以形成導電結構。另外，導電結構608可包括凹陷及/或突出部，該凹陷及/或突出部亦可使用額外或替代拋光步驟（如本文中所揭示）糾正。此外，導電結構可在介電質之接近於導電結構的一部分上方突出，同時仍相對於接合表面/平面凹進。
圖7展示根據具體實例之用於化學機械拋光的實例程序700。在程序中，可調整程序變數（諸如金屬層參數、拋光消耗品及拋光參數）中之一或多者以達成所要結果（例如，使介電質侵蝕最小化及使導電結構凹陷最小化）。將對關於三個區塊（A、B及C）所論述之程序變數的調整論述三個區塊。一般而言，可能需要平衡影響導電結構凹陷之程序參數與影響介電質侵蝕（「圓化」）之程序變數。
舉例而言，用於導電結構凹進之驅動因素包括介電質702（例如，氧化物）及障壁層704（例如，氮化物等等）之相對拋光速率（每單位時間之材料移除速率）與導電結構708（例如，銅）之拋光速率；及拋光時間（其判定以給定拋光速率移除之材料之量）。應注意，拋光速率不同於每種材料之主體移除速率。若相應地調整程序參數，則介電質702、障壁層704及導電結構708之拋光材料移除速率可最終達成穩態，且凹進層級在拋光時間內變得恆定（相對於介電質702之上表面維持相對凹進）。
舉例而言，在區塊A步驟1處，可將障壁層704沈積於介電層702上，且可將導電層706沈積於障壁層704上。在一個具體實例中，介電層702可類似於介電層104，且導電層706可類似於導電結構106。此外，在導電層706之平坦化期間，介電層702及導電層706可發現於中間結構（例如晶圓、互連件結構等等）上。
參考區塊A，在步驟2處，可移除導電層706之一部分以產生導電結構708。在一個具體實例中，移除導電層706之一部分可顯露障壁層704以在層608上方形成第一預定凹進。區塊A之步驟2包括對障壁層704拋光，使得可達成穩態材料移除速率，其中導電結構708之凹進僅維持在介電質702之上表面下方以相對於介電質702之平坦化接合表面形成第二預定凹進。
在實施中，為了達成此穩態材料移除（亦即，拋光移除速率且並非主體材料移除速率），介電層702及導電層706之材料移除速率（以產生導電結構708）經調整以儘可能地類似於障壁層704之移除速率。此包含調整程序參數及消耗品中之一或多者以達成微妙平衡，從而在整個拋光過程中產生寬的程序窗且導致導電結構708中之凹進自我調節。在一個具體實例中，在拋光期間，導電結構708之凹進（第一預定凹進）可保持在障壁層704之表面下方少於30 nm。
在區塊A步驟3處，在完成對介電質702、障壁層704及導電結構708拋光（藉由使用CMP）之後，導電結構708之凹進（第二預定凹進）可小於10 nm。另外，導電結構708之凹進（第二預定凹進）可為障壁層704之厚度的一部分。在較薄障壁層704之具體實例中，在障壁層704之厚度可在3至25 nm之間變化的情況下，第二凹進可與障壁層在障壁移除步驟之後的厚度相當。此外，介電質侵蝕710可為最小的。
在區塊B步驟1處，介電層702、障壁層704及導電層706之結構可採用類似於區塊A步驟1之方式，如本文中所描述。在區塊B步驟2處，移除導電層706之一部分（至多障壁層704之表面）以產生導電結構712。在一個具體實例中，基於導電層706材料之過度移除，導電結構712之凹進（第一預定凹進）可在障壁層704之表面下方40至50 nm。
在區塊B步驟3處，在完成對介電質702、障壁層704及導電結構708拋光（藉由使用CMP）之後，導電結構712之凹進（第二預定凹進）可小於20 nm。另外，介電質侵蝕714可較明顯（相比於介電質侵蝕710）。因此，判定導電結構712之初始凹進的程序參數可能對導電結構712之最終凹進有影響。
在區塊C步驟1處，介電層702、障壁層704及導電層706之結構可採用類似於區塊A步驟1之方式，如本文中所描述。在區塊C步驟2處，移除導電層706之一部分（至多障壁層704之表面）以產生導電結構716。在一個具體實例中，基於導電層706材料之過度移除，導電結構716之凹進（第一預定凹進）可在障壁層704之表面下方多於60 nm。
在區塊C步驟3處，在完成對介電質702、障壁層704及導電結構708拋光（藉由使用CMP）之後，導電結構716之凹進（第二預定凹進）可大於30 nm，但大於導電結構712之凹進（第二預定凹進）。另外，介電質侵蝕718可較明顯（相比於介電質侵蝕714）。因此，判定導電結構716之初始凹進的程序參數可能對導電結構716之最終凹進有影響。區塊C步驟3亦說明導電結構可在介電質及障壁層之局部表面上方突出，但仍相對於較大接合表面齊平或凹進。當多個接觸結構彼此緊密接近置放時，可能存在可低於整體接合平面且高於或低於接觸結構之二次表面。
在各種具體實例中，可能有益的是在移除障壁層704之所要部分之前使導電結構708、712、716之凹進（第一預定凹進）最小化。另外，為了使凹進（諸如導電結構708中所展示）減少低於10 nm，用於移除障壁層704之程序步驟（例如，化學反應等等）可選擇為對用於導電層706之材料（例如，銅）具有良好選擇性。並且，基於所使用之程序元件，若在障壁層704移除之前導電結構（諸如導電結構708）之凹進較少（例如，低於10 nm），則介電質侵蝕（諸如介電質侵蝕710）亦可為最小的。
相比之下，若在移除障壁層704之表面（如導電結構716中所展示）之前導電結構712、716之凹進較大（例如大於60 nm），則介電質侵蝕（諸如介電質侵蝕718）可較顯著地增加。
另外，介電質侵蝕可與障壁層（諸如障壁層704）之厚度有關。舉例而言，若障壁層為約75 nm厚，且若導電結構之凹進（第一預定凹進）為約75 nm，則在移除障壁層之後，介電質侵蝕可為最小的。相比之下，若障壁層為約40 nm厚，且若導電結構之凹進（第一預定凹進）為約75 nm，則在移除障壁層之後，介電質侵蝕可較顯著地增加。
在具體實例中，對障壁層704拋光可用以控制導電結構（諸如導電結構708）之凹進。舉例而言，如所論述，可用以控制導電結構708之凹進的一或多個因素包括介電層（諸如介電層702）之拋光速率、障壁層（諸如障壁層704）之拋光速率、導電結構（諸如導電結構708）之拋光速率及拋光時間。介電層、障壁層及導電結構之拋光速率可經組態成使得可達成每一者之穩態移除。應瞭解，在移除導電層706之一部分之前將不進行介電層702之拋光。（如區塊A、B及C之步驟2中所展示）。在穩態程序中，導電結構708之凹進可在程序時間內保持恆定。
另外，在另一具體實例中，可使用拋光壓力來控制凹陷及介電質侵蝕（諸如介電性表面之圓化，諸如介電質侵蝕710、714及/或718）。所施加之拋光壓力愈高，導電層706、障壁層704及介電層702之移除速率愈高。因此，較高拋光壓力在導電層中產生較高凹陷且在介電層中產生較高侵蝕。類似地，較低壓力產生相反效果，且伴隨產出率較低之損失。在一個具體實例中，可對所施加壓力分級。舉例而言，導電層之起始壓力可為在適當時間量內4 psi。接著，中間拋光壓力可為在適當時間量內2.5 psi。用以移除障壁層之表面上方之導電層的最終拋光壓力可在2至1.5 psi之間變化且在障壁表面上停止。類似地，可對用於移除障壁層之拋光壓力分級。作為實例，障壁層移除壓力可在2.5至0.5 psi之間變化。初始起始壓力可為2 psi，且在障壁步驟結束時，拋光壓力可為0.7 psi。分級壓力法之一個優點為，在障壁層下方之介電層曝光於較低壓力，此往往有利於降低導電層之凹陷，且極低而不存在介電質侵蝕角度。在一個具體實例中，拋光程序可包括某一壓力下之穩態移除程序，其中導電結構、障壁層及介電層之移除速率大致相同。在此方法中，在對導電結構拋光之後的第一預定凹進類似於第二預定凹進。可藉由其他額外步驟修改第二預定凹進以形成第三預定凹進，該些步驟例如藉由用經稀釋漿料進一步對該結構拋光、濕洗程序或者含氧或含氮電漿。在一些應用中，可製備且緊密接合具有包含第二預定凹進之接合表面的基板。而在其他具體實例中，具有包含第二預定凹進之接合表面的基板可直接接合至包含具有第三預定凹進之經製備之表面的另一基板。
圖8A至圖8D展示根據具體實例之各種實例導電襯墊800佈局，其判定晶粒或晶圓之表面上的襯墊金屬密度。
舉例而言，在圖8A處，在如以襯墊陣列說明之導電襯墊800配置之情況下，金屬密度相對於介電質為約20%。舉例而言，具有陣列之襯墊大小臨界尺寸（critical dimension;CD）802（表示每一導電襯墊800之直徑）可小於20 um。間距804（或襯墊間隔）等於CD 802之長度的約兩倍。
在圖8B處，在具有如所說明之配置之導電襯墊800配置之實例的情況下，襯墊金屬密度相對於介電質為約7%。CD 802亦可小於20 um，但間距804等於CD 802之長度的約四倍。換言之，此襯墊陣列中之襯墊金屬密度由於襯墊間隔804增加至圖8A處之先前狀況的兩倍而受顯著影響（例如，減少65%）。
在圖8C處，在如所說明之導電襯墊800配置之情況下，金屬密度相對於介電質為約13%。CD 802保持約20 um，然而，間距804等於CD 802之長度的約2.8倍。換言之，在圖8C之中間配置之情況下，此襯墊陣列中之襯墊金屬密度由於襯墊間隔804增加至圖8A處之先前狀況之間隔的1.4倍而仍受顯著影響（例如，減少35%）。在一些其他應用中，陣列或襯墊內之襯墊之寬度可在2至50微米之範圍內變化，且該陣列內之襯墊之間距可在1.2至8之間變化。並且，具有不同襯墊組態之襯墊陣列可以週期性或非週期性圖案彼此隔離，或聚集以形成聚集襯墊陣列。舉例而言，聚集襯墊陣列可包含：第一襯墊陣列，其包含具有第一間距之襯墊；及第二襯墊陣列，其具有第二間距；及第三襯墊陣列，其包含具有第三間距之襯墊。第一襯墊陣列之間距可小於第二襯墊陣列之間距。在一個具體實例中，第一襯墊陣列中之襯墊之大小大於聚集陣列中第二襯墊陣列中之襯墊之大小。在各種實施中，在晶粒或晶圓之表面上之金屬密度不同的情況下，本發明之方法對晶粒內及基板之表面之上的襯墊密度或襯墊大小之局部或遠側變化較不敏感。拋光方法可應用於含有具不同金屬圖案密度、不同寬度（在合理限度內）及不同深度之金屬襯墊及溝槽的基板，以產生在各種導電結構內具有最小介電質侵蝕及適當凹進的平坦介電性表面。在一個具體實例中，各種襯墊及溝槽包含機械襯墊及溝槽，其經組態以增強除電屬性之外的基板屬性，例如以改良介電層之熱傳遞能力或提供微機電系統（microelectromechanical system；MEMS）及類似者。
在圖8D處，說明了導電襯墊800之實例配置。在此實例中，襯墊880之兩個配置各自具有不同襯墊大小及不同間距。此外，配置可分離大於兩個配置之間距中之任一者的距離。當然，此等者僅為實例配置及佈局。在至少一個其他實例中，較大襯墊之配置相比於較小襯墊之配置可具有較大間距。另外，其他配置及/或非均一配置之接觸可經提供及/或添加至此等配置。
在實施中，襯墊800配置或佈局（例如，圖案、分組等等）亦可用於使介電質侵蝕及導電結構凹進最小化。在使用習知CMP方法之傳統常見配置中，可使用跨越整個晶圓902之規則圖案（相同特徵大小及大體均一配置）作為控制介電質侵蝕及凹陷之方法，將襯墊800形成且配置於晶粒或晶圓表面上。傳統金屬CMP方法往往會產生凹進，凹進隨著經拋光導電結構之寬度增加而增加。舉例而言，在障壁移除步驟之後，可在5微米寬的導電結構中量測到約15 nm之凹進，且在15微米導電結構中量測到約28 nm之凹進。類似地，大於20微米之導電結構可展現大於35 nm之凹進。習知晶粒之上的凹進中之此等較大變化意指較小導電結構中之導電金屬將必須膨脹至少15 nm，而較大導電結構將必須膨脹至少35 nm以與相對的接合表面緊密配合。晶粒之上的此等較大變化之含義為，將需要較高溫度熱處理程序（例如。320℃）以實現各種接觸導電結構中之充分機械及電耦接以及良好基板接合。相比之下，根據本文中所描述之新穎結構及方法，可使用各種襯墊佈局、配置或圖案將襯墊800形成且配置於晶粒或晶圓表面上，該些圖案可為規則的、不規則的、循環的、準隨機的，或其類似者。在障壁拋光步驟之後，此等配置中之接觸結構之變化可小於10 nm，且較佳小於6 nm。立即實務含義為可在較低溫度（典型地低於250℃且較佳低於200℃）下形成緊密良好接合。
舉例而言，圖9展示根據各種具體實例之基於實例圖案的一些實例襯墊佈局。配置906、908及910展示在由本發明所揭示之技術實現之晶粒或晶圓之上使用的圖案之設計之靈活性的實例。單一設計內之襯墊大小及佈局之此類變化對電路設計者具有吸引力，此係因為其減少或消除對達成必要平坦度所另外需要之虛擬襯墊的需求。與均一佈局之此差異係合乎需要的，因為歸因於潛在耦接損耗，未連接金屬（例如虛擬襯墊）不需要高於信號線。本發明技術允許設計者使佈局更具靈活性以避免此不合需要之情形。
本文中所描述之技術的其他優點包括金屬層減少且與堆疊相關聯之成本降低。舉例而言，組合能夠控制品質接合表面之平坦度及介電質侵蝕的TSV結構允許接合界面之上晶圓或晶粒TSV至TSV、TSV至襯墊及/或襯墊至襯墊連接的堆疊。因而，可達成第二電路晶粒或晶圓之前側上的互連，而無需在TSV之頂部上進行金屬層沈積。此可致使用於諸如記憶體陣列之複雜堆疊結構的處理得以簡化。為了控制所有襯墊800之上的凹陷，可按需要對晶粒或晶圓之表面之一或多個特定區使用第一圖案，且對一或多個其他區使用其他圖案。
如圖9所展示之A，襯墊800之分組可具有多種配置中之任一者，包括但不限於所展示之彼等者。在A處，說明了第一實例圖案906。在B處，展示了具有不同配置或分組之另一實例圖案908。在C處，第三實例圖案910展示為具有替代配置。應瞭解，可使用實例晶圓902之襯墊800之任何類型的圖案或配置，而無不利的介電質侵蝕及導電結構凹進。此等及其他圖案可分別使用或在單一晶粒或設計內組合至襯墊800之任何佈局，其中在襯墊800之後續分組中，一個圖案或配置可後接不同圖案或配置。此類圖案配置准許適應記憶體、邏輯或其他電主動或被動組件及系統之設計。
在一個具體實例中，導電結構608之凹陷可能在一些或所有襯墊800之上發生，其基於襯墊800之大小或基於襯墊800之間距或配置而具有不同嚴重性，其中所有襯墊800之間的特徵大小一致。因此，在各種具體實例中，在維持其他程序元件相同時，藉由調整襯墊（800）大小、間距及/或配置（分組、圖案等等）來實現對介電質侵蝕及導電結構凹進之控制（包括使介電質侵蝕及導電結構凹進減少或最小化）。
圖10A及圖10B展示根據具體實例之基於襯墊調節參數的實例表面平坦化結果1000。襯墊調節參數可能影響拋光速率，且又可能影響最終介電質侵蝕（諸如介電層之圓化）及導電結構凹陷。舉例而言，當使用不藉由有意調節之DOW IC1000TM 型襯墊時，導電結構、障壁金屬及介電層之導電材料之拋光速率可在不使用具有調節盤之襯墊之有意調節的情況下維持高於複數個晶圓。此程序可用於多種DBI圖案，包括20 um間距之10 um直徑DBI襯墊，以及具有5至15 um寬密封環銅線之密封環晶圓。在一個具體實例中，對經圖案化金屬障壁晶圓拋光可藉由自然調節襯墊來輔助。另外，DBI晶圓障壁層之規則拋光可使DOW IC1000TM 襯墊條件處於DBI凹陷之理想狀態。
如藉由結果1000所展示，低導電結構凹陷可藉由具有20 um間距之10 um直徑襯墊800來表明。如上文所描述，在一些實例中，複數個互連襯墊800（例如，包含導電結構（諸如導電結構608））之間距可為導電襯墊800之寬度的兩倍。另外，導電結構可包括襯墊800、溝槽、跡線及/或穿過基板之互連件。
作為實例，晶圓1002可包括直徑為10 um且間距為20 um之複數個襯墊800。樣本線1004表示在障壁層移除程序之後晶圓1002的橫截面，其用以評估襯墊800之凹陷及介電質104之圓化。舉例而言，剖面線1006展示襯墊800及介電質104在橫截面樣本線1004處之剖面。另外，表1008展示在游標之位置處沿樣本線1004之剖面高度的瞬時變化。
實例拋光公式及參數
在各種具體實例中，可使用與本文中給定之揭示內容一致的多種配方。舉例而言，用於達成可接受DBI接合表面之第一配方可包括使用具有以下約束條件之減少的漿料：1）具有ViPR載體之工具IPEC 472；2）工作台速度63；3）晶圓載體速度57；4）襯墊SubaTM 500 EMB壓印襯墊；5）無有意襯墊調節；6）向下力1.5；7）漿料流速40 ml/min；及8）Dow ACuPLANE™ LK393漿料與經添加至每公升漿料之約13 ml之H2O2混合。以此方式，與低向下力及SubaTM 襯墊組合的40 ml/min之低漿料流速可幫助達成（CMP之最終步驟之）DBI為5 um且低於1至10 nm的穩態導電結構凹陷值。
用於達成可接受DBI接合表面之第二配方可包括使用具有以下約束條件之經稀釋漿料流：1）具有輪廓頭部之工具AMA TMirra® MESA；2）工作台速度113；3）晶圓載體速度107；4）襯墊SubaTM 500 GEL XY有槽襯墊；5）無有意襯墊調節；6）向下力2 psi；7）漿料流速150 ml/min；及8）Dow ACuPLANE™ LK393 1公升，與2.75升水，與15 ml之H2O2。在一個具體實例中，此經稀釋漿料流可極佳地作用於5至10 um直徑晶圓，其中在以正常漿料流速進行正常障壁拋光之後，此類晶圓具有突出的銅及低的初始導電結構凹陷。以此方式，與較高工作台及載體速度以及XY切割襯墊組合的經稀釋漿料可幫助達成約2至3 nm之恆定導電結構凹陷（第二預定凹進）。另外，在使用此配方之情況下，較長拋光時間可能導致鄰近於銅襯墊之介電質侵蝕（諸如介電層之角圓化）增加。
用於達成可接受DBI表面之第三配方可包括使用具有以下約束條件之減少的H202：1）具有鈦載體之工具IPEC 472；2）工作台速度63；3）晶圓載體速度57；4）襯墊SubaTM 500 EMB壓印襯墊；5）襯墊調節，原位5次掃描每分鐘，6 psi，3M調節盤；6）向下力1.5；7）漿料流速40 ml/min；及8）Dow ACuPLANE™ LK393 5升，H2O2 13 ml。以此方式，減少之H2O2可幫助恢復在對導電結構拋光（使用CMP）之後可能已預先凹陷之導電材料（諸如銅）。
用於達成可接受DBI表面之第四配方可包括使用具有以下約束條件之調節：1）具有VipR載體之工具Strasbaugh 6EC；2）工作台速度63；3）晶圓載體速度57；4）IC 1000；5）襯墊調節-無有意調節；6）向下力3；7）漿料流速150 ml/min；及8）Dow ACuPLANE™ LK393漿料每公升混合13 ml H2O2。以此方式，調節可幫助達成多種金屬形狀及大小的一致平坦化。
圖11為說明根據具體實例之用於拋光層以供混合接合之實例程序的流程圖1100。在1102處，程序包括在基板（諸如基板層602）上沈積且圖案化介電層（諸如介電層604）以在介電層中形成開口（諸如開口610）。另外，在1104處，程序包括在介電層上方且在開口之第一部分內沈積障壁層（諸如障壁層606）。在1106處，程序包括在障壁層上方且在開口之未由障壁層佔據之第二部分內沈積導電結構（諸如導電結構608），開口之第二部分中之導電結構之至少一部分耦接至或接觸電路或一或多個導電結構。沈積導電結構之方法可包括在沈積導電結構之前，在障壁層上方沈積晶種層。在一個具體實例中，開口中之導電結構之至少一部分可耦接至或可接觸基板內之電路。另外，程序可包括製備第一平坦接合表面以用於接合操作，及將第一平坦接合表面與第二平坦接合表面接合。舉例而言，在藉由在低於400℃之溫度下對接合結構退火來進行接合之後，可在導電結構（諸如導電結構608）與另一導電結構之間形成電連接。在一個具體實例中，可在低於350℃之溫度下對接合結構退火。
此外，任何數目個晶圓可藉由本文中所揭示之程序製備，且接著經堆疊。舉例而言，第一晶圓及第二晶圓（諸如第一晶圓102及/或第二晶圓306）可經製備且發現為平坦的，且可因此堆疊（例如，第一晶圓102之接合表面可接合至第二晶圓306之接合表面）。任何數目個額外晶圓可堆疊於經堆疊第一晶圓及第二晶圓（諸如第一晶圓102及/或第二晶圓306）之頂部上或在經堆疊第一晶圓及第二晶圓下方（且接合至經堆疊第一晶圓及第二晶圓）。在一個具體實例中，接合表面製備步驟可包括清潔第一晶圓及第二晶圓兩者之接合表面且將第一晶圓及/或第二晶圓之經清潔表面曝光至氮或鹵化物電漿。此外，經接合晶圓（諸如第一介電層502及/或第二介電層506之經接合晶圓）之第二表面（亦即，未接合表面）可在製備中經平坦化以供後續接合。
另外，可使用不藉由黏著劑之直接接合技術、使用金屬至金屬擴散接合或此兩者（例如，混合接合）來接合基板之接合表面與另一基板之接合表面。此外，接合表面及導電結構可具有小於1 nm均方根（root mean square；RMS）之組合表面粗糙度。
在一個具體實例中，任兩個鄰近經接合晶圓（諸如在第一晶圓102與第二晶圓306之間）之CTE可為不同的。舉例而言，第一介電層之材料之CTE可比第二介電層之材料之CTE高兩（2）倍。另外，介電層之寬度可為不同的。舉例而言，在一個具體實例中，第二晶圓306可包括其中已形成接合表面之分段基板或晶粒，且經製備的接合表面可緊密接合至另一晶圓（諸如第一晶圓102）之經製備的表面。另外，經接合晶粒之後表面可經平坦化，使得可清潔且製備經平坦化後表面以供後續額外接合。以此方式，可形成多個晶粒堆疊。
在1108處，程序包括對導電結構拋光以顯露障壁層之沈積於介電層上方且未沈積於開口之第二部分中的部分，使得導電結構在由障壁層之沈積於介電層上方且未沈積於開口之第二部分中的部分界定之平面下方不會凹進（或凹陷）多於10 nm。
在1110處，程序包括藉由選擇性拋光對障壁層拋光以在介電層上或在介電層處顯露接合表面，而不使得介電層之鄰近於開口之第二部分中之導電結構的表面圓化。
應瞭解，流程圖1100可在前述圖式中之任一者之內容背景中操作。舉例而言，以減少導電結構凹陷之方式對導電結構拋光及/或以減少介電質侵蝕之方式對障壁層拋光可使用圖7之程序（諸如藉由修改介電層702及導電結構706之拋光速率來達成穩態）、圖8之襯墊佈局（其可考慮金屬密度、襯墊之CD及襯墊之間的間距）及圖9之襯墊佈局（其可採用為襯墊佈局之圖案）中之一或多者。以此方式，圖11之方法可應用於前述圖式中之任一者之內容背景中。
如本文中所揭示，對導電結構拋光可包括維持均一的導電結構移除速率。另外，對導電結構拋光可由反應性液體漿料控制。對障壁層拋光可包括移除任何過多障壁層，且可包括同時移除導電材料之至少一部分、障壁層之至少一部分及介電層之至少一部分。此外，與對障壁層拋光相關聯之移除速率可控制導電結構之深度及介電層之傾斜度。
與對障壁層拋光相關聯之選擇性可控制導電結構之深度及介電層之傾斜度。舉例而言，選擇性可為兩種不同材料之移除率之比率。導電結構與介電層之選擇性可為導電結構（諸如銅）之移除速率除以介電層（諸如氧化物）之移除速率的比率。
選擇性亦可包括修改金屬層參數，該些金屬層參數包括障壁金屬類型、障壁金屬厚度或障壁金屬之侵蝕速率中的至少一者。舉例而言，障壁金屬類型可包括與Cabot EPOCH C8902銅漿料一起使用之鈦或與Dow ACuPLANE™ LK393漿料一起使用之鈦或鉭中的至少一者。選擇性可包括修改拋光消耗品，該些拋光消耗品包括拋光墊、漿料類型、漿料流動速率、漿料稀釋度、拋光壓力或調節盤類型中之至少一者。拋光墊可包括SubaTM 500或DOW IC1000TM 型襯墊中之一者。另外，選擇性可包括修改拋光參數，該些拋光參數包括壓板速度、晶圓載體速度、漿料流速、向下力或襯墊調節類型中之至少一者。舉例而言，提高漿料流速可減少導電材料之凹陷，或降低漿料流速可增加導電材料之凹陷。
結論
儘管已以特定針對於結構特徵及/或方法行動之語言描述本發明之實施，但應理解，實施不一定限於所描述特定特徵或行動。實情為，將特定特徵及行動揭示為實施實例裝置及技術之代表性形式。
本文之每項申請專利範圍構成單獨具體實例，且組合不同申請專利範圍之具體實例及/或不同具體實例在本發明之範圍內，且將在查閱本發明之後即刻對於一般熟習此項技術者顯而易見。
1‧‧‧步驟
2‧‧‧步驟
3‧‧‧步驟
100‧‧‧微電子元件
102‧‧‧第一晶圓/第一基板
103‧‧‧第一基底層
104‧‧‧介電質/介電層
106‧‧‧導電結構
108‧‧‧凹進
200‧‧‧程序
202‧‧‧腔
204‧‧‧表面
206‧‧‧層
208‧‧‧曲率半徑/介電質侵蝕
210‧‧‧曲率半徑/介電質侵蝕
300‧‧‧剖面圖
302‧‧‧第一介電層
304‧‧‧第一導電結構
306‧‧‧第二晶圓/第二基板
308‧‧‧第二介電層
310‧‧‧第二導電結構
312‧‧‧間隙
400‧‧‧微電子組件
402‧‧‧介電層
404‧‧‧導電結構
406‧‧‧凹進
500‧‧‧微電子總成
502‧‧‧第一介電層
504‧‧‧第一導電結構
506‧‧‧第二介電層
508‧‧‧第二導電結構
510‧‧‧介電質侵蝕
512‧‧‧導電結構凹陷
600‧‧‧剖面圖
602‧‧‧基板層
604‧‧‧介電層
606‧‧‧障壁層
608‧‧‧導電結構
610‧‧‧開口
700‧‧‧程序
702‧‧‧介電層
704‧‧‧障壁層
706‧‧‧導電層
708‧‧‧導電結構
710‧‧‧介電質侵蝕
712‧‧‧導電結構
714‧‧‧介電質侵蝕
716‧‧‧導電結構
718‧‧‧介電質侵蝕
800‧‧‧襯墊
802‧‧‧臨界尺寸
804‧‧‧間距
902‧‧‧晶圓
906‧‧‧配置
908‧‧‧配置
910‧‧‧配置
1000‧‧‧表面平坦化結果
1002‧‧‧晶圓
1004‧‧‧樣本線
1006‧‧‧剖面線
1008‧‧‧表
1100‧‧‧流程圖
1102‧‧‧步驟
1104‧‧‧步驟
1106‧‧‧步驟
1108‧‧‧步驟
1110‧‧‧步驟
A‧‧‧步驟/區塊
B‧‧‧步驟/區塊
C‧‧‧步驟/區塊
D‧‧‧步驟
E‧‧‧步驟
參考隨附圖式闡述詳細描述。在該些圖中，參考數字之最左側數位標識首次出現該參考數字之圖。在不同圖中使用相同參考數字指示類似或相同物件。
對此論述，在圖式中所說明之裝置及系統展示為具有大量組件。如本文中所描述，裝置及/或系統之各種實施可包括較少組件且保持在本發明之範圍內。替代地，裝置及/或系統之其他實施可包括額外組件或所描述組件之各種組合，且保持在本發明之範圍內。
圖1展示氧化物圓化及導電結構凹陷之剖面圖。
圖2展示導致氧化物圓化及導電結構凹陷之程序。
圖3展示示出氧化物圓化及導電結構凹陷之堆疊晶圓的剖面圖。
圖4展示根據具體實例之減少之氧化物圓化及減少之導電結構凹陷的剖面圖。
圖5展示根據具體實例之堆疊晶圓的剖面圖。
圖6展示根據具體實例之晶圓之層的剖面圖。
圖7展示根據具體實例之化學機械拋光的程序。
圖8A至圖8D展示根據實例具體實例之基於金屬密度的襯墊佈局。
圖9展示根據具體實例之基於圖案的襯墊佈局。
圖10A及圖10B展示根據具體實例之襯墊調節參數的結果。
圖11為說明根據具體實例之用於拋光層以供混合接合之實例程序的流程圖。

Claims (21)

  1. 一種方法，其包含： 在基板之介電層之表面中形成一或多個預定開口，該些開口中之至少一者之寬度為至少5微米； 在該介電層之該表面及該些開口上方形成障壁層； 在該障壁層上方且在該些開口內形成導電結構； 對該導電結構之至少一部分拋光以顯露該障壁層之表面；及 對該障壁層拋光以顯露具有小於1 nm之表面粗糙度的平坦介電質接合表面，且使得該導電結構自該接合表面凹進小於20 nm。
  2. 如請求項1所述之方法，其中該些開口中之該導電結構之至少一部分耦接至或接觸該基板內之電路或導電結構。
  3. 一種方法，其包含： 在基板之介電層之表面中形成開口； 在該介電層之該表面上方且在該些開口內形成障壁層； 在該障壁層之該表面上方且在該些開口內形成導電結構； 對該導電結構之至少一部分拋光以顯露該障壁層之表面，使得該些開口內之該導電結構之至少一部分在該介電層之該表面上方自該障壁層之一部分凹進第一預定量，該些導電結構中之至少一者之寬度為至少5微米，且導電結構配置之間距為該導電結構之該寬度的至少1.2倍；及 對該障壁層拋光以曝光該介電層之接合表面，使得該導電結構凹進第二預定量，該第二預定量在該介電層之該接合表面下方少於20 nm。
  4. 如請求項3所述之方法，其中該些開口中之該導電結構之至少一部分耦接至或接觸該基板內之電路或導電結構。
  5. 如請求項3所述之方法，其進一步包含在沈積該導電層之前，在該障壁層上方塗佈晶種層。
  6. 一種形成具有導電結構之陣列之介電質接合表面的方法，其包含： 在基板之介電層中形成開口之一或多個預定陣列； 在該介電層上方，包括在該些開口內，形成障壁層； 在該障壁層上方形成導電材料； 對該導電材料之一部分拋光以顯露該障壁層之表面且形成導電結構，該些導電結構的表面處於該障壁層之該表面下方之第一預定凹進，該些導電結構之寬度為5至50微米，且該些導電結構之陣列之圖案密度小於30%；及 對該障壁層拋光以顯露平坦介電質接合表面且在該導電結構中、該平坦介電質接合表面下方形成第二預定凹進。
  7. 如請求項6所述之方法，其中該第一預定凹進等於或大於該第二預定凹進，且該第二預定凹進小於20 nm。
  8. 如請求項6所述之方法，其中該基板為第一基板，該方法進一步包含將該第一基板之該平坦介電質接合表面接合至第二基板之經製備的平坦接合表面。
  9. 如請求項8所述之方法，其中該第二基板小於該第一基板。
  10. 如請求項8所述之方法，其中該第一基板之導電結構之該陣列中的局部襯墊金屬密度大於5%且小於50%。
  11. 一種組件，其包含： 第一基板，其包含至少一第一平坦介電層，該第一平坦介電層包括導電結構之配置，該些導電結構各自具有至少5微米之寬度；及 第二基板，其包含直接接合至該第一介電層之至少一第二平坦介電層，該第二平坦介電層包括導電結構之配置，該第二基板上之該些導電結構中之至少一者與該第一基板上之該些導電結構中之至少一者接觸， 其中該第一基板上之該些導電結構之該配置之間距為該第二基板上之該些導電結構中之至少一者之寬度的至少1.2倍。
  12. 如請求項11所述之組件，其中該第一基板及該第二基板上之導電結構之該配置設置於相對於該第一基板與該第二基板之間的接合界面之第一區中，該組件進一步包含相對於該第一基板與該第二基板之間的接合界面之第二區，其中沿該接合界面不具有導電結構。
  13. 如請求項12所述之組件，其中該第一區相對於且沿該第一基板與該第二基板之間的接合界面處於中心區中。
  14. 如請求項12所述之組件，其中該中心區包含該接合界面之小於一半區域。
  15. 如請求項11所述之組件，其中第一導電結構之該配置為第一配置，該第一基板具有第二導電結構之第二配置，其中第一導電結構之該第一配置的間距不同於該第一基板上之第二導電結構之該第二配置的間距。
  16. 如請求項15所述之組件，其中該第一配置中之該些第一導電結構中之至少一者具有不同於該第二配置中之該些第二結構中之至少一者之寬度的寬度。
  17. 如請求項11所述之組件，其中該第一基板及該第二基板上之導電結構之該配置在該些第二導電結構中之至少一些之間不規則。
  18. 如請求項11所述之組件，其中該第二基板包括微電子儲存裝置。
  19. 如請求項11所述之組件，其中該些導電結構係由銅、銅合金或鎳構成。
  20. 如請求項11所述之組件，其中該第一基板與該第二基板之間的界面包括氮氣。
  21. 如請求項16所述之組件，其中該第一配置與該第二配置分離距離，該距離不同於該第一配置之該間距或該第二配置之該間距。
TW107133206A 2017-09-24 2018-09-20 用於混合接合的化學機械拋光 TWI835746B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201762562449P 2017-09-24 2017-09-24
US62/562,449 2017-09-24
US201862730936P 2018-09-13 2018-09-13
US62/730,936 2018-09-13
US16/133,299 2018-09-17
US16/133,299 US10840205B2 (en) 2017-09-24 2018-09-17 Chemical mechanical polishing for hybrid bonding

Publications (2)

Publication Number Publication Date
TW201921587A true TW201921587A (zh) 2019-06-01
TWI835746B TWI835746B (zh) 2024-03-21

Family

ID=65808955

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107133206A TWI835746B (zh) 2017-09-24 2018-09-20 用於混合接合的化學機械拋光

Country Status (5)

Country Link
US (3) US10840205B2 (zh)
EP (1) EP3685432A4 (zh)
CN (3) CN117476547A (zh)
TW (1) TWI835746B (zh)
WO (1) WO2019060304A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111933533B (zh) * 2020-08-17 2021-06-04 长江存储科技有限责任公司 半导体封装结构及其制造方法

Families Citing this family (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US10886250B2 (en) 2015-07-10 2021-01-05 Invensas Corporation Structures and methods for low temperature bonding using nanoparticles
US9953941B2 (en) 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10580735B2 (en) 2016-10-07 2020-03-03 Xcelsis Corporation Stacked IC structure with system level wiring on multiple sides of the IC die
US10719762B2 (en) 2017-08-03 2020-07-21 Xcelsis Corporation Three dimensional chip structure implementing machine trained network
TWI822659B (zh) 2016-10-27 2023-11-21 美商艾德亞半導體科技有限責任公司 用於低溫接合的結構和方法
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
TWI782939B (zh) 2016-12-29 2022-11-11 美商英帆薩斯邦德科技有限公司 具有整合式被動構件的接合結構
JP7030825B2 (ja) 2017-02-09 2022-03-07 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド 接合構造物
US10629577B2 (en) 2017-03-16 2020-04-21 Invensas Corporation Direct-bonded LED arrays and applications
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
US10217720B2 (en) 2017-06-15 2019-02-26 Invensas Corporation Multi-chip modules formed using wafer-level processing of a reconstitute wafer
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US10796995B2 (en) 2017-11-29 2020-10-06 Tohoku University Semiconductor devices including a first cobalt alloy in a first barrier layer and a second cobalt alloy in a second barrier layer
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
US11276676B2 (en) 2018-05-15 2022-03-15 Invensas Bonding Technologies, Inc. Stacked devices and methods of fabrication
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
US10910344B2 (en) 2018-06-22 2021-02-02 Xcelsis Corporation Systems and methods for releveled bump planes for chiplets
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11515291B2 (en) 2018-08-28 2022-11-29 Adeia Semiconductor Inc. Integrated voltage regulator and passive components
US20200075533A1 (en) 2018-08-29 2020-03-05 Invensas Bonding Technologies, Inc. Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
KR20210104742A (ko) 2019-01-14 2021-08-25 인벤사스 본딩 테크놀로지스 인코포레이티드 접합 구조체
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US10854578B2 (en) 2019-03-29 2020-12-01 Invensas Corporation Diffused bitline replacement in stacked wafer memory
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
CN110085515B (zh) * 2019-04-30 2021-04-13 德淮半导体有限公司 晶片接合方法
CN110071051A (zh) * 2019-04-30 2019-07-30 德淮半导体有限公司 晶片接合方法
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
KR20210025156A (ko) 2019-08-26 2021-03-09 삼성전자주식회사 반도체 장치 및 그 제조방법
US11837575B2 (en) * 2019-08-26 2023-12-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding passive devices on active device dies to form 3D packages
KR20210024893A (ko) 2019-08-26 2021-03-08 삼성전자주식회사 반도체 소자 제조 방법
KR20210048638A (ko) 2019-10-23 2021-05-04 삼성전자주식회사 반도체 패키지
US11862602B2 (en) 2019-11-07 2024-01-02 Adeia Semiconductor Technologies Llc Scalable architecture for reduced cycles across SOC
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11876076B2 (en) 2019-12-20 2024-01-16 Adeia Semiconductor Technologies Llc Apparatus for non-volatile random access memory stacks
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
US11842894B2 (en) 2019-12-23 2023-12-12 Adeia Semiconductor Bonding Technologies Inc. Electrical redundancy for bonded structures
US11205635B2 (en) 2020-02-05 2021-12-21 Shun-Ping Huang Low temperature hybrid bonding structures and manufacturing method thereof
KR20230003471A (ko) 2020-03-19 2023-01-06 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 결합된 구조체들을 위한 치수 보상 제어
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11410957B2 (en) 2020-07-23 2022-08-09 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and method of manufacturing the same
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11264357B1 (en) 2020-10-20 2022-03-01 Invensas Corporation Mixed exposure for large die
WO2022094587A1 (en) * 2020-10-29 2022-05-05 Invensas Bonding Technologies, Inc. Direct bonding methods and structures
FR3116268B1 (fr) * 2020-11-16 2023-10-20 Commissariat Energie Atomique Circuit électronique pour un collage moléculaire hybride
JP2022130097A (ja) 2021-02-25 2022-09-06 キオクシア株式会社 半導体装置およびその製造方法
US11804378B2 (en) * 2021-12-31 2023-10-31 International Business Machines Corporation Surface conversion in chemical mechanical polishing
US11899376B1 (en) 2022-08-31 2024-02-13 Applied Materials, Inc. Methods for forming alignment marks

Family Cites Families (340)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6130059A (ja) 1984-07-20 1986-02-12 Nec Corp 半導体装置の製造方法
KR900008647B1 (ko) 1986-03-20 1990-11-26 후지쓰 가부시끼가이샤 3차원 집적회로와 그의 제조방법
JPH07112041B2 (ja) 1986-12-03 1995-11-29 シャープ株式会社 半導体装置の製造方法
US4904328A (en) 1987-09-08 1990-02-27 Gencorp Inc. Bonding of FRP parts
US4784970A (en) 1987-11-18 1988-11-15 Grumman Aerospace Corporation Process for making a double wafer moated signal processor
JPH0272642A (ja) 1988-09-07 1990-03-12 Nec Corp 基板の接続構造および接続方法
JPH0344067A (ja) 1989-07-11 1991-02-25 Nec Corp 半導体基板の積層方法
US5489804A (en) 1989-08-28 1996-02-06 Lsi Logic Corporation Flexible preformed planar structures for interposing between a chip and a substrate
JP3190057B2 (ja) 1990-07-02 2001-07-16 株式会社東芝 複合集積回路装置
JP2729413B2 (ja) 1991-02-14 1998-03-18 三菱電機株式会社 半導体装置
JP2910334B2 (ja) 1991-07-22 1999-06-23 富士電機株式会社 接合方法
JPH05198739A (ja) 1991-09-10 1993-08-06 Mitsubishi Electric Corp 積層型半導体装置およびその製造方法
CA2083072C (en) 1991-11-21 1998-02-03 Shinichi Hasegawa Method for manufacturing polyimide multilayer wiring substrate
US6008126A (en) 1992-04-08 1999-12-28 Elm Technology Corporation Membrane dielectric isolation IC fabrication
US5236118A (en) 1992-05-12 1993-08-17 The Regents Of The University Of California Aligned wafer bonding
JPH0682753B2 (ja) 1992-09-28 1994-10-19 株式会社東芝 半導体装置の製造方法
US5503704A (en) 1993-01-06 1996-04-02 The Regents Of The University Of California Nitrogen based low temperature direct bonding
EP0610709B1 (de) 1993-02-11 1998-06-10 Siemens Aktiengesellschaft Verfahren zur Herstellung einer dreidimensionalen Schaltungsanordnung
US5516727A (en) 1993-04-19 1996-05-14 International Business Machines Corporation Method for encapsulating light emitting diodes
JPH0766093A (ja) 1993-08-23 1995-03-10 Sumitomo Sitix Corp 半導体ウエーハの貼り合わせ方法およびその装置
JP2560625B2 (ja) 1993-10-29 1996-12-04 日本電気株式会社 半導体装置およびその製造方法
DE69429848T2 (de) 1993-11-01 2002-09-26 Matsushita Electric Ind Co Ltd Elektronische Anordnung und Verfahren zur Herstellung
US5501003A (en) 1993-12-15 1996-03-26 Bel Fuse Inc. Method of assembling electronic packages for surface mount applications
US5442235A (en) 1993-12-23 1995-08-15 Motorola Inc. Semiconductor device having an improved metal interconnect structure
US5413952A (en) 1994-02-02 1995-05-09 Motorola, Inc. Direct wafer bonded structure method of making
JP3294934B2 (ja) 1994-03-11 2002-06-24 キヤノン株式会社 半導体基板の作製方法及び半導体基板
JPH07283382A (ja) 1994-04-12 1995-10-27 Sony Corp シリコン基板のはり合わせ方法
JPH08125121A (ja) 1994-08-29 1996-05-17 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
KR960009074A (ko) 1994-08-29 1996-03-22 모리시다 요이치 반도체 장치 및 그 제조방법
JP3171366B2 (ja) 1994-09-05 2001-05-28 三菱マテリアル株式会社 シリコン半導体ウェーハ及びその製造方法
DE4433330C2 (de) 1994-09-19 1997-01-30 Fraunhofer Ges Forschung Verfahren zur Herstellung von Halbleiterstrukturen mit vorteilhaften Hochfrequenzeigenschaften sowie eine Halbleiterwaferstruktur
DE4433845A1 (de) 1994-09-22 1996-03-28 Fraunhofer Ges Forschung Verfahren zur Herstellung einer dreidimensionalen integrierten Schaltung
JPH08186235A (ja) 1994-12-16 1996-07-16 Texas Instr Inc <Ti> 半導体装置の製造方法
JP2679681B2 (ja) 1995-04-28 1997-11-19 日本電気株式会社 半導体装置、半導体装置用パッケージ及びその製造方法
US5610431A (en) 1995-05-12 1997-03-11 The Charles Stark Draper Laboratory, Inc. Covers for micromechanical sensors and other semiconductor devices
US5872051A (en) * 1995-08-02 1999-02-16 International Business Machines Corporation Process for transferring material to semiconductor chip conductive pads using a transfer substrate
JP3490198B2 (ja) 1995-10-25 2004-01-26 松下電器産業株式会社 半導体装置とその製造方法
JP3979687B2 (ja) 1995-10-26 2007-09-19 アプライド マテリアルズ インコーポレイテッド ハロゲンをドープした酸化珪素膜の膜安定性を改良する方法
KR100438256B1 (ko) 1995-12-18 2004-08-25 마츠시타 덴끼 산교 가부시키가이샤 반도체장치 및 그 제조방법
ATE204251T1 (de) 1996-05-14 2001-09-15 Degussa Verfahren zur herstellung von trimethylhydrochinon
US5956605A (en) 1996-09-20 1999-09-21 Micron Technology, Inc. Use of nitrides for flip-chip encapsulation
JP3383811B2 (ja) 1996-10-28 2003-03-10 松下電器産業株式会社 半導体チップモジュール及びその製造方法
US5888631A (en) 1996-11-08 1999-03-30 W. L. Gore & Associates, Inc. Method for minimizing warp in the production of electronic assemblies
US6054363A (en) 1996-11-15 2000-04-25 Canon Kabushiki Kaisha Method of manufacturing semiconductor article
US5821692A (en) 1996-11-26 1998-10-13 Motorola, Inc. Organic electroluminescent device hermetic encapsulation package
EP0951064A4 (en) 1996-12-24 2005-02-23 Nitto Denko Corp PREPARATION OF A SEMICONDUCTOR DEVICE
US6221753B1 (en) 1997-01-24 2001-04-24 Micron Technology, Inc. Flip chip technique for chip assembly
JPH10223636A (ja) 1997-02-12 1998-08-21 Nec Yamagata Ltd 半導体集積回路装置の製造方法
JP4026882B2 (ja) 1997-02-24 2007-12-26 三洋電機株式会社 半導体装置
US5929512A (en) 1997-03-18 1999-07-27 Jacobs; Richard L. Urethane encapsulated integrated circuits and compositions therefor
US5915167A (en) 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
AU7147798A (en) 1997-04-23 1998-11-13 Advanced Chemical Systems International, Inc. Planarization compositions for cmp of interlayer dielectrics
JP4032454B2 (ja) 1997-06-27 2008-01-16 ソニー株式会社 三次元回路素子の製造方法
US6097096A (en) 1997-07-11 2000-08-01 Advanced Micro Devices Metal attachment method and structure for attaching substrates at low temperatures
JPH11186120A (ja) 1997-12-24 1999-07-09 Canon Inc 同種あるいは異種材料基板間の密着接合法
US6137063A (en) 1998-02-27 2000-10-24 Micron Technology, Inc. Electrical interconnections
EP0951068A1 (en) 1998-04-17 1999-10-20 Interuniversitair Micro-Elektronica Centrum Vzw Method of fabrication of a microstructure having an inside cavity
US6147000A (en) 1998-08-11 2000-11-14 Advanced Micro Devices, Inc. Method for forming low dielectric passivation of copper interconnects
US6316786B1 (en) 1998-08-29 2001-11-13 International Business Machines Corporation Organic opto-electronic devices
JP2000100679A (ja) 1998-09-22 2000-04-07 Canon Inc 薄片化による基板間微小領域固相接合法及び素子構造
SG99289A1 (en) 1998-10-23 2003-10-27 Ibm Chemical-mechanical planarization of metallurgy
US6515343B1 (en) 1998-11-19 2003-02-04 Quicklogic Corporation Metal-to-metal antifuse with non-conductive diffusion barrier
US6409904B1 (en) 1998-12-01 2002-06-25 Nutool, Inc. Method and apparatus for depositing and controlling the texture of a thin film
US6123825A (en) 1998-12-02 2000-09-26 International Business Machines Corporation Electromigration-resistant copper microstructure and process of making
US6232150B1 (en) 1998-12-03 2001-05-15 The Regents Of The University Of Michigan Process for making microstructures and microstructures made thereby
JP3918350B2 (ja) 1999-03-05 2007-05-23 セイコーエプソン株式会社 半導体装置の製造方法
US6348709B1 (en) 1999-03-15 2002-02-19 Micron Technology, Inc. Electrical contact for high dielectric constant capacitors and method for fabricating the same
JP3532788B2 (ja) 1999-04-13 2004-05-31 唯知 須賀 半導体装置及びその製造方法
US6259160B1 (en) 1999-04-21 2001-07-10 Advanced Micro Devices, Inc. Apparatus and method of encapsulated copper (Cu) Interconnect formation
JP2000311982A (ja) 1999-04-26 2000-11-07 Toshiba Corp 半導体装置と半導体モジュールおよびそれらの製造方法
US6258625B1 (en) 1999-05-18 2001-07-10 International Business Machines Corporation Method of interconnecting electronic components using a plurality of conductive studs
KR100333384B1 (ko) 1999-06-28 2002-04-18 박종섭 칩 사이즈 스택 패키지 및 그의 제조방법
US6218203B1 (en) 1999-06-28 2001-04-17 Advantest Corp. Method of producing a contact structure
JP3619395B2 (ja) 1999-07-30 2005-02-09 京セラ株式会社 半導体素子内蔵配線基板およびその製造方法
US6756253B1 (en) 1999-08-27 2004-06-29 Micron Technology, Inc. Method for fabricating a semiconductor component with external contact polymer support layer
US6583515B1 (en) 1999-09-03 2003-06-24 Texas Instruments Incorporated Ball grid array package for enhanced stress tolerance
US6355153B1 (en) * 1999-09-17 2002-03-12 Nutool, Inc. Chip interconnect and packaging deposition methods and structures
US6593645B2 (en) 1999-09-24 2003-07-15 United Microelectronics Corp. Three-dimensional system-on-chip structure
JP2001102479A (ja) 1999-09-27 2001-04-13 Toshiba Corp 半導体集積回路装置およびその製造方法
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6500694B1 (en) 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6333120B1 (en) 1999-10-27 2001-12-25 International Business Machines Corporation Method for controlling the texture and microstructure of plated copper and plated structure
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
AU2001247109A1 (en) 2000-04-27 2001-11-12 Nutool, Inc. Conductive structure for use in multi-level metallization and process
JP4123682B2 (ja) 2000-05-16 2008-07-23 セイコーエプソン株式会社 半導体装置及びその製造方法
US6326698B1 (en) 2000-06-08 2001-12-04 Micron Technology, Inc. Semiconductor devices having protective layers thereon through which contact pads are exposed and stereolithographic methods of fabricating such semiconductor devices
JP4322402B2 (ja) 2000-06-22 2009-09-02 大日本印刷株式会社 プリント配線基板及びその製造方法
JP3440057B2 (ja) 2000-07-05 2003-08-25 唯知 須賀 半導体装置およびその製造方法
TW515223B (en) 2000-07-24 2002-12-21 Tdk Corp Light emitting device
US6423640B1 (en) 2000-08-09 2002-07-23 Taiwan Semiconductor Manufacturing Co., Ltd. Headless CMP process for oxide planarization
US6483044B1 (en) 2000-08-23 2002-11-19 Micron Technology, Inc. Interconnecting substrates for electrical coupling of microelectronic components
US6583460B1 (en) 2000-08-29 2003-06-24 Micron Technology, Inc. Method of forming a metal to polysilicon contact in oxygen environment
JP2002110799A (ja) 2000-09-27 2002-04-12 Toshiba Corp 半導体装置及びその製造方法
US6600224B1 (en) 2000-10-31 2003-07-29 International Business Machines Corporation Thin film attachment to laminate using a dendritic interconnection
US6552436B2 (en) 2000-12-08 2003-04-22 Motorola, Inc. Semiconductor device having a ball grid array and method therefor
JP2002353416A (ja) 2001-05-25 2002-12-06 Sony Corp 半導体記憶装置およびその製造方法
JP3705159B2 (ja) 2001-06-11 2005-10-12 株式会社デンソー 半導体装置の製造方法
DE10131627B4 (de) 2001-06-29 2006-08-10 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterspeichereinrichtung
JP2003023071A (ja) 2001-07-05 2003-01-24 Sony Corp 半導体装置製造方法および半導体装置
US6847527B2 (en) 2001-08-24 2005-01-25 3M Innovative Properties Company Interconnect module with reduced power distribution impedance
US6555917B1 (en) 2001-10-09 2003-04-29 Amkor Technology, Inc. Semiconductor package having stacked semiconductor chips and method of making the same
US6667225B2 (en) 2001-12-17 2003-12-23 Intel Corporation Wafer-bonding using solder and method of making the same
US20030113947A1 (en) 2001-12-19 2003-06-19 Vandentop Gilroy J. Electrical/optical integration scheme using direct copper bonding
US6660564B2 (en) 2002-01-25 2003-12-09 Sony Corporation Wafer-level through-wafer packaging process for MEMS and MEMS package produced thereby
US6887769B2 (en) 2002-02-06 2005-05-03 Intel Corporation Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
US6624003B1 (en) 2002-02-06 2003-09-23 Teravicta Technologies, Inc. Integrated MEMS device and package
US6762076B2 (en) 2002-02-20 2004-07-13 Intel Corporation Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
US6720212B2 (en) 2002-03-14 2004-04-13 Infineon Technologies Ag Method of eliminating back-end rerouting in ball grid array packaging
US6627814B1 (en) 2002-03-22 2003-09-30 David H. Stark Hermetically sealed micro-device package with window
US6642081B1 (en) 2002-04-11 2003-11-04 Robert Patti Interlocking conductor method for bonding wafers to produce stacked integrated circuits
US7105980B2 (en) 2002-07-03 2006-09-12 Sawtek, Inc. Saw filter device and method employing normal temperature bonding for producing desirable filter production and performance characteristics
JP4083502B2 (ja) 2002-08-19 2008-04-30 株式会社フジミインコーポレーテッド 研磨方法及びそれに用いられる研磨用組成物
US7023093B2 (en) 2002-10-24 2006-04-04 International Business Machines Corporation Very low effective dielectric constant interconnect Structures and methods for fabricating the same
US7354798B2 (en) 2002-12-20 2008-04-08 International Business Machines Corporation Three-dimensional device fabrication method
JP3918935B2 (ja) 2002-12-20 2007-05-23 セイコーエプソン株式会社 半導体装置の製造方法
JP3981026B2 (ja) 2003-01-30 2007-09-26 株式会社東芝 多層配線層を有する半導体装置およびその製造方法
US6962835B2 (en) 2003-02-07 2005-11-08 Ziptronix, Inc. Method for room temperature metal direct bonding
US7135780B2 (en) 2003-02-12 2006-11-14 Micron Technology, Inc. Semiconductor substrate for build-up packages
US6908027B2 (en) 2003-03-31 2005-06-21 Intel Corporation Complete device layer transfer without edge exclusion via direct wafer bonding and constrained bond-strengthening process
DE10319538B4 (de) 2003-04-30 2008-01-17 Qimonda Ag Halbleitervorrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
TWI275168B (en) 2003-06-06 2007-03-01 Sanyo Electric Co Semiconductor device and method for making the same
US20040262772A1 (en) 2003-06-30 2004-12-30 Shriram Ramanathan Methods for bonding wafers using a metal interlayer
JP2005086089A (ja) 2003-09-10 2005-03-31 Seiko Epson Corp ３次元デバイスの製造方法
JP2005093486A (ja) 2003-09-12 2005-04-07 Seiko Epson Corp 半導体装置の製造方法及び半導体装置
US6867073B1 (en) 2003-10-21 2005-03-15 Ziptronix, Inc. Single mask via method and device
JP2005135988A (ja) 2003-10-28 2005-05-26 Toshiba Corp 半導体装置の製造方法
US8026128B2 (en) * 2004-11-10 2011-09-27 Stats Chippac, Ltd. Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
US6927498B2 (en) 2003-11-19 2005-08-09 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad for flip chip package
US7842948B2 (en) 2004-02-27 2010-11-30 Nvidia Corporation Flip chip semiconductor die internal signal access system and method
KR100618855B1 (ko) 2004-08-02 2006-09-01 삼성전자주식회사 금속 콘택 구조체 형성방법 및 이를 이용한 상변화 메모리제조방법
US20060057945A1 (en) 2004-09-16 2006-03-16 Chia-Lin Hsu Chemical mechanical polishing process
US20060076634A1 (en) 2004-09-27 2006-04-13 Lauren Palmateer Method and system for packaging MEMS devices with incorporated getter
GB0505680D0 (en) 2005-03-22 2005-04-27 Cambridge Display Tech Ltd Apparatus and method for increased device lifetime in an organic electro-luminescent device
US7998335B2 (en) 2005-06-13 2011-08-16 Cabot Microelectronics Corporation Controlled electrochemical polishing method
US7485968B2 (en) 2005-08-11 2009-02-03 Ziptronix, Inc. 3D IC method and device
US7193423B1 (en) 2005-12-12 2007-03-20 International Business Machines Corporation Wafer-to-wafer alignments
US7348648B2 (en) 2006-03-13 2008-03-25 International Business Machines Corporation Interconnect structure with a barrier-redundancy feature
TWI299552B (en) 2006-03-24 2008-08-01 Advanced Semiconductor Eng Package structure
US7972683B2 (en) 2006-03-28 2011-07-05 Innovative Micro Technology Wafer bonding material with embedded conductive particles
US20070257366A1 (en) * 2006-05-03 2007-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Barrier layer for semiconductor interconnect structure
US7750488B2 (en) 2006-07-10 2010-07-06 Tezzaron Semiconductor, Inc. Method for bonding wafers to produce stacked integrated circuits
KR100825648B1 (ko) 2006-11-29 2008-04-25 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
US9343330B2 (en) 2006-12-06 2016-05-17 Cabot Microelectronics Corporation Compositions for polishing aluminum/copper and titanium in damascene structures
US7803693B2 (en) 2007-02-15 2010-09-28 John Trezza Bowed wafer hybridization compensation
KR101494591B1 (ko) * 2007-10-30 2015-02-23 삼성전자주식회사 칩 적층 패키지
US8435421B2 (en) 2007-11-27 2013-05-07 Cabot Microelectronics Corporation Metal-passivating CMP compositions and methods
DE102008007001B4 (de) 2008-01-31 2016-09-22 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Vergrößern des Widerstandsverhaltens gegenüber Elektromigration in einer Verbindungsstruktur eines Halbleiterbauelements durch Bilden einer Legierung
US20090200668A1 (en) 2008-02-07 2009-08-13 International Business Machines Corporation Interconnect structure with high leakage resistance
US8349721B2 (en) * 2008-03-19 2013-01-08 Stats Chippac, Ltd. Semiconductor device and method of forming insulating layer on conductive traces for electrical isolation in fine pitch bonding
US8349635B1 (en) 2008-05-20 2013-01-08 Silicon Laboratories Inc. Encapsulated MEMS device and method to form the same
US9893004B2 (en) 2011-07-27 2018-02-13 Broadpak Corporation Semiconductor interposer integration
US8344503B2 (en) 2008-11-25 2013-01-01 Freescale Semiconductor, Inc. 3-D circuits with integrated passive devices
KR100945800B1 (ko) 2008-12-09 2010-03-05 김영혜 이종 접합 웨이퍼 제조방법
IT1392793B1 (it) 2008-12-30 2012-03-23 St Microelectronics Srl Condensatore integrato con piatto a spessore non-uniforme
US8476165B2 (en) 2009-04-01 2013-07-02 Tokyo Electron Limited Method for thinning a bonding wafer
WO2010138480A2 (en) 2009-05-26 2010-12-02 Rambus Inc. Stacked semiconductor device assembly
US8101517B2 (en) 2009-09-29 2012-01-24 Infineon Technologies Ag Semiconductor device and method for making same
US8482132B2 (en) 2009-10-08 2013-07-09 International Business Machines Corporation Pad bonding employing a self-aligned plated liner for adhesion enhancement
FR2954585B1 (fr) 2009-12-23 2012-03-02 Soitec Silicon Insulator Technologies Procede de realisation d'une heterostructure avec minimisation de contrainte
KR101559617B1 (ko) 2010-03-01 2015-10-12 오사카 유니버시티 반도체장치 및 반도체장치용 접합재
US9018768B2 (en) 2010-06-28 2015-04-28 Samsung Electronics Co., Ltd. Integrated circuit having through silicon via structure with minimized deterioration
JP5517800B2 (ja) 2010-07-09 2014-06-11 キヤノン株式会社 固体撮像装置用の部材および固体撮像装置の製造方法
CN104011848A (zh) 2010-07-30 2014-08-27 昆山智拓达电子科技有限公司 一种硅通孔互连结构及其制造方法
FR2966283B1 (fr) 2010-10-14 2012-11-30 Soi Tec Silicon On Insulator Tech Sa Procede pour realiser une structure de collage
US8377798B2 (en) 2010-11-10 2013-02-19 Taiwan Semiconductor Manufacturing Co., Ltd Method and structure for wafer to wafer bonding in semiconductor packaging
US8476146B2 (en) 2010-12-03 2013-07-02 Taiwan Semiconductor Manufacturing Company, Ltd. Reducing wafer distortion through a low CTE layer
US8620164B2 (en) 2011-01-20 2013-12-31 Intel Corporation Hybrid III-V silicon laser formed by direct bonding
US8988299B2 (en) 2011-02-17 2015-03-24 International Business Machines Corporation Integrated antenna for RFIC package applications
JP2012174988A (ja) 2011-02-23 2012-09-10 Sony Corp 接合電極、接合電極の製造方法、半導体装置、及び、半導体装置の製造方法
KR101780423B1 (ko) 2011-03-18 2017-09-22 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US8501537B2 (en) 2011-03-31 2013-08-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures formed using such methods
US8716105B2 (en) 2011-03-31 2014-05-06 Soitec Methods for bonding semiconductor structures involving annealing processes, and bonded semiconductor structures and intermediate structures formed using such methods
WO2012161044A1 (ja) 2011-05-24 2012-11-29 ソニー株式会社 半導体装置
JP6031765B2 (ja) 2011-07-05 2016-11-24 ソニー株式会社 半導体装置、電子機器、及び、半導体装置の製造方法
JP5982748B2 (ja) 2011-08-01 2016-08-31 ソニー株式会社 半導体装置、半導体装置の製造方法、および電子機器
US8697493B2 (en) 2011-07-18 2014-04-15 Soitec Bonding surfaces for direct bonding of semiconductor structures
US8441131B2 (en) 2011-09-12 2013-05-14 Globalfoundries Inc. Strain-compensating fill patterns for controlling semiconductor chip package interactions
US8796853B2 (en) 2012-02-24 2014-08-05 International Business Machines Corporation Metallic capped interconnect structure with high electromigration resistance and low resistivity
US20130256913A1 (en) 2012-03-30 2013-10-03 Bryan Black Die stacking with coupled electrical interconnects to align proximity interconnects
CN103377911B (zh) 2012-04-16 2016-09-21 中国科学院微电子研究所 提高化学机械平坦化工艺均匀性的方法
JP2013243333A (ja) * 2012-04-24 2013-12-05 Tadatomo Suga チップオンウエハ接合方法及び接合装置並びにチップとウエハとを含む構造体
US9412725B2 (en) 2012-04-27 2016-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for image sensor packaging
US8809123B2 (en) 2012-06-05 2014-08-19 Taiwan Semiconductor Manufacturing Company, Ltd. Three dimensional integrated circuit structures and hybrid bonding methods for semiconductor wafers
US9142517B2 (en) 2012-06-05 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding mechanisms for semiconductor wafers
US9048283B2 (en) 2012-06-05 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding systems and methods for semiconductor wafers
US8772946B2 (en) 2012-06-08 2014-07-08 Invensas Corporation Reduced stress TSV and interposer structures
US8735219B2 (en) 2012-08-30 2014-05-27 Ziptronix, Inc. Heterogeneous annealing method and device
DE102012224310A1 (de) 2012-12-21 2014-06-26 Tesa Se Gettermaterial enthaltendes Klebeband
US20140175655A1 (en) 2012-12-22 2014-06-26 Industrial Technology Research Institute Chip bonding structure and manufacturing method thereof
US9368438B2 (en) 2012-12-28 2016-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package (PoP) bonding structures
US8916448B2 (en) 2013-01-09 2014-12-23 International Business Machines Corporation Metal to metal bonding for stacked (3D) integrated circuits
US9082644B2 (en) 2013-01-18 2015-07-14 Infineon Technologies Ag Method of manufacturing and testing a chip package
TWI518991B (zh) 2013-02-08 2016-01-21 Sj Antenna Design Integrated antenna and integrated circuit components of the shielding module
US8946784B2 (en) 2013-02-18 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for image sensor packaging
WO2014131152A1 (en) 2013-02-26 2014-09-04 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including alternating stepped semiconductor die stacks
US9331032B2 (en) 2013-03-06 2016-05-03 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding and apparatus for performing the same
US9105485B2 (en) 2013-03-08 2015-08-11 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structures and methods of forming the same
US9443796B2 (en) 2013-03-15 2016-09-13 Taiwan Semiconductor Manufacturing Company, Ltd. Air trench in packages incorporating hybrid bonding
US8802538B1 (en) 2013-03-15 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for hybrid wafer bonding
US9064937B2 (en) 2013-05-30 2015-06-23 International Business Machines Corporation Substrate bonding with diffusion barrier structures
US9929050B2 (en) 2013-07-16 2018-03-27 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
US9040385B2 (en) 2013-07-24 2015-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for cleaning substrate surface for hybrid bonding
WO2015040784A1 (ja) * 2013-09-17 2015-03-26 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
JP6212720B2 (ja) 2013-09-20 2017-10-18 パナソニックＩｐマネジメント株式会社 半導体装置及びその製造方法
US9723716B2 (en) 2013-09-27 2017-08-01 Infineon Technologies Ag Contact pad structure, an electronic component, and a method for manufacturing a contact pad structure
FR3011679B1 (fr) 2013-10-03 2017-01-27 Commissariat Energie Atomique Procede ameliore d'assemblage par collage direct entre deux elements, chaque element comprenant des portions de metal et de materiaux dielectriques
US9257399B2 (en) 2013-10-17 2016-02-09 Taiwan Semiconductor Manufacturing Company, Ltd. 3D integrated circuit and methods of forming the same
US9059333B1 (en) 2013-12-04 2015-06-16 International Business Machines Corporation Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding
JP2015115446A (ja) 2013-12-11 2015-06-22 株式会社東芝 半導体装置の製造方法
US9437572B2 (en) 2013-12-18 2016-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pad structure for hybrid bonding and methods of forming same
US9865523B2 (en) 2014-01-17 2018-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Robust through-silicon-via structure
US9343433B2 (en) 2014-01-28 2016-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Packages with stacked dies and methods of forming the same
US9425155B2 (en) 2014-02-25 2016-08-23 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer bonding process and structure
US20150262902A1 (en) 2014-03-12 2015-09-17 Invensas Corporation Integrated circuits protected by substrates with cavities, and methods of manufacture
US9391109B2 (en) * 2014-03-28 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Uniform-size bonding patterns
US9299736B2 (en) 2014-03-28 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid bonding with uniform pattern density
US9230941B2 (en) 2014-03-28 2016-01-05 Taiwan Semiconductor Manufacturing Company, Ltd. Bonding structure for stacked semiconductor devices
US9343369B2 (en) 2014-05-19 2016-05-17 Qualcomm Incorporated Three dimensional (3D) integrated circuits (ICs) (3DICs) and related systems
FR3021455B1 (fr) * 2014-05-21 2017-10-13 St Microelectronics Crolles 2 Sas Procede d'aplanissement d'evidements remplis de cuivre
US9472458B2 (en) 2014-06-04 2016-10-18 Semiconductor Components Industries, Llc Method of reducing residual contamination in singulated semiconductor die
KR102275705B1 (ko) 2014-07-11 2021-07-09 삼성전자주식회사 웨이퍼 대 웨이퍼 접합 구조
US9536848B2 (en) 2014-10-16 2017-01-03 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
KR102274775B1 (ko) 2014-11-13 2021-07-08 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9394161B2 (en) 2014-11-14 2016-07-19 Taiwan Semiconductor Manufacturing Co., Ltd. MEMS and CMOS integration with low-temperature bonding
US9899442B2 (en) 2014-12-11 2018-02-20 Invensas Corporation Image sensor device
US11069734B2 (en) 2014-12-11 2021-07-20 Invensas Corporation Image sensor device
US10355039B2 (en) 2015-05-18 2019-07-16 Sony Corporation Semiconductor device and imaging device
US9741620B2 (en) 2015-06-24 2017-08-22 Invensas Corporation Structures and methods for reliable packages
US9656852B2 (en) 2015-07-06 2017-05-23 Taiwan Semiconductor Manufacturing Company Ltd. CMOS-MEMS device structure, bonding mesa structure and associated method
US20170012081A1 (en) * 2015-07-06 2017-01-12 Xintec Inc. Chip package and manufacturing method thereof
US10075657B2 (en) 2015-07-21 2018-09-11 Fermi Research Alliance, Llc Edgeless large area camera system
US9728521B2 (en) 2015-07-23 2017-08-08 Taiwan Semiconductor Manufacturing Co., Ltd. Hybrid bond using a copper alloy for yield improvement
US9559081B1 (en) 2015-08-21 2017-01-31 Apple Inc. Independent 3D stacking
US9953941B2 (en) * 2015-08-25 2018-04-24 Invensas Bonding Technologies, Inc. Conductive barrier direct hybrid bonding
CN105140144A (zh) 2015-09-02 2015-12-09 武汉新芯集成电路制造有限公司 一种介质加压热退火混合键合方法
US9496239B1 (en) 2015-12-11 2016-11-15 International Business Machines Corporation Nitride-enriched oxide-to-oxide 3D wafer bonding
US9852988B2 (en) 2015-12-18 2017-12-26 Invensas Bonding Technologies, Inc. Increased contact alignment tolerance for direct bonding
US9893028B2 (en) 2015-12-28 2018-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Bond structures and the methods of forming the same
US9881882B2 (en) 2016-01-06 2018-01-30 Mediatek Inc. Semiconductor package with three-dimensional antenna
US9923011B2 (en) 2016-01-12 2018-03-20 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure with stacked semiconductor dies
US10446532B2 (en) 2016-01-13 2019-10-15 Invensas Bonding Technologies, Inc. Systems and methods for efficient transfer of semiconductor elements
US10050018B2 (en) * 2016-02-26 2018-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC structure and methods of forming
US10636767B2 (en) 2016-02-29 2020-04-28 Invensas Corporation Correction die for wafer/die stack
WO2017155002A1 (ja) 2016-03-11 2017-09-14 ボンドテック株式会社 基板接合方法
US10026716B2 (en) 2016-04-15 2018-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. 3DIC formation with dies bonded to formed RDLs
US10204893B2 (en) 2016-05-19 2019-02-12 Invensas Bonding Technologies, Inc. Stacked dies and methods for forming bonded structures
KR102505856B1 (ko) 2016-06-09 2023-03-03 삼성전자 주식회사 웨이퍼 대 웨이퍼 접합 구조체
US9859254B1 (en) 2016-06-30 2018-01-02 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and a manufacturing method thereof
US9941241B2 (en) 2016-06-30 2018-04-10 International Business Machines Corporation Method for wafer-wafer bonding
US9892961B1 (en) 2016-08-09 2018-02-13 International Business Machines Corporation Air gap spacer formation for nano-scale semiconductor devices
US10446487B2 (en) 2016-09-30 2019-10-15 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
JP2018064758A (ja) 2016-10-19 2018-04-26 ソニーセミコンダクタソリューションズ株式会社 半導体装置、製造方法、および電子機器
CN106571334B (zh) 2016-10-26 2020-11-10 上海集成电路研发中心有限公司 一种硅片间的混合键合方法
US10163750B2 (en) 2016-12-05 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure for heat dissipation
US10453832B2 (en) 2016-12-15 2019-10-22 Taiwan Semiconductor Manufacturing Co., Ltd. Seal ring structures and methods of forming same
US10002844B1 (en) 2016-12-21 2018-06-19 Invensas Bonding Technologies, Inc. Bonded structures
EP3563411B1 (en) 2016-12-28 2021-04-14 Invensas Bonding Technologies, Inc. Method of processing a substrate on a temporary substrate
US20180182665A1 (en) 2016-12-28 2018-06-28 Invensas Bonding Technologies, Inc. Processed Substrate
US20180190583A1 (en) 2016-12-29 2018-07-05 Invensas Bonding Technologies, Inc. Bonded structures with integrated passive component
TWI782939B (zh) 2016-12-29 2022-11-11 美商英帆薩斯邦德科技有限公司 具有整合式被動構件的接合結構
US10276909B2 (en) 2016-12-30 2019-04-30 Invensas Bonding Technologies, Inc. Structure comprising at least a first element bonded to a carrier having a closed metallic channel waveguide formed therein
CN106653720A (zh) 2016-12-30 2017-05-10 武汉新芯集成电路制造有限公司 一种混合键合结构及混合键合方法
US10431614B2 (en) 2017-02-01 2019-10-01 Semiconductor Components Industries, Llc Edge seals for semiconductor packages
JP7030825B2 (ja) 2017-02-09 2022-03-07 インヴェンサス ボンディング テクノロジーズ インコーポレイテッド 接合構造物
CN106920795B (zh) 2017-03-08 2019-03-12 长江存储科技有限责任公司 存储器结构及其制备方法、存储器的测试方法
CN106920797B (zh) 2017-03-08 2018-10-12 长江存储科技有限责任公司 存储器结构及其制备方法、存储器的测试方法
US10515913B2 (en) 2017-03-17 2019-12-24 Invensas Bonding Technologies, Inc. Multi-metal contact structure
US10508030B2 (en) 2017-03-21 2019-12-17 Invensas Bonding Technologies, Inc. Seal for microelectronic assembly
JP6640780B2 (ja) 2017-03-22 2020-02-05 キオクシア株式会社 半導体装置の製造方法および半導体装置
JP2018163970A (ja) 2017-03-24 2018-10-18 東芝メモリ株式会社 半導体装置及びその製造方法
US10784191B2 (en) 2017-03-31 2020-09-22 Invensas Bonding Technologies, Inc. Interface structures and methods for forming same
US10269756B2 (en) 2017-04-21 2019-04-23 Invensas Bonding Technologies, Inc. Die processing
US10312275B2 (en) 2017-04-25 2019-06-04 Semiconductor Components Industries, Llc Single-photon avalanche diode image sensor with photon counting and time-of-flight detection capabilities
US10580823B2 (en) 2017-05-03 2020-03-03 United Microelectronics Corp. Wafer level packaging method
US10879212B2 (en) 2017-05-11 2020-12-29 Invensas Bonding Technologies, Inc. Processed stacked dies
US10446441B2 (en) * 2017-06-05 2019-10-15 Invensas Corporation Flat metal features for microelectronics applications
CN107665829B (zh) 2017-08-24 2019-12-17 长江存储科技有限责任公司 晶圆混合键合中提高金属引线制程安全性的方法
CN107731668B (zh) 2017-08-31 2018-11-13 长江存储科技有限责任公司 3d nand混合键合工艺中补偿晶圆应力的方法
US10840205B2 (en) 2017-09-24 2020-11-17 Invensas Bonding Technologies, Inc. Chemical mechanical polishing for hybrid bonding
US11195748B2 (en) 2017-09-27 2021-12-07 Invensas Corporation Interconnect structures and methods for forming same
US11031285B2 (en) 2017-10-06 2021-06-08 Invensas Bonding Technologies, Inc. Diffusion barrier collar for interconnects
US11251157B2 (en) 2017-11-01 2022-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Die stack structure with hybrid bonding structure and method of fabricating the same and package
CN107993928B (zh) 2017-11-20 2020-05-12 长江存储科技有限责任公司 一种抑制晶圆混合键合中铜电迁移的方法
CN107993927A (zh) 2017-11-20 2018-05-04 长江存储科技有限责任公司 提高晶圆混合键合强度的方法
US11152417B2 (en) 2017-11-21 2021-10-19 Taiwan Semiconductor Manufacturing Co., Ltd. Anchor structures and methods for uniform wafer planarization and bonding
US11011503B2 (en) 2017-12-15 2021-05-18 Invensas Bonding Technologies, Inc. Direct-bonded optoelectronic interconnect for high-density integrated photonics
US11380597B2 (en) 2017-12-22 2022-07-05 Invensas Bonding Technologies, Inc. Bonded structures
US10923408B2 (en) 2017-12-22 2021-02-16 Invensas Bonding Technologies, Inc. Cavity packages
JP6967980B2 (ja) 2018-01-23 2021-11-17 東京エレクトロン株式会社 接合方法、および接合装置
TWI782169B (zh) 2018-01-23 2022-11-01 日商東京威力科創股份有限公司 接合系統及接合方法
US10727219B2 (en) 2018-02-15 2020-07-28 Invensas Bonding Technologies, Inc. Techniques for processing devices
US11169326B2 (en) 2018-02-26 2021-11-09 Invensas Bonding Technologies, Inc. Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects
US11256004B2 (en) 2018-03-20 2022-02-22 Invensas Bonding Technologies, Inc. Direct-bonded lamination for improved image clarity in optical devices
US11056348B2 (en) 2018-04-05 2021-07-06 Invensas Bonding Technologies, Inc. Bonding surfaces for microelectronics
US10790262B2 (en) 2018-04-11 2020-09-29 Invensas Bonding Technologies, Inc. Low temperature bonded structures
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
US11398258B2 (en) 2018-04-30 2022-07-26 Invensas Llc Multi-die module with low power operation
US11004757B2 (en) 2018-05-14 2021-05-11 Invensas Bonding Technologies, Inc. Bonded structures
CN112514059B (zh) 2018-06-12 2024-05-24 隔热半导体粘合技术公司 堆叠微电子部件的层间连接
US11393779B2 (en) 2018-06-13 2022-07-19 Invensas Bonding Technologies, Inc. Large metal pads over TSV
US11749645B2 (en) 2018-06-13 2023-09-05 Adeia Semiconductor Bonding Technologies Inc. TSV as pad
US10937755B2 (en) 2018-06-29 2021-03-02 Advanced Micro Devices, Inc. Bond pads for low temperature hybrid bonding
WO2020010056A1 (en) 2018-07-03 2020-01-09 Invensas Bonding Technologies, Inc. Techniques for joining dissimilar materials in microelectronics
US11462419B2 (en) 2018-07-06 2022-10-04 Invensas Bonding Technologies, Inc. Microelectronic assemblies
US11158606B2 (en) 2018-07-06 2021-10-26 Invensas Bonding Technologies, Inc. Molded direct bonded and interconnected stack
US20200035641A1 (en) 2018-07-26 2020-01-30 Invensas Bonding Technologies, Inc. Post cmp processing for hybrid bonding
CN109155301A (zh) 2018-08-13 2019-01-04 长江存储科技有限责任公司 具有帽盖层的键合触点及其形成方法
US20200075533A1 (en) 2018-08-29 2020-03-05 Invensas Bonding Technologies, Inc. Bond enhancement in microelectronics by trapping contaminants and arresting cracks during direct-bonding processes
US11011494B2 (en) 2018-08-31 2021-05-18 Invensas Bonding Technologies, Inc. Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics
CN109417077B (zh) 2018-09-10 2019-10-18 长江存储科技有限责任公司 使用梳状路由结构以减少金属线装载的存储器件
WO2020051731A1 (en) 2018-09-10 2020-03-19 Yangtze Memory Technologies Co., Ltd. Memory device using comb-like routing structure for reduced metal line loading
CN109417075B (zh) 2018-09-20 2020-06-26 长江存储科技有限责任公司 多堆叠层三维存储器件
US11158573B2 (en) 2018-10-22 2021-10-26 Invensas Bonding Technologies, Inc. Interconnect structures
CN109643643B (zh) 2018-11-30 2020-08-25 长江存储科技有限责任公司 键合存储器件及其制造方法
US11244920B2 (en) 2018-12-18 2022-02-08 Invensas Bonding Technologies, Inc. Method and structures for low temperature device bonding
CN109844915A (zh) 2019-01-02 2019-06-04 长江存储科技有限责任公司 用于晶圆键合的等离子体活化处理
KR20210104742A (ko) 2019-01-14 2021-08-25 인벤사스 본딩 테크놀로지스 인코포레이티드 접합 구조체
US11387202B2 (en) 2019-03-01 2022-07-12 Invensas Llc Nanowire bonding interconnect for fine-pitch microelectronics
US11901281B2 (en) 2019-03-11 2024-02-13 Adeia Semiconductor Bonding Technologies Inc. Bonded structures with integrated passive component
US11205625B2 (en) 2019-04-12 2021-12-21 Invensas Bonding Technologies, Inc. Wafer-level bonding of obstructive elements
US11373963B2 (en) 2019-04-12 2022-06-28 Invensas Bonding Technologies, Inc. Protective elements for bonded structures
US11610846B2 (en) 2019-04-12 2023-03-21 Adeia Semiconductor Bonding Technologies Inc. Protective elements for bonded structures including an obstructive element
US11355404B2 (en) 2019-04-22 2022-06-07 Invensas Bonding Technologies, Inc. Mitigating surface damage of probe pads in preparation for direct bonding of a substrate
US11385278B2 (en) 2019-05-23 2022-07-12 Invensas Bonding Technologies, Inc. Security circuitry for bonded structures
US20200395321A1 (en) 2019-06-12 2020-12-17 Invensas Bonding Technologies, Inc. Sealed bonded structures and methods for forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US20210098412A1 (en) 2019-09-26 2021-04-01 Invensas Bonding Technologies, Inc. Direct gang bonding methods and structures
US11762200B2 (en) 2019-12-17 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded optical devices
US11842894B2 (en) 2019-12-23 2023-12-12 Adeia Semiconductor Bonding Technologies Inc. Electrical redundancy for bonded structures
US11721653B2 (en) 2019-12-23 2023-08-08 Adeia Semiconductor Bonding Technologies Inc. Circuitry for electrical redundancy in bonded structures
US20210242152A1 (en) 2020-02-05 2021-08-05 Invensas Bonding Technologies, Inc. Selective alteration of interconnect pads for direct bonding
KR20230003471A (ko) 2020-03-19 2023-01-06 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 결합된 구조체들을 위한 치수 보상 제어
US11742314B2 (en) 2020-03-31 2023-08-29 Adeia Semiconductor Bonding Technologies Inc. Reliable hybrid bonded apparatus
US11735523B2 (en) 2020-05-19 2023-08-22 Adeia Semiconductor Bonding Technologies Inc. Laterally unconfined structure
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
WO2022094587A1 (en) 2020-10-29 2022-05-05 Invensas Bonding Technologies, Inc. Direct bonding methods and structures
KR20230095110A (ko) 2020-10-29 2023-06-28 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 직접 접합 방법 및 구조체

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111933533B (zh) * 2020-08-17 2021-06-04 长江存储科技有限责任公司 半导体封装结构及其制造方法
CN113380640A (zh) * 2020-08-17 2021-09-10 长江存储科技有限责任公司 半导体封装结构及其制造方法

Also Published As

Publication number Publication date
CN117476548A (zh) 2024-01-30
CN111108592A (zh) 2020-05-05
US20210066233A1 (en) 2021-03-04
US20190096842A1 (en) 2019-03-28
TWI835746B (zh) 2024-03-21
WO2019060304A1 (en) 2019-03-28
US10840205B2 (en) 2020-11-17
CN117476547A (zh) 2024-01-30
EP3685432A1 (en) 2020-07-29
EP3685432A4 (en) 2021-07-07
US20230268308A1 (en) 2023-08-24
US11552041B2 (en) 2023-01-10

Similar Documents

Publication Publication Date Title
TWI835746B (zh) 用於混合接合的化學機械拋光
US11158573B2 (en) Interconnect structures
US20230360968A1 (en) Diffusion barrier collar for interconnects
US11244916B2 (en) Low temperature bonded structures
JP2024501016A (ja) 基板貫通ビアを有する構造体及びそれを形成する方法
US5494854A (en) Enhancement in throughput and planarity during CMP using a dielectric stack containing HDP-SiO2 films
CN104051288B (zh) 用于混合晶圆接合的方法
US10199275B2 (en) Systems and methods for producing flat surfaces in interconnect structures
JP2013042066A (ja) 半導体装置の製造方法
CN106711131A (zh) 半导体封装件及其形成方法
JP2001015460A (ja) 半導体装置の製造方法
US20150028493A1 (en) Semiconductor device and manufacturing method thereof
JP4698144B2 (ja) 半導体装置の製造方法
JP2001044156A (ja) 半導体装置の製造方法及び化学研磨装置
TW202422782A (zh) 用於混合接合的化學機械拋光
JP2001351923A (ja) パターン形成方法
CN117690866A (zh) 一种用于芯片封装的制作方法及芯片
JP2007194480A (ja) 半導体装置の製造方法
JP2006135059A (ja) 半導体装置の製造方法