TWI518991B - Integrated antenna and integrated circuit components of the shielding module - Google Patents

Integrated antenna and integrated circuit components of the shielding module Download PDF

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Publication number
TWI518991B
TWI518991B TW102105471A TW102105471A TWI518991B TW I518991 B TWI518991 B TW I518991B TW 102105471 A TW102105471 A TW 102105471A TW 102105471 A TW102105471 A TW 102105471A TW I518991 B TWI518991 B TW I518991B
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Taiwan
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antenna
shielding
shielding module
integrated circuit
magnetic conductor
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TW102105471A
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TW201433003A (zh
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Ya Chung Yu
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Sj Antenna Design
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Priority to TW102105471A priority Critical patent/TWI518991B/zh
Priority to US13/942,684 priority patent/US9368866B2/en
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Publication of TWI518991B publication Critical patent/TWI518991B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/52—Means for reducing coupling between antennas; Means for reducing coupling between an antenna and another structure
    • H01Q1/526—Electromagnetic shields
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q13/00—Waveguide horns or mouths; Slot antennas; Leaky-waveguide antennas; Equivalent structures causing radiation along the transmission path of a guided wave
    • H01Q13/08—Radiating ends of two-conductor microwave transmission lines, e.g. of coaxial lines, of microstrip lines
    • H01Q13/085—Slot-line radiating ends
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q19/00—Combinations of primary active antenna elements and units with secondary devices, e.g. with quasi-optical devices, for giving the antenna a desired directional characteristic
    • H01Q19/28—Combinations of primary active antenna elements and units with secondary devices, e.g. with quasi-optical devices, for giving the antenna a desired directional characteristic using a secondary device in the form of two or more substantially straight conductive elements
    • H01Q19/30—Combinations of primary active antenna elements and units with secondary devices, e.g. with quasi-optical devices, for giving the antenna a desired directional characteristic using a secondary device in the form of two or more substantially straight conductive elements the primary active element being centre-fed and substantially straight, e.g. Yagi antenna
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
    • H01Q9/04—Resonant antennas
    • H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Details Of Aerials (AREA)
  • Transceivers (AREA)

Description

整合天線與積體電路元件之屏蔽模組
本案係關於一種天線屏蔽模組，尤指一種整合天線與積體電路元件之屏蔽模組。
隨著無線傳輸系統的蓬勃發展，許多應用產品須具有無線傳輸的性能，藉以滿足消費者之需求。天線是在無線傳輸系統中用來發射與接收電磁波能量的重要元件，若是缺少天線，則無線傳輸系統將會無法發射與接收資料，且其更是攸關於系統之整體性能的主要構成要件。目前較通用的天線頻帶規範有IEEE 802.11以及藍芽通訊(IEEE 802.15.1)等，其中802.11又可分為802.11a、802.11b及802.11g。802.11a規範在5 GHz頻帶，而802.11b、802.11g及802.11n規範在2.4 GHz頻帶，藍芽通訊工作即於2.4 GHz頻帶。而高畫質(Full high definition，Full HD)1080P影音高速傳輸應用(如無線千兆位元(Wireless Gigabit，Wigig)與無線高畫質(Wireless high definition，Wireless HD))之頻帶在60 GHz，且需具有20 Gbit/sec之資料傳輸率(data rate)，是未來行動通訊裝置中必備的傳輸模組，同時也被納入IEEE 802.11ad規範中，而與802.11b/g/n規範並駕齊驅。
由於60 GHz之訊號在大氣中容易被氧氣吸收而使強度衰減，所以只能進行短距離(小於10公尺)之訊號傳輸，此將影響資料傳輸率與應用情境，故其無線傳輸系統中的高頻射頻積體電路(Integrated Circuit,IC)元件特性與天線輻射型態及效率就格外重要。一般而言，如低雜訊放大器(Low Noise Amplifier，LNA)、功率放大器(Power Amplifier，PA)、 混合器(Mixer)等積體電路元件皆需利用金屬容器(shielding box)對其進行屏蔽封裝，以確保天線之訊號傳輸不受外部雜訊與電磁輻射之干擾。
多數天線都被配置於射頻積體電路元件週遭，且必須要留有一淨空區域來維持天線之電磁特性。由於未來智慧型行動通訊裝置之內部空間有限，若天線仍以淨空效能、積體電路元件仍維持傳統之金屬封裝方式來對外界之電磁干擾進行屏蔽，則勢必大量佔據行動通訊裝置之電路基板的空間，而增加產品的複雜度、成本與體積。此外，現有行動通訊裝置包含許多離散式被動元件(discrete passive component)，且當通訊協定不斷擴充時，天線數量也會隨之增加，此將使需進行屏蔽封裝之面積或體積明顯增加。當為縮減電路基板之體積而使產品符合輕薄短小之趨勢時，將使行動通訊裝置之整體效能受到影響，增加天線裝置與電路基板整合之難度。因此，需要一種可同時整合天線與積體電路元件(IC晶片)之屏蔽模組。
爰是之故，申請人有鑑於習知技術之缺失，發明出本案「整合天線與積體電路元件之屏蔽模組」，用以改善上述習用手段之缺失。
本發明係有關於一種整合天線與積體電路元件之屏蔽模組，其天線具有端點式(endfired)或側面式(broadside)之輻射場型，而積體電路元件為一射頻積體電路晶片或一離散式被動元件，封裝於由人造磁導體基板之共用接地面(ground plane)與複數導孔(via hole)所形成之屏蔽槽內。利用天線形成於積體電路元件之上方，可減少積體電路元件之封裝面積，以達到降低成本之目的。此外，本發明之整合天線與積體電路元件之屏蔽模組能維持天線之效能，同時提供天線 與積體電路元件間之抗電磁輻射干擾機制，屏蔽積體電路元件對天線訊號傳輸之影響。
本發明之一目的係提供一種整合天線與積體電路元件之屏蔽模組，包含一人造磁導體(artificial magnetic conductor，AMC)基板、一天線、一共用接地面、複數第一導孔、一屏蔽槽、複數第二導孔及一積體電路元件。人造磁導體基板具有一第一表面及相對於第一表面之一第二表面；天線係設於人造磁導體基板之第一表面上；共用接地面係設於人造磁導體基板之第一表面與第二表面之間；複數第一導孔形成於人造磁導體基板之第一表面與共用接地面之間；屏蔽槽係凹設於人造磁導體基板之第二表面，且其一端與共用接地面相通；複數第二導孔形成於共用接地面與第二表面之間，並環繞屏蔽槽；積體電路元件係容設於第二表面之屏蔽槽內，其一端以一覆晶封裝(flip chip)方式與共用接地面電連接。天線以人造磁導體基板之共用接地面及複數第一導孔為間隔而形成於屏蔽槽之該端、複數第二導孔及積體電路元件之該端上方並與積體電路元件屏蔽。
關於本發明之優點與精神，可以藉由以下的實施方式及所附圖式得到進一步的瞭解。
1‧‧‧屏蔽模組
3‧‧‧人造磁導體基板
5‧‧‧第一表面
7‧‧‧第二表面
9‧‧‧天線
11‧‧‧共用接地面
13‧‧‧第一導孔
15‧‧‧屏蔽槽
17‧‧‧積體電路元件
19‧‧‧第二導孔
21‧‧‧焊接元件
23‧‧‧印刷電路板
H1、H2‧‧‧高度
A‧‧‧方向
D1、D2‧‧‧距離
第1圖：本發明一較佳實施例之整合天線與積體電路元件之屏蔽模組之局部剖面示意圖。
第2圖：本發明之第1圖中A視角方向之局部視圖。
請參閱第1圖，其係本發明一較佳實施例之整合天線與積體電路元件之屏蔽模組之局部剖面示意圖。根據第1 圖，本發明之整合天線與積體電路元件之屏蔽模組1包含一人造磁導體基板3、一天線9、一共用接地面11、複數第一導孔13、一屏蔽槽15、複數第二導孔19及一積體電路元件17。人造磁導體基板3具有一第一表面5及相對於第一表面5之一第二表面7。人造磁導體基板3為一低溫共燒陶瓷(Low-Temperature Cofired Ceramics，LTCC)基板或一多層印刷電路板(Multilayer Printed Circuit Board)。天線9係設於人造磁導體基板3之第一表面5上，其具有V頻帶。天線9可以是中心、頻率等於或大於60GHZ之漸進式槽孔天線(tapered slot antenna)或八木天線(yagi antenna)，其輻射場型為端射式輻射場型(endfired radiation pattern)且平行於人造磁導體基板3。共用接地面11係設於人造磁導體基板3之第一表面5與第二表面7之間。天線9亦可以是共用接地面11與一貼片天線(patch antenna)之組合，其中心頻率等於或大於60 GHz，且其輻射場型為垂直於人造磁導體基板3之側向輻射場型(broadside radiation pattern)。
復根據第1圖，複數第一導孔13形成於人造磁導體基板3之第一表面5與共用接地面11之間，其高度H1小於四分之一波長的奇數倍。屏蔽槽15係凹設於人造磁導體基板3之第二表面7，且其一端與共用接地面11相通。複數第二導孔19形成於共用接地面11與第二表面7之間，並環繞屏蔽槽15，其高度H2小於四分之一波長的奇數倍。積體電路元件17係容設於第二表面7之屏蔽槽15內，其一端以一覆晶封裝方式，利用複數焊接元件21與共用接地面11電連接。積體電路元件17可以是一射頻(radio frequency)積體電路晶片或一離散式被動元件。據此，天線9以人造磁導體基板3之共用接地面11及複數第一導孔13為間隔而形成於屏蔽槽15之該端、複數第二導孔19及積體電路元件17之該端上方並與積體電路元件17屏蔽。本發明之整合天線與積體電路元件之屏蔽模組1接著可利用複數焊接元件21而與一印刷電路 板(Printed Circuit Board，PCB)23電連接。
請同時參閱第1及2圖，第2圖為本發明之第1圖中A視角方向(即人造磁導體基板3之第二表面7)之局部視圖。第2圖與第1圖中相同之元件具有相同之功效並使用相同之參照符號，於此不再贅述。根據第2圖，積體電路元件17係容設於由人造磁導體基板3之共用接地面11及複數第二導孔19所形成之屏蔽槽15內。複數第二導孔19間之距離D1小於四分之一波長的奇數倍；積體電路元件17與屏蔽槽15之槽壁間的距離D2小於四分之一波長的奇數倍。
綜上所述，依據本發明之整合天線與積體電路元件之屏蔽模組，其包含一人造磁導體基板、一天線、一共用接地面、複數第一導孔、一屏蔽槽、複數第二導孔及一積體電路元件。積體電路元件係容設於由人造磁導體基板之共用接地面及複數第二導孔所形成之屏蔽槽內，其一端以一覆晶封裝方式與共用接地面電連接。天線係利用人造磁導體基板之共用接地面及複數第一導孔而與積體電路元件隔絕。據此，天線係以人造磁導體基板之共用接地面及複數第一導孔為間隔而形成於屏蔽槽、複數第二導孔及積體電路元件之上方，如此可縮減積體電路元件之封裝面積及成本，同時可屏蔽外界雜訊與電磁輻射之干擾，維持天線及高頻積體電路元件之特性與效能。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明之範圍，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
1‧‧‧屏蔽模組
3‧‧‧人造磁導體基板
5‧‧‧第一表面
7‧‧‧第二表面
9‧‧‧天線
11‧‧‧共用接地面
13‧‧‧第一導孔
15‧‧‧屏蔽槽
17‧‧‧積體電路元件
19‧‧‧第二導孔
21‧‧‧焊接元件
23‧‧‧印刷電路板
H1、H2‧‧‧高度
A‧‧‧方向

Claims (16)

  1. 一種整合天線與積體電路元件之屏蔽模組，其包含：一人造磁導體(artificial magnetic conductor，AMC)基板，具有一第一表面及相對於該第一表面之一第二表面；一天線，設於該人造磁導體基板之該第一表面上；一共用接地面，設於該人造磁導體基板之該第一表面與該第二表面之間；複數第一導孔(via holes)，形成於該人造磁導體基板之該第一表面與該共用接地面之間；一屏蔽槽，凹設於該人造磁導體基板之該第二表面，且該屏蔽槽之一端與該共用接地面相通；複數第二導孔，形成於該共用接地面與該第二表面之間，並環繞該屏蔽槽；及一積體電路元件，容設於該第二表面之該屏蔽槽內，且該積體電路元件之一端以一覆晶封裝(flip chip)方式與該共用接地面電連接；其中，該天線以該人造磁導體基板之該共用接地面及該些第一導孔為間隔而形成於該屏蔽槽之該端、該些第二導孔及該積體電路元件之該端上方並與該積體電路元件屏蔽。
  2. 如申請專利範圍第1項所述之屏蔽模組，其中該人造磁導體基板為一低溫共燒陶瓷(Low-Temperature Cofired Cerarmics，LTCC)基板或一多層印刷電路板(Multilayer Printed Circuit Board)。
  3. 如申請專利範圍第1項所述之屏蔽模組，其中該天線具有V頻帶。
  4. 如申請專利範圍第1項所述之屏蔽模組，其中該天線為漸進式槽孔天線(tapered slot antenna)或八木天線(yagi antenna)。
  5. 如申請專利範圍第4項所述之屏蔽模組，其中該天線之中心頻率等於或大於60 GHz。
  6. 如申請專利範圍第4項所述之屏蔽模組，其中該天線之輻射場型為端射式輻射場型(endfired radiation pattern)。
  7. 如申請專利範圍第4項所述之屏蔽模組，其中該天線之輻射場型平行於該人造磁導體基板。
  8. 如申請專利範圍第1項所述之屏蔽模組，其中該天線為該共用接地面與一貼片天線(patch antenna)之組合。
  9. 如申請專利範圍第8項所述之屏蔽模組，其中該天線之中心頻率等於或大於60 GHz。
  10. 如申請專利範圍第8項所述之屏蔽模組，其中該天線之輻射場型為側向輻射場型(broadside radiation pattern)。
  11. 如申請專利範圍第8項所述之屏蔽模組，其中該天線之輻射場型垂直於該人造磁導體基板。
  12. 如申請專利範圍第1項所述之屏蔽模組，其中該些第一導孔之高度小於四分之一波長的奇數倍。
  13. 如申請專利範圍第1項所述之屏蔽模組，其中該些第二導孔之高度小於四分之一波長的奇數倍。
  14. 如申請專利範圍第1項所述之屏蔽模組，其中該些第二導 孔間之距離小於四分之一波長的奇數倍。
  15. 如申請專利範圍第1項所述之屏蔽模組，其中該積體電路元件為一射頻(radio frequency)積體電路晶片或一離散式被動元件(discrete passive component)。
  16. 如申請專利範圍第1項所述之屏蔽模組，其中該積體電路元件與該屏蔽槽間之距離小於四分之一波長的奇數倍。
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