JPH0344067A - 半導体基板の積層方法 - Google Patents

半導体基板の積層方法

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Publication number
JPH0344067A
JPH0344067A JP1179268A JP17926889A JPH0344067A JP H0344067 A JPH0344067 A JP H0344067A JP 1179268 A JP1179268 A JP 1179268A JP 17926889 A JP17926889 A JP 17926889A JP H0344067 A JPH0344067 A JP H0344067A
Authority
JP
Japan
Prior art keywords
thin film
layer
film device
forming
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1179268A
Other languages
English (en)
Inventor
Yoshihiro Hayashi
喜宏 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1179268A priority Critical patent/JPH0344067A/ja
Priority to US07/551,095 priority patent/US5087585A/en
Publication of JPH0344067A publication Critical patent/JPH0344067A/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7422—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7434—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used in a transfer process involving at least two transfer steps, i.e. including an intermediate handle substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （産業上の利用分野ン 本発明は半導体基板の積層方法に関するものであり、詳
しくは複数の薄膜デバイスを半導体装置上に順次積層す
る半導体基板の積層方法に関するものである。
（従来の技術） ３次元ＬＳＩを製造する方法として、従来、ＭＯＳトラ
ンジスタ等のデバイスがすでに形成されている半導体基
板を張り合わせる方法が知られている（安本雅昭ら、Ｓ
ｅｍ１ｃｏｎｄｕｃｔｏｒ　ｗｏｒｌｄ、　５．、　ｐ
ｐｌ−８）。この方法ではまず第３図（ａ）に示したよ
うにデバイス層（３１）の上に金バンプ等の接続電極（
３２）が形成された第１の半導体基板（３３）及び第２
の半導体基板（３４）を用意する。その後、第３図（ｂ
）に示したようにデバイス形成筒がそれぞれ向かい合う
ように、すなわちデバイス上に形成されている接続電極
がお互いに向かい合うように２枚の基板を位置合わせし
て接合することにより２層構造の３次元ＬＳＩを得る。
（発明が解決しようとする課題） しかしながら、上述した積層方法では３層以上のデバイ
スを積層することはできない。あえて上述した積層方法
により３層以」二のデバイスを積層するには、第３図（
Ｃ）に示したように、張り合わせた第２の半導体基板（
３４）の裏面より選択ポリッシング（浜口恒夫ら、応用
物理、５６［１１］ｐｐ１４８０（１９８７））を行い
、薄膜デバイス（３５）を作威し、さらにその裏面に第
３層目デバイスを接続するための裏面側接続電極（３６
）を形成しなければならない。すなわち、この方法によ
り３層以上のデバイスを接続するためには、２層以上の
デバイスが既に積層された半導体基板に対して、半導体
基板を薄膜化するための研磨工程を行わなければならず
、研磨の際に加わる応力かみ接続電極部に作用し接続不
良を導く恐れがある。
本発明の目的は２層以上のデバイスが既に積層された基
板にさらにデバイスを積層するときこの基板を研磨・薄
膜化する工程を必要としない積層方法を提供することに
ある。
（課題を解決するための手段） 本発明は、以下の（ア）に示す積層用薄膜デバイス形成
プロセスにより薄膜デバイスの表面およびその裏面にそ
れぞれ接続電極を形成し、さらに以下の（イ）に示す薄
膜デバイス積層プロセスにより第１の半導体基板に形成
された第１層目あるいは第２層目デバイス上に前記薄膜
デバイスを順次積層することを特徴とする半導体基板の
積層方法である。
（ア）積層用薄膜デバイス形成プロセス半導体基板にデ
バイスを形成する工程と、前記デバイス」二に表面側接
続電極を形成する工程と、前記半導体基板のデバイス形
成形成面側に支持基板を接着する工程と、前記半導体基
板を薄膜化することにより薄膜デバイスを形成する工程
と、前記薄膜デバイス上に裏面絶縁膜を形成する工程と
、前記薄膜デバイスに裏面側接続電極を形成する工程と
により、支持基板に接着された状態の薄膜デバイス表面
及びその裏面にそれぞれ接続電極を形成するプロセス。
（イ）薄膜デバイス積層プロセス 第１の半導体基板に第１層目あるいは第２層目デバイス
を形成する工程と、このデバイス上に表面側接続電極を
形成する工程と、（ア）に示した薄膜デバイス形成プロ
セスにより得られた第２層目あるいは第３層目薄膜デバ
イスの裏面側接続電極と第１層目あるいは第２層目デバ
イス上の表面側接続電極とを位置合わぜして接続する工
程と、前記薄膜デバイス上に接着されている支持基板お
よび接着剤を除去する工程と、前記第２層目あるいは第
３層目デバイス上の表面側電極と（ア）に示した薄膜デ
バイス形成プロセスにより得られた第３層目薄膜デバイ
スの裏面側接続電極とを位置合わせして接続する工程と
、前記第３層目薄膜デバイス上に接着されている支持基
板および接着剤を除去する工程。
（作用） 本発明による半導体基板の積層方法では、デバイス表面
およびその裏面に接続電極がすでに形成されている薄膜
デバイスを積層単位として第１層目デバイス上に順次積
層するため、デバイスが積層されている構造を有する半
導体基板を研磨・薄膜化する工程を必要としない。すな
わち、積層されたデバイス間の接続電極部に研磨の応力
が作用するといった問題は生じ得ない。
（実施例） 以下、この発明の実施例としてシリコン基板に形成され
たデバイスを３層積層する場合を例にとって説明する。
本発明による半導体基板の積層方法は積層用薄膜デバイ
ス形成プロセスと薄膜デバイス積層プロセスからなる。
第１図（ａ）〜（ｅ）に積層用薄膜デバイス形成プロセ
スを説明するための製造工程断面図を示す。積層用薄膜
デバイス形成プロセスでは、まず通常のＬＳＩ製造工程
によりシリコン基板（１１）にデバイス（１２）を形成
した（第１図（ａ））後、前記デバイス（１２）上に表
面側後接続電極としてタングステン等の高融点金属バン
プ（１３）を形成する（＄１図（ｂ））。その後、接着
剤（１４）を用いてデバイス（１２）上に支持基板（１
５）としてシリコン基板を接着しく第１図（Ｃ））、さ
らに選択ポリッシング法によりシリコン基板（１１）を
研磨することにより薄膜デバイス（１６）を得る（第１
図（ｄ））。なお、薄膜デバイスは支持基板に接着され
ているため、機械的および電気的に破壊される心配はな
い。しかる後、薄膜デバイス（１６）にＳｉＯ２等の裏
面絶縁膜（１７）を形成し、さらに裏面側接続電極とし
て前記裏面絶縁膜（１７）の開口部にＩｎ等の低融点金
属を埋め込んだ低融点金属プール（１８）を形成する。
（第１図（ｅ））。
上述した積層用薄膜デバイス形成プロセスにより、薄膜
デバイスの表面およびその裏面に接続電極を形成し、以
下に述べる薄膜デバイス積層プロセスにより第１の半導
体基板に形成された第１層目デバイス上に順次薄膜デバ
イスを積層する。
第２図に（ａ）〜（ｇ）に、薄膜デバイス積層プロセス
を説明するための製造工程断面図を示す。まず、第１の
シリコン基板（２１）に第１層目デバイス（２２）を形
成し、さらに前記第１層目デバイス（２２）上に表面側
接続電極として高融点金属バンプ（１３）を形成する（
第２図（ａ））。このあと、前記積層用薄膜デバイス形
成プロセスにより得られた第２層目薄膜デバイス（２３
）裏面に形成された低融点金属プール（１８）と前記第
１層目デバイス（２２）上の高融点金属バンプ（１３）
とが向かい合うように位置合わぜを行う（第２図（ｂ）
）。なお、上述した位置合わせには支持基板（１５Ｘ本
実施例ではシリコン）を透過する赤外線顕微鏡を利用す
る。
しかる後、１層目デバイス（２２）上の高融点金属バン
プ（１３）が第２層目薄膜デバイス（２３）裏面に形成
されている低融点金属プール（１８）に挿入されるまで
１層目デバイスと第２層目薄膜デバイスとを密着させ、
接続する（第２図（Ｃ））。なお、上述したデバイスの
接続温度は低融点金属プールに埋め込んだ金属の融点よ
りも高い温度、たとえはゴロを埋め込んだ場合には２０
０°Ｃ〜３０００Ｃである。その後、エツチングにより
支持基板（１５）を除去し、さらに酸素プラズマ処理に
より接着剤（１４）を除去する（第２図（ｄ））。
さらに、前記した積層用薄膜デバイス形成プロセスによ
り得られた第３層目薄膜デバイス（２４）を用意し、裏
面に形成された低融点金属プール（１８）と第２層目薄
膜デバイス上の高融点金属バンプ（１３）とが向かい合
うように位置合わせを行い（第２図（ｅ））、密着・接
続しく第２図（ｆ））、さらに第３層目薄膜デバイス（
２４）上の支持基板（１５）および接着剤（１４）を除
去する（第２図（ｇ））。
上述した一連の工程により、第１層目薄膜デバイスと第
２層目薄膜デバイスと第３層目薄膜デバイスとが接続さ
れた構造を有する積層デバイスを得る。なお、上述した
実施例ではデバイスを３層積層する場合を述べたが、本
発明によれば４層以上のデバイスを積層しうろことは自
明である。また、上述した実施例では、デバイスを接続
するための接続電極として高融点金属バンプと低融点金
属プールをそれぞれデバイスの表面およびその奥面に形
成し、バンプ・プール間の゛ろう着″によりデバイスを
接続したが、その他のデバイス接続方法、例えば金属バ
ンプと金属バンプとの熱圧着等を利用できることも自明
である。
さらに、本発明によればシリコン基板以外の半導体基板
に形成されたデバイスや絶縁性基板に形成された配線層
を積層することが可能であることは説明するまでもない
。
（発明の効果） 以上詳述したように、本発明による半導体基板の積層方
法では、デバイスの主なる２面、すなわちデバイス表面
およびその裏面に接続電極がすでに形成されている薄膜
デバイスを積層単位として第１層目あるいは第２層目デ
バイス上に順次積層するため、デバイスが積層されてい
る構造を有する半導体基板を研磨・薄膜化する工程を必
要としない。このため、積層されたデバイス間の接続電
極部に研磨の際に生じる応力が作用するといった問題は
生じ得ない。
さらに、本発明による半導体姑仮の積層方法は薄膜デバ
イス形成プロセスと薄膜デバイス積層プロセスとが完全
に分離されている。このため、予め複数のデバイスのシ
ステム・回路・マスクの設計及び薄膜デバイス形成プロ
セスまでを並列処理で用意しておいた後、薄膜デバイス
積層プロセスにより薄膜デバイスを順次積層するといっ
た一部並列工程処理が可能となり、積層数が増加しても
ＴＡＴが著しく長期化する恐れもない。
【図面の簡単な説明】
第１図は本発明に係る半導体基板の積層方法のうち積層
用薄膜デバイス形成プロセスの一実施例を説明するため
の製造工程断面図、第２図は本発明に係る薄膜デバイス
の積層プロセスを説明するため（１１） の製造工程断面図、第３図は従来の半導体丞仮の積層方
法を説明するための工程断面図である。 １１・・・シリコン基板、１２・・・デバイス、１３・
・、高融点金属バンプ、１４・・・接着剤、１５・１．
支持基板、１６・・・薄膜デバイス、１７−１．裏面絶
縁膜、１８・、・低融点金属プール、２１・・・第１の
シリコン基板、２２・・・第１層目デバイス、２３・・
・第２層目薄膜デバイス、２４・・・第３層目薄膜デバ
イス、３１・・・デバイス層、３２・・・接続電極、３
３・・・第１の半導体基板、３４・・・第２の半導体基
板、３５・、・薄膜デバイス、３６１３．裏面側接続電
極。

Claims (1)

  1. 【特許請求の範囲】 以下の（ア）に示す積層用薄膜デバイス形成プロセスに
    より薄膜デバイスの表面およびその裏面にそれぞれ接続
    電極を形成し、さらに以下の（イ）に示す薄膜デバイス
    積層プロセスにより第１の半導体基板に形成された第１
    層目あるいは第２層目デバイス上に前記薄膜デバイスを
    順次積層することを特徴とする半導体基板の積層方法。 （ア）半導体基板にデバイスを形成する工程と、前記デ
    バイス上に表面側接続電極を形成する工程と、前記半導
    体基板のデバイス形成面側に支持基板を接着する工程と
    、前記半導体基板を薄膜化することにより薄膜デバイス
    を形成する工程と、前記薄膜デバイス上に裏面絶縁膜を
    形成する工程と、前記薄膜デバイスに裏面側接続電極を
    形成する工程とにより、支持基板に接着された状態の薄
    膜デバイス表面及びその裏面にそれぞれ接続電極を形成
    するプロセス。 （イ）第１の半導体基板に第１層目あるいは第１、第２
    層目デバイスを形成する工程と、このデバイス上に表面
    側接続電極を形成する工程と、（ア）に示した薄膜デバ
    イス形成プロセスにより得られた第２層目あるいは第３
    層目薄膜デバイスの裏面側接続電極と第１層目あるいは
    第２層目デバイス上の表面側接続電極とを位置合わせし
    て接続する工程と、前記薄膜デバイス上に接着されてい
    る支持基板および接着剤を除去する工程と、前記第２層
    目あるいは第３層目デバイス上の表面側電極と（ア）に
    示した薄膜デバイス形成プロセスにより得られた第３層
    目薄膜デバイスの裏面側接続電極とを位置合わせして接
    続する工程と、前記第３層目薄膜デバイス上に接着され
    ている支持基板および接着剤を除去する工程。
JP1179268A 1989-07-11 1989-07-11 半導体基板の積層方法 Pending JPH0344067A (ja)

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US07/551,095 US5087585A (en) 1989-07-11 1990-07-11 Method of stacking semiconductor substrates for fabrication of three-dimensional integrated circuit

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JP1179268A JPH0344067A (ja) 1989-07-11 1989-07-11 半導体基板の積層方法

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