JPS6130059A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

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Publication number
JPS6130059A
JPS6130059A JP15059884A JP15059884A JPS6130059A JP S6130059 A JPS6130059 A JP S6130059A JP 15059884 A JP15059884 A JP 15059884A JP 15059884 A JP15059884 A JP 15059884A JP S6130059 A JPS6130059 A JP S6130059A
Authority
JP
Japan
Prior art keywords
layer
bumps
circuit boards
metal
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15059884A
Other languages
English (en)
Inventor
Masaaki Yasumoto
安本　雅昭
Hiroshi Hayama
浩 葉山
Tadayoshi Enomoto
榎本　忠儀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP15059884A priority Critical patent/JPS6130059A/ja
Priority to EP19850108891 priority patent/EP0168815B1/en
Priority to DE8585108891T priority patent/DE3586732T2/de
Priority to US06/755,987 priority patent/US4612083A/en
Publication of JPS6130059A publication Critical patent/JPS6130059A/ja
Pending legal-status Critical Current

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    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P10/00—Bonding of wafers, substrates or parts of devices
    • H10P10/12—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates
    • H10P10/128—Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates by direct semiconductor to semiconductor bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
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    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7438—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
    • H—ELECTRICITY
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    • H10W72/00—Interconnections or connectors in packages
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    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01251—Changing the shapes of bumps
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    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
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    • H10W80/312—Bonding techniques, e.g. hybrid bonding characterised by the direct bonding of electrically conductive pads
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    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路に係）、更に詳しくは、機能
が異なる半導体集積回路基板を積層して得られる多層半
導体集積回路の製造方法に関する。
〔従来技術とその問題点〕
多層半導体集積回路は、トランジスタ、ダイオード、抵
抗、容量等の機能菓子と各機能素子間を接続する金属配
線等が平面上に集積化された能動層を複数層積層した構
造を持ち、単一能動層からなる現在良く知られた二次元
半導体集積回路に比べて、集積回路の集積密度の向上や
、多機能化が期待できる。多層半導体集積回路の製造方
法として現在知られているものは、（１）第１の能動層
上に形成された絶縁膜上に、レーザビーム、電子ビーム
、あるいはストリップヒータ等を用いてアニールし再結
晶化させたポリシリコン層（ＳＯＩ構造）を形成し、（
２）このポリシリコン層上に第２の能動層を形成し、以
下、これらの工程を繰ル返すことによシ多層化する方法
である（　Ｓ、Ｋａｗａｍｕｒａ　。
ＩＥＤＭ　Ｔｅｃｈｎｉｃａｌ　ＤｉｇｅｓｔＢ、　Ｐ
Ｐ　、　３６４　、１９８３）。
しかしこの方法には、能動層を順に形成するため、製造
期間が長くなる２歩留シの低下が激しい９等の短所があ
る。更には、各能動層の表面を平担にする技術、既に形
成されている下層の能動層の素子特性を劣化させずに新
しく積層する能動層を作製する低温プロセス技術、ある
いは大面積のＳＯＩ構造を形成する技術、等新たに開発
を必要とする新技術が多い。
〔本発明の目的〕
本発明は、従来の多層半導体集積回路の製造方法の欠点
を除去できる多層半導体集積回路の製造方法を提供する
ことを目的とする。
〔発明の構成〕
本発明に依れば１表面に絶縁層が形成された半導体装置
を半導体基板上に形成し、前記絶縁層の一部分を貫通す
る金属バンプを形成して得られる半導体回路基板を２枚
準備し、一方あるいは両方の半導体回路基板の表面に該
金属バンプを十分に覆い、しかも表面がほぼ平担になる
膜厚の絶縁性樹脂接着剤層を回転塗布し、しかる後、前
記金属バンプの表面が現われるまで、該絶縁性樹脂接着
剤層を一様にエツチングし、次にとれら２枚の半導体回
路基板表面を互い対向させた状態で、両半導体回路基板
上の金属バンプが互−に一致するようにして両半導体回
路基板を接触させ、咳絶縁性樹脂接着剤層を加熱、乾燥
させることＫより、両半導体回路基板を接着させ、しか
も咳金属バンプ同志を電気的に接続させることを特徴と
する半導体装置の製造方法が得られる。
〔実施例〕
以下、図面を用いて本発明の実施例を詳細に説明する。
第１図（ａ）〜（ｆ）は本発明を用い声多層半導体集積
回路の製造方法の流れである。第１図（ａ）は。
シリコン、ガリウム砒素等の半導体や二酸化シリコン、
サファイア等の絶縁体からなる基板１０１上Ｋ、機能素
子、およびこれらを互いに接続するアルミニウム等の金
属配線からなる能動層１０２と、１０２を保護する二酸
化シリコン等の絶縁層１０３を形成した半導体回路基板
１を示したものである。この半導体回路基板１は、通常
の二次元集積回路を製造するプロセス、例えばＮＭＯＳ
プロセス、ＰＭＯＳプロセス、ＣＭＯＳプロセス、バイ
ポーラプロセス、等によシ作製される。
次に第１図中）に示すように、ｌ上の１０３の一部に開
口部を設け、この開口部に金等の金属バンプ１０４′ｆ
ｔ：形成する。第１図（ｂ）を形成する方法として、与
真喰刻法を用いてパターン化されたフォトレジスＩｆマ
スクとし、７ツ酸等の薬品を用いて二酸化シリコン等の
１０３を開口した後、真空蒸着等により１０３の膜厚よ
シ厚い、金等の金属膜を形成し、最後にフォトレジスト
を除去（リフトオツ７法と言う）し、金属バンプ１０４
ｔ−形成する方法等がある。尚、１０４は能動層１０２
と機能的に接続されている。
この後、第１図（ｅ）に示すように、絶縁層１０３、お
よび１０４上Ｋ、１０４を完全に覆い、しかも表面が殆
ど平担化される膜厚のポリイミド系樹脂等の絶縁性樹脂
接着剤をスピン塗布する。例えば。
金属バンプの高さを能動層１０２の表面から測って１．
５μｍとし、ポリイミド系樹脂の膜厚が２．５μｍ程度
になるように、スピン速度やスピン時間を選ぶと、塗布
後の表面はは埋平担になる。次に酸素プラズマ中等で絶
縁性樹脂接着剤層を表面から一様に金属バンプ１０４の
表面が現われるまでエツチングする。
この結果、第１図（ｄ）Ｋ示されているように、金属バ
ンプ１０４が露出し、それ以外の部分が平担な絶縁性樹
脂接着剤層１０５でおおわれた半導体回路基板１が得ら
れる。以上の工程を経た半導体回路基板を２枚準備し、
一方の表面を上向きに、他方の表面を下向きにし、これ
らの半導体回路基板に設けられた金属バッグの位置が元
いに一致するように目合せを行なう〔第１図（ｅ）〕。
以下の説明では、下の半導体回路基板を第１の回路基板
１５０゜上の半導体回路基板を第２の回路基板１５１と
称する。図面番号は、１５０が第１図（ｄ）の番号を。
１５１が第１図（ｄ）の番号にダッシュがついた本のを
使用する。
目合せ方法の１例として、縮少投影露光機等に用いられ
ているオフ・アクシス法がある。目合せ装置内に２か所
の目合せ場所を設ける。それぞれの目合せ場所にはチッ
プあるいはウニ／１−を固定するステージと目合せ基準
マークが設けられている。２か所の目合せ基準マークの
距離はあらかじめ決められている。まず、１５０．１５
１４’それぞれのステージに固定した後、ステージを微
動させ、それぞれの目合せ基準マークと一致させる。次
に、一方、例えば１５０が固定されているステージを目
合せ基準マーク間の距離だけ移動させ、１５０が１５１
の直下へ来るようにする。この結果、１５０と１５１は
ステージを移動させる機械的な精度内で目合せされる。
最後に、１５０と１５１の平面方向の相対位置を保った
状態で、１５０と１５１を接触、加熱し。
１０５．１０５’を乾燥させることにより、１０５と１
０５′を接着させ、第１図（ｆ）に示されている多層半
導体集積回路が実現できる。この時、金属バンプ１０４
，１０４’も接触し、１５０と１５１は、１０４゜１０
４′を介して電気的に接続される。１０５，１０５′が
ポリイミド系樹脂の場合、加熱する温度は２５０〜４０
０℃１時間は２０〜６０分である。加熱時に１５０と１
５１′の間にある一定の圧力を加えれば、１０４と１０
４″は互いに拡散溶接され、１０４，１０４’間の電気
抵抗が非常に小さくなる他、１５０と１５１′の接着力
も強化される。
第２図は、本発明の製造方法を用いて作製された２層半
導体集積回路の一例である。２０１は第１の回路基板（
以下下層と称する）２５０のシリコン等の基板、２０２
は二酸化シリコン等の絶縁膜。
２２０は、ソース、ドレイン２０３，２０５　、チャネ
ル２０４．ゲート２０６がＳＯＩ構造上に作製された下
層の薄膜トランジスタである。２０７は下層の金属配線
、２０８は、下層の絶縁層である。また、２０９は、下
層の金属バンプ、２１０は下層の絶縁性樹脂接着剤層で
ある。尚、第２の回路基板（以下、上層と称する）２５
１のうち、下層と同一素子は、下層の素子番号にダッシ
ュが付けられている。
第２図に示されているように、上下層の薄膜トランジス
タ、２２０，２２０’のソース、ドレイン２０５゜２０
５′は、金属配線、２０７，２０７’および金属バンプ
２０９，２０９’ｆｆｉ介して接続され、目的とする回
路を形成することができる。
第２図は、２層半導体集積回路について示されているが
、上下層に、それぞれ、従来方式を用いて作製されたに
層、に′層半導体集積回路を用いれば、（ｋ十に’）層
の多層集積回路も実現できる。
あるいは、第２図において、上層の絶縁膜２０２″を貫
通する垂直配線ｔ−Ｓらかじめ設けておき、本発明を用
いて上下層を積層した後、上層の基板２０１′を除去し
、再び本発明を用いて、第３の回路基板を積層する工程
を繰シ返せば３層以上の多層半導体集積回路も実現でき
る。３層積層した場合の一例を第３図に示す、３０１は
、第１の回路基板で第２図の２５０に相等する。３０２
は第２の回路基板で第２図の２５１から基板２０１′を
除去したものに相等する。３０１．３０２を構成する素
子名は、第２図のそれと等しい。新しく追加されている
部分は、絶縁［２０２’を貫通する金やアルミニウム等
からなる垂直配線３０４である。３０３は、第３の回路
基板である。３１１は基板、３０５は、絶縁膜。
３０６は薄膜トランジスタ、３０７は、金属配線。
３０８は、絶縁層、３０９は、金属バンク、３１０は、
第３の回路基板上に形成された絶縁性樹脂接着剤層であ
る。、３０６は、３０７．３０９，２０９’を介して電
気的に、２０７′と接続されるから、第１゜第２．第３
の回路基板は、機能的に接続される。
第１図の説明では、絶縁性樹脂接着剤層を第１および第
２の回路基板に形成する場合について説明したが、一方
の回路基板にのみ形成する場合であってもかまわない。
また、第２図、第３図において、各層の回路基板として
ＳＯＩ構造を示したが、これに限るものでない。全く異
なる基板、たとえばシリコン基板とＳＯ８基板、シリコ
ン基板とガリウム砒素基板でもかまわない。あるいは、
全く異なる機能、例えば、ＣＭＯ８集積回路とイメージ
センサ、信号処理用集積回路と発光、受光菓子との組み
合わせ等でもよい。また、第１の回路基板と第２の回路
基板のサイズが異なってもかまわない。例えば、ウェハ
ースケール集積回路上に複数個の小さなチップを積層す
る場合も考えられる。
〔発明の効果〕
本発明に依れば、各層の能動層は並行して同時に作製で
きるから従来の多層半導体集積回路の製造方法に比べて
製造期間が短縮できる。また、各層の能動層をあらかじ
め検査し、正常な動作をするもののみ積層すれば歩留シ
の向上が期待できる。
また、レーザアニール技術等による大面積ＳＯＩ製造技
術の開発を待たずして、バルク基板やＳＯ８基板を用い
た多層半導体集積回路が実現できるから、開発スｅ−ド
が早い、また、積層するプロセスが低温プロセスである
。絶縁性樹脂接着剤層を形成する工程で各層の回路基板
表面が平担化される１等、今までの製造方法の欠点を除
去できる。
更には、各層の回路基板の構造、製造プロセスに制限が
ないから、多機能化等、今までの製造方法では、考えら
れなかった応用も可能となる。
【図面の簡単な説明】
第１図（＆）〜（ｆ）は本発明による多層半導体集積回
路の製造方法の流れを説明するための断面図である。１
０１，１０２，１０３，１０４，１０５はそれぞれ、基
板、能動層、絶縁層、金属バンプ、絶縁性樹脂接着剤層
である。また１５０．１５１は、第１の回路基板、第２
の回路基板である。第２図、第３図は、本発明の応用例
の断面図で、それぞれ２層半導体集積回路、３層半導体
集積回路を示したものである。２５０．３０１は第１の
回路基板、２５１゜３０２は第２の回路基板、３０３は
第３の回路基板である。 第１図 第１図 第２図 第３図

Claims (1)

    【特許請求の範囲】
  1. 　表面に絶縁層が設けられた半導体装置を半導体基板上
    に形成し、前記絶縁層の一部分を貫通する金属バンプを
    形成して得られる半導体回路基板を２枚準備し、一方あ
    るいは両方の半導体回路基板の表面に該金属バンプを十
    分に覆い、しかも表面がほぼ平担になる膜厚の絶縁性樹
    脂接着剤層を回転塗布し、しかる後、前記金属バンプの
    表面が現われるまで、該絶縁性樹脂接着剤層を一様にエ
    ッチングし、次にこれら２枚の半導体回路基板表面を互
    い対向させた状態で、両半導体回路基板上の金属バンプ
    が互いに一致するようにして両半導体回路基板を接触さ
    せ、該絶縁性樹脂接着剤層を加熱、乾燥させることによ
    り、両半導体回路基板を接着させ、しかも該金属バンプ
    同志を電気的に接続させることを特徴とする半導体装置
    の製造方法。
JP15059884A 1984-07-20 1984-07-20 半導体装置の製造方法 Pending JPS6130059A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP15059884A JPS6130059A (ja) 1984-07-20 1984-07-20 半導体装置の製造方法
EP19850108891 EP0168815B1 (en) 1984-07-20 1985-07-16 Process for fabricating three-dimensional semiconductor device
DE8585108891T DE3586732T2 (de) 1984-07-20 1985-07-16 Verfahren zum herstellen einer dreidimentionaler halbleiteranordung.
US06/755,987 US4612083A (en) 1984-07-20 1985-07-17 Process of fabricating three-dimensional semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15059884A JPS6130059A (ja) 1984-07-20 1984-07-20 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPS6130059A true JPS6130059A (ja) 1986-02-12

Family

ID=15500377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15059884A Pending JPS6130059A (ja) 1984-07-20 1984-07-20 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US4612083A (ja)
EP (1) EP0168815B1 (ja)
JP (1) JPS6130059A (ja)
DE (1) DE3586732T2 (ja)

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EP0168815A3 (en) 1988-01-20

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