DE3586732T2 - Verfahren zum herstellen einer dreidimentionaler halbleiteranordung. - Google Patents

Verfahren zum herstellen einer dreidimentionaler halbleiteranordung.

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Publication number
DE3586732T2
DE3586732T2 DE19853586732 DE3586732T DE3586732T2 DE 3586732 T2 DE3586732 T2 DE 3586732T2 DE 19853586732 DE19853586732 DE 19853586732 DE 3586732 T DE3586732 T DE 3586732T DE 3586732 T2 DE3586732 T2 DE 3586732T2
Authority
DE
Germany
Prior art keywords
producing
dimensional semiconductor
semiconductor arrangement
arrangement
dimensional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19853586732
Other languages
English (en)
Other versions
DE3586732D1 (de
Inventor
Masaaki Yasumoto
Hiroshi Hayama
Tadayoshi Enomoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
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Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE3586732D1 publication Critical patent/DE3586732D1/de
Publication of DE3586732T2 publication Critical patent/DE3586732T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S148/00Metal treatment
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DE10200399A1 (de) * 2002-01-08 2003-07-24 Advanced Micro Devices Inc Dreidimensional integrierte Halbleitervorrichtung
US6943067B2 (en) 2002-01-08 2005-09-13 Advanced Micro Devices, Inc. Three-dimensional integrated semiconductor devices
DE10200399B4 (de) * 2002-01-08 2008-03-27 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erzeugung einer dreidimensional integrierten Halbleitervorrichtung und dreidimensional integrierte Halbleitervorrichtung
WO2015000527A1 (de) * 2013-07-05 2015-01-08 Ev Group E. Thallner Gmbh Verfahren zum bonden von metallischen kontaktflächen unter lösen einer auf einer der kontaktflächen aufgebrachten opferschicht in mindestens einer der kontaktflächen
US9640510B2 (en) 2013-07-05 2017-05-02 Ev Group E. Thallner Gmbh Method for bonding metallic contact areas with solution of a sacrificial layer applied on one of the contact areas

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EP0168815A3 (en) 1988-01-20
EP0168815A2 (de) 1986-01-22
US4612083A (en) 1986-09-16
DE3586732D1 (de) 1992-11-12
EP0168815B1 (de) 1992-10-07
JPS6130059A (ja) 1986-02-12

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