DE3483280D1 - Verfahren zum herstellen einer mehrschicht-halbleiteranordnung. - Google Patents

Verfahren zum herstellen einer mehrschicht-halbleiteranordnung.

Info

Publication number
DE3483280D1
DE3483280D1 DE8484105127T DE3483280T DE3483280D1 DE 3483280 D1 DE3483280 D1 DE 3483280D1 DE 8484105127 T DE8484105127 T DE 8484105127T DE 3483280 T DE3483280 T DE 3483280T DE 3483280 D1 DE3483280 D1 DE 3483280D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor arrangement
multilayer semiconductor
multilayer
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484105127T
Other languages
English (en)
Inventor
Shinji C O Patent Divi Taguchi
Homare C O Patent Di Matsumura
Kenji C O Patent Divi Maeguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3483280D1 publication Critical patent/DE3483280D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
DE8484105127T 1983-05-31 1984-05-07 Verfahren zum herstellen einer mehrschicht-halbleiteranordnung. Expired - Lifetime DE3483280D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58096126A JPS59220952A (ja) 1983-05-31 1983-05-31 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3483280D1 true DE3483280D1 (de) 1990-10-31

Family

ID=14156686

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484105127T Expired - Lifetime DE3483280D1 (de) 1983-05-31 1984-05-07 Verfahren zum herstellen einer mehrschicht-halbleiteranordnung.

Country Status (4)

Country Link
US (1) US4619037A (de)
EP (1) EP0127020B1 (de)
JP (1) JPS59220952A (de)
DE (1) DE3483280D1 (de)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0618213B2 (ja) * 1982-06-25 1994-03-09 松下電子工業株式会社 半導体装置の製造方法
JPH0680660B2 (ja) * 1984-01-23 1994-10-12 沖電気工業株式会社 半導体装置の製造方法
US5087591A (en) * 1985-01-22 1992-02-11 Texas Instruments Incorporated Contact etch process
JPS61191043A (ja) * 1985-02-20 1986-08-25 Toshiba Corp 半導体装置
JPS62261156A (ja) * 1986-04-30 1987-11-13 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション 導電性バイア経路の形成方法
JPS62260340A (ja) * 1986-05-06 1987-11-12 Toshiba Corp 半導体装置の製造方法
US4696098A (en) * 1986-06-24 1987-09-29 Advanced Micro Devices, Inc. Metallization technique for integrated circuit structures
JPS63127551A (ja) * 1986-11-17 1988-05-31 Toshiba Corp 半導体装置の製造方法
US4914501A (en) * 1987-03-13 1990-04-03 Harris Corporation Vertical contact structure
JPS63237443A (ja) * 1987-03-25 1988-10-03 Mitsubishi Electric Corp 半導体装置
US4962414A (en) * 1988-02-11 1990-10-09 Sgs-Thomson Microelectronics, Inc. Method for forming a contact VIA
US4977105A (en) * 1988-03-15 1990-12-11 Mitsubishi Denki Kabushiki Kaisha Method for manufacturing interconnection structure in semiconductor device
JPH0231418A (ja) * 1988-07-21 1990-02-01 Fujitsu Ltd 半導体装置の電気的接合構造
US5196233A (en) * 1989-01-18 1993-03-23 Sgs-Thomson Microelectronics, Inc. Method for fabricating semiconductor circuits
JPH02202054A (ja) * 1989-01-31 1990-08-10 Texas Instr Japan Ltd 半導体装置及びその製造方法
US5221634A (en) * 1989-01-31 1993-06-22 Texas Instruments Incorporated Method of making semiconductor device employing self diffusion of dopant from contact member for augmenting electrical connection to doped region in substrate
US5011791A (en) * 1989-02-03 1991-04-30 Motorola, Inc. Fusible link with built-in redundancy
US4966864A (en) * 1989-03-27 1990-10-30 Motorola, Inc. Contact structure and method
KR920010129B1 (ko) * 1989-11-30 1992-11-16 현대전자산업 주식회사 콘택홀의 패턴형성방법
US5279990A (en) * 1990-03-02 1994-01-18 Motorola, Inc. Method of making a small geometry contact using sidewall spacers
US5243220A (en) * 1990-03-23 1993-09-07 Kabushiki Kaisha Toshiba Semiconductor device having miniaturized contact electrode and wiring structure
US5151387A (en) 1990-04-30 1992-09-29 Sgs-Thomson Microelectronics, Inc. Polycrystalline silicon contact structure
US5527561A (en) * 1991-05-28 1996-06-18 Electrotech Limited Method for filing substrate recesses using elevated temperature and pressure
GB9219268D0 (en) * 1992-09-11 1992-10-28 Inmos Ltd Semiconductor device incorporating a contact and manufacture thereof
US5439848A (en) * 1992-12-30 1995-08-08 Sharp Microelectronics Technology, Inc. Method for fabricating a self-aligned multi-level interconnect
JP2919227B2 (ja) * 1993-05-31 1999-07-12 日本電気株式会社 半導体装置及びその製造方法
US5571751A (en) * 1994-05-09 1996-11-05 National Semiconductor Corporation Interconnect structures for integrated circuits
JP2658899B2 (ja) * 1994-09-22 1997-09-30 日本電気株式会社 半導体装置の製造方法
KR0137978B1 (ko) * 1994-10-12 1998-06-15 김주용 반도체 소자 제조방법
JP2720796B2 (ja) * 1994-11-15 1998-03-04 日本電気株式会社 半導体装置の製造方法
US6740573B2 (en) 1995-02-17 2004-05-25 Micron Technology, Inc. Method for forming an integrated circuit interconnect using a dual poly process
JP3903189B2 (ja) * 1995-03-07 2007-04-11 マイクロン・テクノロジー・インコーポレーテッド Ｄｒａｍ半導体装置
US5684331A (en) * 1995-06-07 1997-11-04 Lg Semicon Co., Ltd. Multilayered interconnection of semiconductor device
US6140684A (en) * 1997-06-24 2000-10-31 Stmicroelectronic, Inc. SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers
US5895264A (en) * 1997-07-30 1999-04-20 Chartered Semiconductor Manufacturing Ltd. Method for forming stacked polysilicon
US7071557B2 (en) * 1999-09-01 2006-07-04 Micron Technology, Inc. Metallization structures for semiconductor device interconnects, methods for making same, and semiconductor devices including same
US6461963B1 (en) * 2000-08-30 2002-10-08 Micron Technology, Inc. Utilization of disappearing silicon hard mask for fabrication of semiconductor structures

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1473197A (fr) * 1965-01-27 1967-03-17 Texas Instruments Inc Procédé de formation de connexions électriques, et pièces en résultant
US3323198A (en) * 1965-01-27 1967-06-06 Texas Instruments Inc Electrical interconnections
US3382568A (en) * 1965-07-22 1968-05-14 Ibm Method for providing electrical connections to semiconductor devices
US3865624A (en) * 1970-06-29 1975-02-11 Bell Telephone Labor Inc Interconnection of electrical devices
US3881971A (en) * 1972-11-29 1975-05-06 Ibm Method for fabricating aluminum interconnection metallurgy system for silicon devices
US4265935A (en) * 1977-04-28 1981-05-05 Micro Power Systems Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
US4184909A (en) * 1978-08-21 1980-01-22 International Business Machines Corporation Method of forming thin film interconnection systems
JPS57194551A (en) * 1981-05-26 1982-11-30 Toshiba Corp Manufacture of semiconductor device
US4428111A (en) * 1981-12-07 1984-01-31 Bell Telephone Laboratories, Incorporated Microwave transistor

Also Published As

Publication number Publication date
EP0127020A3 (en) 1987-08-26
JPS59220952A (ja) 1984-12-12
EP0127020B1 (de) 1990-09-26
EP0127020A2 (de) 1984-12-05
US4619037A (en) 1986-10-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee