DE3483531D1 - Verfahren zum herstellen einer integrierten halbleiterschaltkreisanordnung mit einem misfet. - Google Patents

Verfahren zum herstellen einer integrierten halbleiterschaltkreisanordnung mit einem misfet.

Info

Publication number
DE3483531D1
DE3483531D1 DE8484116283T DE3483531T DE3483531D1 DE 3483531 D1 DE3483531 D1 DE 3483531D1 DE 8484116283 T DE8484116283 T DE 8484116283T DE 3483531 T DE3483531 T DE 3483531T DE 3483531 D1 DE3483531 D1 DE 3483531D1
Authority
DE
Germany
Prior art keywords
misfet
producing
circuit arrangement
semiconductor circuit
integrated semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8484116283T
Other languages
English (en)
Inventor
Kousuke Hitachi-Nishik Okuyama
Norio Hitachi-Maehara-R Suzuki
Satoshi Meguro
Kouichi Nagasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=12820022&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=DE3483531(D1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE3483531D1 publication Critical patent/DE3483531D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
DE8484116283T 1984-03-16 1984-12-24 Verfahren zum herstellen einer integrierten halbleiterschaltkreisanordnung mit einem misfet. Expired - Lifetime DE3483531D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59049042A JPH0693494B2 (ja) 1984-03-16 1984-03-16 半導体集積回路装置の製造方法

Publications (1)

Publication Number Publication Date
DE3483531D1 true DE3483531D1 (de) 1990-12-06

Family

ID=12820022

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484116283T Expired - Lifetime DE3483531D1 (de) 1984-03-16 1984-12-24 Verfahren zum herstellen einer integrierten halbleiterschaltkreisanordnung mit einem misfet.

Country Status (7)

Country Link
US (1) US4637124A (de)
EP (1) EP0164449B1 (de)
JP (1) JPH0693494B2 (de)
KR (1) KR850006656A (de)
DE (1) DE3483531D1 (de)
HK (1) HK20993A (de)
SG (1) SG102592G (de)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5276346A (en) * 1983-12-26 1994-01-04 Hitachi, Ltd. Semiconductor integrated circuit device having protective/output elements and internal circuits
US5610089A (en) * 1983-12-26 1997-03-11 Hitachi, Ltd. Method of fabrication of semiconductor integrated circuit device
JPH0695563B2 (ja) * 1985-02-01 1994-11-24 株式会社日立製作所 半導体装置
JPS60241256A (ja) * 1984-05-16 1985-11-30 Hitachi Ltd 半導体装置およびその製造方法
JPS61263137A (ja) * 1985-05-07 1986-11-21 Hitachi Ltd 半導体装置
US4843023A (en) * 1985-09-25 1989-06-27 Hewlett-Packard Company Process for forming lightly-doped-drain (LDD) without extra masking steps
ES2033241T5 (es) * 1985-12-04 1998-02-16 Advanced Micro Devices Inc Transistores de efecto de campo.
US4735911A (en) * 1985-12-17 1988-04-05 Siemens Aktiengesellschaft Process for the simultaneous production of bipolar and complementary MOS transistors on a common silicon substrate
JPH0831602B2 (ja) * 1986-06-30 1996-03-27 沖電気工業株式会社 Ｍｉｓ型電界効果トランジスタの製造方法
US5215936A (en) * 1986-10-09 1993-06-01 Kabushiki Kaisha Toshiba Method of fabricating a semiconductor device having a lightly-doped drain structure
US4978628A (en) * 1986-11-19 1990-12-18 Teledyne Industries, Inc. Drail-well/extension high voltage MOS transistor structure and method of fabrication
US4801555A (en) * 1987-01-14 1989-01-31 Motorola, Inc. Double-implant process for forming graded source/drain regions
JPS63302566A (ja) * 1987-06-02 1988-12-09 Sanyo Electric Co Ltd Ｍｏｓ半導体装置の製造方法
JPS63302565A (ja) * 1987-06-02 1988-12-09 Sanyo Electric Co Ltd Ｍｏｓ半導体装置の製造方法
JPS63302567A (ja) * 1987-06-02 1988-12-09 Sanyo Electric Co Ltd Ｍｏｓ半導体装置の製造方法
JPS63302568A (ja) * 1987-06-02 1988-12-09 Sanyo Electric Co Ltd Ｍｏｓ半導体装置の製造方法
US4771014A (en) * 1987-09-18 1988-09-13 Sgs-Thomson Microelectronics, Inc. Process for manufacturing LDD CMOS devices
IT1223571B (it) * 1987-12-21 1990-09-19 Sgs Thomson Microelectronics Procedimento per la fabbricazione di dispositivi integrati cmos con lunghezze di porta ridotte
JPH01175260A (ja) * 1987-12-29 1989-07-11 Nec Corp 絶縁ゲート電界効果トランジスタの製造方法
JPH01189962A (ja) * 1988-01-26 1989-07-31 Seiko Instr & Electron Ltd 半導体集積回路装置の製造方法
US5075249A (en) * 1988-04-04 1991-12-24 Fujitsu Limited Method of making a bic memory cell having contact openings with straight sidewalls and sharp-edge rims
US5006477A (en) * 1988-11-25 1991-04-09 Hughes Aircraft Company Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices
EP0405293B1 (de) * 1989-06-27 1996-08-21 National Semiconductor Corporation Silicid-Übereinstimmendes CMOS-Verfahren mit einer differenzierten Oxid-Implantierungsmaske
US5021353A (en) * 1990-02-26 1991-06-04 Micron Technology, Inc. Split-polysilicon CMOS process incorporating self-aligned silicidation of conductive regions
JPH0434968A (ja) * 1990-05-30 1992-02-05 Mitsubishi Electric Corp 相補型電界効果トランジスタおよびその製造方法
KR100233558B1 (ko) * 1996-06-29 1999-12-01 김영환 반도체 소자의 제조방법
US5943565A (en) * 1997-09-05 1999-08-24 Advanced Micro Devices, Inc. CMOS processing employing separate spacers for independently optimized transistor performance
US7880173B2 (en) * 2002-06-28 2011-02-01 National Institute Of Advanced Industrial Science And Technology Semiconductor device and method of manufacturing same
US9293577B2 (en) * 2010-03-30 2016-03-22 Volterra Semiconductor LLC LDMOS with no reverse recovery

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4356623A (en) * 1980-09-15 1982-11-02 Texas Instruments Incorporated Fabrication of submicron semiconductor devices
US4366613A (en) * 1980-12-17 1983-01-04 Ibm Corporation Method of fabricating an MOS dynamic RAM with lightly doped drain
JPS5879766A (ja) * 1981-11-06 1983-05-13 Nec Corp Ｍｏｓ型半導体装置の製造法
JPS58159345A (ja) * 1982-03-18 1983-09-21 Toshiba Corp 半導体装置及びその製造方法
JPS58201362A (ja) * 1982-05-20 1983-11-24 Toshiba Corp 半導体装置の製造方法
JPS5952849A (ja) * 1982-09-20 1984-03-27 Fujitsu Ltd 半導体装置の製造方法
US4536944A (en) * 1982-12-29 1985-08-27 International Business Machines Corporation Method of making ROM/PLA semiconductor device by late stage personalization
JPS59138379A (ja) * 1983-01-27 1984-08-08 Toshiba Corp 半導体装置の製造方法
DE3314450A1 (de) * 1983-04-21 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen

Also Published As

Publication number Publication date
JPS60194568A (ja) 1985-10-03
SG102592G (en) 1992-12-24
EP0164449A2 (de) 1985-12-18
KR850006656A (ko) 1985-10-14
JPH0693494B2 (ja) 1994-11-16
HK20993A (en) 1993-03-19
EP0164449B1 (de) 1990-10-31
EP0164449A3 (en) 1987-01-07
US4637124A (en) 1987-01-20

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8365 Fully valid after opposition proceedings
8339 Ceased/non-payment of the annual fee