DE3586109D1 - Verfahren zum herstellen einer verbindungsstruktur von einer halbleiteranordnung. - Google Patents
Verfahren zum herstellen einer verbindungsstruktur von einer halbleiteranordnung.Info
- Publication number
- DE3586109D1 DE3586109D1 DE8585300829T DE3586109T DE3586109D1 DE 3586109 D1 DE3586109 D1 DE 3586109D1 DE 8585300829 T DE8585300829 T DE 8585300829T DE 3586109 T DE3586109 T DE 3586109T DE 3586109 D1 DE3586109 D1 DE 3586109D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- connection structure
- semiconductor arrangement
- semiconductor
- arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59021835A JPS60173856A (ja) | 1984-02-10 | 1984-02-10 | 半導体装置の製造方法 |
JP59223351A JPS61116858A (ja) | 1984-10-24 | 1984-10-24 | 層間絶縁膜の形成方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3586109D1 true DE3586109D1 (de) | 1992-07-02 |
Family
ID=26358958
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585300829T Expired - Fee Related DE3586109D1 (de) | 1984-02-10 | 1985-02-08 | Verfahren zum herstellen einer verbindungsstruktur von einer halbleiteranordnung. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4654113A (de) |
EP (1) | EP0154419B1 (de) |
KR (1) | KR900004968B1 (de) |
DE (1) | DE3586109D1 (de) |
Families Citing this family (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2588417B1 (fr) * | 1985-10-03 | 1988-07-29 | Bull Sa | Procede de formation d'un reseau metallique multicouche d'interconnexion des composants d'un circuit integre de haute densite et circuit integre en resultant |
FR2588418B1 (fr) * | 1985-10-03 | 1988-07-29 | Bull Sa | Procede de formation d'un reseau metallique multicouche d'interconnexion des composants d'un circuit integre de haute densite et circuit integre en resultant |
US4676867A (en) * | 1986-06-06 | 1987-06-30 | Rockwell International Corporation | Planarization process for double metal MOS using spin-on glass as a sacrificial layer |
KR880005661A (ko) * | 1986-10-17 | 1988-06-29 | 아르레뜨 다낭제 | 반도체 집적회로 소자 제조 공정 |
US4966865A (en) * | 1987-02-05 | 1990-10-30 | Texas Instruments Incorporated | Method for planarization of a semiconductor device prior to metallization |
US4795722A (en) * | 1987-02-05 | 1989-01-03 | Texas Instruments Incorporated | Method for planarization of a semiconductor device prior to metallization |
US4824521A (en) * | 1987-04-01 | 1989-04-25 | Fairchild Semiconductor Corporation | Planarization of metal pillars on uneven substrates |
JPH0654774B2 (ja) * | 1987-11-30 | 1994-07-20 | 株式会社東芝 | 半導体装置及びその製造方法 |
US5055423A (en) * | 1987-12-28 | 1991-10-08 | Texas Instruments Incorporated | Planarized selective tungsten metallization system |
JPH063804B2 (ja) * | 1988-01-21 | 1994-01-12 | シャープ株式会社 | 半導体装置製造方法 |
EP0326293A1 (de) * | 1988-01-27 | 1989-08-02 | Advanced Micro Devices, Inc. | Methode zur Ausbildung von Verbindungen |
US4894351A (en) * | 1988-02-16 | 1990-01-16 | Sprague Electric Company | Method for making a silicon IC with planar double layer metal conductors system |
GB2216336A (en) * | 1988-03-30 | 1989-10-04 | Philips Nv | Forming insulating layers on substrates |
JP2556138B2 (ja) * | 1989-06-30 | 1996-11-20 | 日本電気株式会社 | 半導体装置の製造方法 |
US5166771A (en) * | 1990-01-12 | 1992-11-24 | Paradigm Technology, Inc. | Self-aligning contact and interconnect structure |
US5483104A (en) * | 1990-01-12 | 1996-01-09 | Paradigm Technology, Inc. | Self-aligning contact and interconnect structure |
JP3128811B2 (ja) * | 1990-08-07 | 2001-01-29 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
JPH0499057A (ja) * | 1990-08-07 | 1992-03-31 | Seiko Epson Corp | 半導体装置とその製造方法 |
JPH04282832A (ja) * | 1990-10-23 | 1992-10-07 | Samsung Electron Co Ltd | 半導体装置の平坦化方法および半導体装置 |
US5162261A (en) * | 1990-12-05 | 1992-11-10 | Texas Instruments Incorporated | Method of forming a via having sloped sidewalls |
US5932289A (en) | 1991-05-28 | 1999-08-03 | Trikon Technologies Limited | Method for filling substrate recesses using pressure and heat treatment |
JP2913918B2 (ja) * | 1991-08-26 | 1999-06-28 | 日本電気株式会社 | 半導体装置の製造方法 |
DE69228099T2 (de) * | 1991-09-23 | 1999-05-20 | Sgs Thomson Microelectronics | Verfahren zur Herstellung von Sacklöchern und hergestellte Struktur |
US5276126A (en) * | 1991-11-04 | 1994-01-04 | Ocg Microelectronic Materials, Inc. | Selected novolak resin planarization layer for lithographic applications |
KR950011555B1 (ko) * | 1992-06-16 | 1995-10-06 | 현대전자산업주식회사 | 반도체 접속장치 및 그 제조방법 |
KR960009100B1 (en) * | 1993-03-02 | 1996-07-10 | Hyundai Electronics Ind | Manufacturing method of minute contact hole for highly integrated device |
US5470801A (en) * | 1993-06-28 | 1995-11-28 | Lsi Logic Corporation | Low dielectric constant insulation layer for integrated circuit structure and method of making same |
US5324689A (en) * | 1993-07-28 | 1994-06-28 | Taiwan Semiconductor Manufacturing Company | Critical dimension control with a planarized underlayer |
US5847457A (en) * | 1993-11-12 | 1998-12-08 | Stmicroelectronics, Inc. | Structure and method of forming vias |
US5508234A (en) * | 1994-10-31 | 1996-04-16 | International Business Machines Corporation | Microcavity structures, fabrication processes, and applications thereof |
US5817571A (en) * | 1996-06-10 | 1998-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multilayer interlevel dielectrics using phosphorus-doped glass |
JP3264196B2 (ja) * | 1996-12-02 | 2002-03-11 | ヤマハ株式会社 | 絶縁膜平坦化法 |
JPH10321631A (ja) | 1997-05-19 | 1998-12-04 | Oki Electric Ind Co Ltd | 半導体装置およびその製造方法 |
US6294456B1 (en) * | 1998-11-27 | 2001-09-25 | Taiwan Semiconductor Manufacturing Company | Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule |
JP4917225B2 (ja) * | 2001-09-28 | 2012-04-18 | ローム株式会社 | 半導体装置 |
US20090230557A1 (en) * | 2008-03-17 | 2009-09-17 | Infineon Technologies Ag | Semiconductor Device and Method for Making Same |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3065150D1 (en) * | 1979-06-21 | 1983-11-10 | Fujitsu Ltd | Improved electronic device having multilayer wiring structure |
US4222792A (en) * | 1979-09-10 | 1980-09-16 | International Business Machines Corporation | Planar deep oxide isolation process utilizing resin glass and E-beam exposure |
US4451326A (en) * | 1983-09-07 | 1984-05-29 | Advanced Micro Devices, Inc. | Method for interconnecting metallic layers |
-
1985
- 1985-02-06 KR KR1019850000744A patent/KR900004968B1/ko not_active IP Right Cessation
- 1985-02-06 US US06/698,901 patent/US4654113A/en not_active Expired - Lifetime
- 1985-02-08 EP EP85300829A patent/EP0154419B1/de not_active Expired - Lifetime
- 1985-02-08 DE DE8585300829T patent/DE3586109D1/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0154419A3 (en) | 1988-05-04 |
KR850006258A (ko) | 1985-10-02 |
US4654113A (en) | 1987-03-31 |
EP0154419B1 (de) | 1992-05-27 |
EP0154419A2 (de) | 1985-09-11 |
KR900004968B1 (ko) | 1990-07-12 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3586109D1 (de) | Verfahren zum herstellen einer verbindungsstruktur von einer halbleiteranordnung. | |
DE3686600D1 (de) | Verfahren zum herstellen einer harzumhuellten halbleiteranordnung. | |
DE3583934D1 (de) | Verfahren zum herstellen einer halbleiterverbundanordnung. | |
DE3780369T2 (de) | Verfahren zum herstellen einer halbleiterstruktur. | |
DE3584757D1 (de) | Verfahren zum herstellen einer zwei-wannen-cmos-halbleiterstruktur. | |
DE3586732T2 (de) | Verfahren zum herstellen einer dreidimentionaler halbleiteranordung. | |
DE3587231T2 (de) | Verfahren zum herstellen einer dmos-halbleiteranordnung. | |
DE3483579D1 (de) | Verfahren zum herstellen einer leiterbahn. | |
DE3779672T2 (de) | Verfahren zum herstellen einer monokristallinen halbleiterschicht. | |
DE3483280D1 (de) | Verfahren zum herstellen einer mehrschicht-halbleiteranordnung. | |
DE3686453D1 (de) | Verfahren zum herstellen einer duennen halbleiterschicht. | |
DE3583472D1 (de) | Verfahren zum herstellen einer halbleiteranordnung mit gateelektrode. | |
DE3786914T2 (de) | Verfahren zum herstellen einer integrierten schaltungspackungsstruktur. | |
DE3685970D1 (de) | Verfahren zum herstellen eines halbleiterbauelements. | |
DE3577371D1 (de) | Apparat zum herstellen einer halbleiteranordnung. | |
DE3578614D1 (de) | Verfahren zum herstellen von chip-einfuegungsschichten. | |
DE3381509D1 (de) | Verfahren zum herstellen von halbleiteranordnungen. | |
DE3684676D1 (de) | Verfahren zum herstellen von halbleitersubstraten. | |
DE3579174D1 (de) | Verfahren zum herstellen einer halbleiterspeicherstruktur und halbleiterspeicherstruktur. | |
DE3483531D1 (de) | Verfahren zum herstellen einer integrierten halbleiterschaltkreisanordnung mit einem misfet. | |
DE3778639D1 (de) | Verfahren zum stapelverbinden von draehten. | |
DE3671583D1 (de) | Verfahren zum herstellen eines halbleiter-speicherbauelementes. | |
DE3671324D1 (de) | Verfahren zum herstellen einer halbleiteranordnung. | |
DE3777522D1 (de) | Verfahren zum herstellen einer gemischten struktur fuer halbleiteranordnung. | |
DE68906034D1 (de) | Verfahren zum herstellen einer halbleiteranordnung. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8363 | Opposition against the patent | ||
8365 | Fully valid after opposition proceedings | ||
8339 | Ceased/non-payment of the annual fee |