DE3585180D1 - Verfahren zum herstellen einer halbleiteranordnung mit leiterschichten. - Google Patents

Verfahren zum herstellen einer halbleiteranordnung mit leiterschichten.

Info

Publication number
DE3585180D1
DE3585180D1 DE8585108953T DE3585180T DE3585180D1 DE 3585180 D1 DE3585180 D1 DE 3585180D1 DE 8585108953 T DE8585108953 T DE 8585108953T DE 3585180 T DE3585180 T DE 3585180T DE 3585180 D1 DE3585180 D1 DE 3585180D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor arrangement
layer layers
layers
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585108953T
Other languages
English (en)
Inventor
Yoshio Honma
Sukeyoshi Tsunekawa
Natsuki Yokoyama
Hiroshi Morisaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE3585180D1 publication Critical patent/DE3585180D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
DE8585108953T 1984-07-18 1985-07-17 Verfahren zum herstellen einer halbleiteranordnung mit leiterschichten. Expired - Lifetime DE3585180D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59147510A JPH069199B2 (ja) 1984-07-18 1984-07-18 配線構造体およびその製造方法

Publications (1)

Publication Number Publication Date
DE3585180D1 true DE3585180D1 (de) 1992-02-27

Family

ID=15431982

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585108953T Expired - Lifetime DE3585180D1 (de) 1984-07-18 1985-07-17 Verfahren zum herstellen einer halbleiteranordnung mit leiterschichten.

Country Status (5)

Country Link
US (1) US4792842A (de)
EP (1) EP0168828B1 (de)
JP (1) JPH069199B2 (de)
KR (1) KR930007836B1 (de)
DE (1) DE3585180D1 (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900005785B1 (ko) * 1985-05-13 1990-08-11 닛뽄덴신덴와 가부시끼가이샤 평탄성 박막의 제조방법
US4884123A (en) * 1987-02-19 1989-11-28 Advanced Micro Devices, Inc. Contact plug and interconnect employing a barrier lining and a backfilled conductor material
US5175608A (en) * 1987-06-30 1992-12-29 Hitachi, Ltd. Method of and apparatus for sputtering, and integrated circuit device
EP0300414B1 (de) * 1987-07-20 1994-10-12 Nippon Telegraph And Telephone Corporation Methode zur Verbindung von Leitungen durch Verbindungslöcher
JPS6482547A (en) * 1987-09-24 1989-03-28 Tadahiro Omi Semiconductor device
JPH0680736B2 (ja) * 1987-10-21 1994-10-12 工業技術院長 配線の形成方法
US5132775A (en) * 1987-12-11 1992-07-21 Texas Instruments Incorporated Methods for and products having self-aligned conductive pillars on interconnects
US5055423A (en) * 1987-12-28 1991-10-08 Texas Instruments Incorporated Planarized selective tungsten metallization system
US5266835A (en) * 1988-02-02 1993-11-30 National Semiconductor Corporation Semiconductor structure having a barrier layer disposed within openings of a dielectric layer
FR2634317A1 (fr) * 1988-07-12 1990-01-19 Philips Nv Procede pour fabriquer un dispositif semiconducteur ayant au moins un niveau de prise de contact a travers des ouvertures de contact de petites dimensions
JPH02178923A (ja) * 1988-12-29 1990-07-11 Fujitsu Ltd 半導体装置の製造方法
JP2537413B2 (ja) * 1989-03-14 1996-09-25 三菱電機株式会社 半導体装置およびその製造方法
US6242811B1 (en) 1989-11-30 2001-06-05 Stmicroelectronics, Inc. Interlevel contact including aluminum-refractory metal alloy formed during aluminum deposition at an elevated temperature
US6271137B1 (en) 1989-11-30 2001-08-07 Stmicroelectronics, Inc. Method of producing an aluminum stacked contact/via for multilayer
US5108951A (en) * 1990-11-05 1992-04-28 Sgs-Thomson Microelectronics, Inc. Method for forming a metal contact
US5472912A (en) * 1989-11-30 1995-12-05 Sgs-Thomson Microelectronics, Inc. Method of making an integrated circuit structure by using a non-conductive plug
US5658828A (en) * 1989-11-30 1997-08-19 Sgs-Thomson Microelectronics, Inc. Method for forming an aluminum contact through an insulating layer
US6287963B1 (en) 1990-11-05 2001-09-11 Stmicroelectronics, Inc. Method for forming a metal contact
KR100214036B1 (ko) * 1991-02-19 1999-08-02 이데이 노부유끼 알루미늄계 배선형성방법
JP2946978B2 (ja) * 1991-11-29 1999-09-13 ソニー株式会社 配線形成方法
US6051490A (en) * 1991-11-29 2000-04-18 Sony Corporation Method of forming wirings
DE69319993T2 (de) * 1992-09-22 1998-12-10 Sgs-Thomson Microelectronics, Inc., Carrollton, Tex. Methode zur Herstellung eines Metallkontaktes
US5356836A (en) * 1993-08-19 1994-10-18 Industrial Technology Research Institute Aluminum plug process
USRE36475E (en) 1993-09-15 1999-12-28 Hyundai Electronics Industries Co., Ltd. Method of forming a via plug in a semiconductor device
US5409861A (en) * 1993-09-15 1995-04-25 Hyundai Electronics Industries Co., Ltd. Method of forming a via plug in a semiconductor device
KR100281887B1 (ko) * 1994-01-18 2001-03-02 윤종용 반도체장치의 제조방법
SG42438A1 (en) * 1995-09-27 1997-08-15 Motorola Inc Process for fabricating a CVD aluminium layer in a semiconductor device
US5730835A (en) * 1996-01-31 1998-03-24 Micron Technology, Inc. Facet etch for improved step coverage of integrated circuit contacts
US6420786B1 (en) 1996-02-02 2002-07-16 Micron Technology, Inc. Conductive spacer in a via
US6376781B1 (en) 1996-05-03 2002-04-23 Micron Technology, Inc. Low resistance contacts fabricated in high aspect ratio openings by resputtering
US5929526A (en) * 1997-06-05 1999-07-27 Micron Technology, Inc. Removal of metal cusp for improved contact fill
US7253109B2 (en) 1997-11-26 2007-08-07 Applied Materials, Inc. Method of depositing a tantalum nitride/tantalum diffusion barrier layer system
WO1999027579A1 (en) * 1997-11-26 1999-06-03 Applied Materials, Inc. Damage-free sculptured coating deposition
US6274486B1 (en) 1998-09-02 2001-08-14 Micron Technology, Inc. Metal contact and process
US6423626B1 (en) 1998-11-02 2002-07-23 Micron Technology, Inc. Removal of metal cusp for improved contact fill
US6261946B1 (en) * 1999-01-05 2001-07-17 Advanced Micro Devices, Inc. Method for forming semiconductor seed layers by high bias deposition
US6537427B1 (en) 1999-02-04 2003-03-25 Micron Technology, Inc. Deposition of smooth aluminum films
US9240378B2 (en) * 2014-05-16 2016-01-19 Taiwan Semiconductor Manufacturing Company Ltd. Method of forming a copper layer using physical vapor deposition

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS543480A (en) * 1977-06-09 1979-01-11 Fujitsu Ltd Manufacture of semiconductor device
US4161430A (en) * 1978-12-04 1979-07-17 Burroughs Corporation Method of forming integrated circuit metal interconnect structure employing molybdenum on aluminum
US4158613A (en) * 1978-12-04 1979-06-19 Burroughs Corporation Method of forming a metal interconnect structure for integrated circuits
JPS58108738A (ja) * 1981-12-22 1983-06-28 Seiko Instr & Electronics Ltd 半導体装置用電極の製造方法
JPS592352A (ja) * 1982-06-28 1984-01-07 Toshiba Corp 半導体装置の製造方法
FR2530383A1 (fr) * 1982-07-13 1984-01-20 Thomson Csf Circuit integre monolithique comprenant une partie logique schottky et une memoire programmable a fusibles
JPH0620067B2 (ja) * 1982-10-08 1994-03-16 株式会社東芝 半導体装置およびその製造方法
JPS60201655A (ja) * 1984-03-27 1985-10-12 Seiko Epson Corp 半導体装置

Also Published As

Publication number Publication date
EP0168828B1 (de) 1992-01-15
EP0168828A2 (de) 1986-01-22
JPS6127657A (ja) 1986-02-07
KR930007836B1 (ko) 1993-08-20
JPH069199B2 (ja) 1994-02-02
US4792842A (en) 1988-12-20
EP0168828A3 (en) 1987-08-12
KR860001495A (ko) 1986-02-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee