DE3685970T2 - Verfahren zum herstellen eines halbleiterbauelements. - Google Patents
Verfahren zum herstellen eines halbleiterbauelements.Info
- Publication number
- DE3685970T2 DE3685970T2 DE8686102226T DE3685970T DE3685970T2 DE 3685970 T2 DE3685970 T2 DE 3685970T2 DE 8686102226 T DE8686102226 T DE 8686102226T DE 3685970 T DE3685970 T DE 3685970T DE 3685970 T2 DE3685970 T2 DE 3685970T2
- Authority
- DE
- Germany
- Prior art keywords
- producing
- semiconductor component
- semiconductor
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0331—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers for lift-off processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
- H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
- H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/061—Gettering-armorphous layers
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/082—Ion implantation FETs/COMs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60030508A JPS61191070A (ja) | 1985-02-20 | 1985-02-20 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3685970D1 DE3685970D1 (de) | 1992-08-20 |
DE3685970T2 true DE3685970T2 (de) | 1993-01-14 |
Family
ID=12305752
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686102226T Expired - Fee Related DE3685970T2 (de) | 1985-02-20 | 1986-02-20 | Verfahren zum herstellen eines halbleiterbauelements. |
Country Status (4)
Country | Link |
---|---|
US (1) | US4697333A (de) |
EP (1) | EP0193117B1 (de) |
JP (1) | JPS61191070A (de) |
DE (1) | DE3685970T2 (de) |
Families Citing this family (61)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0824184B2 (ja) * | 1984-11-15 | 1996-03-06 | ソニー株式会社 | 薄膜トランジスタの製造方法 |
JPH0616556B2 (ja) * | 1987-04-14 | 1994-03-02 | 株式会社東芝 | 半導体装置 |
US4851746A (en) * | 1987-04-15 | 1989-07-25 | Republic Industries, Inc. | Sensing apparatus for automatic door |
AU599223B2 (en) * | 1987-04-15 | 1990-07-12 | Semiconductor Energy Laboratory Co. Ltd. | Superconducting ceramic pattern and its manufacturing method |
US4818711A (en) * | 1987-08-28 | 1989-04-04 | Intel Corporation | High quality oxide on an ion implanted polysilicon surface |
US5017509A (en) * | 1988-07-19 | 1991-05-21 | Regents Of The University Of California | Stand-off transmission lines and method for making same |
JPH0770727B2 (ja) * | 1989-06-16 | 1995-07-31 | 日本電装株式会社 | Misトランジスタ及び相補形misトランジスタの製造方法 |
US5170232A (en) * | 1989-08-24 | 1992-12-08 | Nec Corporation | MOS field-effect transistor with sidewall spacers |
US5043292A (en) * | 1990-05-31 | 1991-08-27 | National Semiconductor Corporation | Self-aligned masking for ultra-high energy implants with application to localized buried implants and insolation structures |
US5045486A (en) * | 1990-06-26 | 1991-09-03 | At&T Bell Laboratories | Transistor fabrication method |
JPH04241466A (ja) * | 1991-01-16 | 1992-08-28 | Casio Comput Co Ltd | 電界効果型トランジスタ |
US5187117A (en) * | 1991-03-04 | 1993-02-16 | Ixys Corporation | Single diffusion process for fabricating semiconductor devices |
US5171700A (en) * | 1991-04-01 | 1992-12-15 | Sgs-Thomson Microelectronics, Inc. | Field effect transistor structure and method |
JPH05198795A (ja) * | 1991-08-21 | 1993-08-06 | Ricoh Co Ltd | MIS型半導体素子用PolySiゲート電極 |
EP0534530B1 (de) * | 1991-09-23 | 2000-05-03 | Koninklijke Philips Electronics N.V. | Verfahren zum Herstellen einer Anordnung, bei dem ein Stoff in einen Körper implantiert wird |
US5418398A (en) * | 1992-05-29 | 1995-05-23 | Sgs-Thomson Microelectronics, Inc. | Conductive structures in integrated circuits |
IT1256362B (it) * | 1992-08-19 | 1995-12-04 | St Microelectronics Srl | Processo di realizzazione su semiconduttori di regioni impiantate a basso rischio di channeling |
US5563093A (en) * | 1993-01-28 | 1996-10-08 | Kawasaki Steel Corporation | Method of manufacturing fet semiconductor devices with polysilicon gate having large grain sizes |
US5350698A (en) * | 1993-05-03 | 1994-09-27 | United Microelectronics Corporation | Multilayer polysilicon gate self-align process for VLSI CMOS device |
US5371396A (en) * | 1993-07-02 | 1994-12-06 | Thunderbird Technologies, Inc. | Field effect transistor having polycrystalline silicon gate junction |
US6498080B1 (en) * | 1993-11-05 | 2002-12-24 | Agere Systems Guardian Corp. | Transistor fabrication method |
US5397722A (en) * | 1994-03-15 | 1995-03-14 | National Semiconductor Corporation | Process for making self-aligned source/drain polysilicon or polysilicide contacts in field effect transistors |
US5451532A (en) * | 1994-03-15 | 1995-09-19 | National Semiconductor Corp. | Process for making self-aligned polysilicon base contact in a bipolar junction transistor |
US5641708A (en) * | 1994-06-07 | 1997-06-24 | Sgs-Thomson Microelectronics, Inc. | Method for fabricating conductive structures in integrated circuits |
US5650340A (en) * | 1994-08-18 | 1997-07-22 | Sun Microsystems, Inc. | Method of making asymmetric low power MOS devices |
US5773309A (en) * | 1994-10-14 | 1998-06-30 | The Regents Of The University Of California | Method for producing silicon thin-film transistors with enhanced forward current drive |
KR960026960A (ko) * | 1994-12-16 | 1996-07-22 | 리 패치 | 비대칭 저전력 모스(mos) 소자 |
US5516711A (en) * | 1994-12-16 | 1996-05-14 | Mosel Vitelic, Inc. | Method for forming LDD CMOS with oblique implantation |
EP0750794A1 (de) * | 1995-01-17 | 1997-01-02 | National Semiconductor Corporation | Gleichzeitige implantation von arsen und phosphor in ausgedehnter drainzone für hochspannung-nmos-anordnung |
US5652156A (en) * | 1995-04-10 | 1997-07-29 | Taiwan Semiconductor Manufacturing Company Ltd. | Layered polysilicon deposition method |
US5504024A (en) * | 1995-07-14 | 1996-04-02 | United Microelectronics Corp. | Method for fabricating MOS transistors |
US6703672B1 (en) * | 1995-09-29 | 2004-03-09 | Intel Corporation | Polysilicon/amorphous silicon composite gate electrode |
US5744840A (en) * | 1995-11-20 | 1998-04-28 | Ng; Kwok Kwok | Electrostatic protection devices for protecting semiconductor integrated circuitry |
US20020197838A1 (en) * | 1996-01-16 | 2002-12-26 | Sailesh Chittipeddi | Transistor fabrication method |
US5665611A (en) * | 1996-01-31 | 1997-09-09 | Micron Technology, Inc. | Method of forming a thin film transistor using fluorine passivation |
US6346439B1 (en) | 1996-07-09 | 2002-02-12 | Micron Technology, Inc. | Semiconductor transistor devices and methods for forming semiconductor transistor devices |
JP3413823B2 (ja) * | 1996-03-07 | 2003-06-09 | 日本電気株式会社 | 半導体装置及びその製造方法 |
US5827747A (en) * | 1996-03-28 | 1998-10-27 | Mosel Vitelic, Inc. | Method for forming LDD CMOS using double spacers and large-tilt-angle ion implantation |
US5686324A (en) * | 1996-03-28 | 1997-11-11 | Mosel Vitelic, Inc. | Process for forming LDD CMOS using large-tilt-angle ion implantation |
AUPO281896A0 (en) * | 1996-10-04 | 1996-10-31 | Unisearch Limited | Reactive ion etching of silica structures for integrated optics applications |
JP3022374B2 (ja) * | 1997-02-03 | 2000-03-21 | 日本電気株式会社 | 半導体装置の製造方法 |
US6017808A (en) * | 1997-10-24 | 2000-01-25 | Lsi Logic Corporation | Nitrogen implanted polysilicon gate for MOSFET gate oxide hardening |
TW399235B (en) * | 1998-12-04 | 2000-07-21 | United Microelectronics Corp | Selective semi-sphere silicon grain manufacturing method |
US6069061A (en) * | 1999-02-08 | 2000-05-30 | United Microelectronics Corp. | Method for forming polysilicon gate |
US6743680B1 (en) | 2000-06-22 | 2004-06-01 | Advanced Micro Devices, Inc. | Process for manufacturing transistors having silicon/germanium channel regions |
US6461945B1 (en) | 2000-06-22 | 2002-10-08 | Advanced Micro Devices, Inc. | Solid phase epitaxy process for manufacturing transistors having silicon/germanium channel regions |
US6630386B1 (en) | 2000-07-18 | 2003-10-07 | Advanced Micro Devices, Inc | CMOS manufacturing process with self-amorphized source/drain junctions and extensions |
US6521502B1 (en) | 2000-08-07 | 2003-02-18 | Advanced Micro Devices, Inc. | Solid phase epitaxy activation process for source/drain junction extensions and halo regions |
US6472282B1 (en) * | 2000-08-15 | 2002-10-29 | Advanced Micro Devices, Inc. | Self-amorphized regions for transistors |
US6475869B1 (en) | 2001-02-26 | 2002-11-05 | Advanced Micro Devices, Inc. | Method of forming a double gate transistor having an epitaxial silicon/germanium channel region |
US20040201067A1 (en) * | 2002-07-08 | 2004-10-14 | Toppoly Optoelectronics Corp. | LLD structure of thin film transistor |
TW544941B (en) * | 2002-07-08 | 2003-08-01 | Toppoly Optoelectronics Corp | Manufacturing process and structure of thin film transistor |
US6605514B1 (en) | 2002-07-31 | 2003-08-12 | Advanced Micro Devices, Inc. | Planar finFET patterning using amorphous carbon |
US20040201068A1 (en) * | 2002-10-02 | 2004-10-14 | Toppoly Optoelectronics Corp. | Process for producing thin film transistor |
WO2004107450A1 (ja) * | 2003-05-30 | 2004-12-09 | Fujitsu Limited | 半導体装置と半導体装置の製造方法 |
JP4308625B2 (ja) * | 2003-11-07 | 2009-08-05 | パナソニック株式会社 | メモリ混載半導体装置及びその製造方法 |
JP2007165401A (ja) * | 2005-12-09 | 2007-06-28 | Nec Electronics Corp | 半導体装置および半導体装置の製造方法 |
US20100019324A1 (en) * | 2006-12-22 | 2010-01-28 | Hiroyuki Ohara | Manufacturing method of semiconductor device and semiconductor device |
KR102223678B1 (ko) * | 2014-07-25 | 2021-03-08 | 삼성디스플레이 주식회사 | 표시장치용 백플레인 및 그 제조 방법 |
CN105336781A (zh) * | 2014-08-07 | 2016-02-17 | 中芯国际集成电路制造(上海)有限公司 | 源漏结构及其制造方法 |
CN111129156A (zh) * | 2019-12-27 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Nmos器件的制作方法及以其制作的半导体器件 |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2837800A1 (de) * | 1978-08-30 | 1980-03-13 | Philips Patentverwaltung | Verfahren zum herstellen von halbleiterbauelementen |
JPS5771175A (en) * | 1980-10-22 | 1982-05-01 | Nec Corp | Semiconductor device |
US4442589A (en) * | 1981-03-05 | 1984-04-17 | International Business Machines Corporation | Method for manufacturing field effect transistors |
US4599118A (en) * | 1981-12-30 | 1986-07-08 | Mostek Corporation | Method of making MOSFET by multiple implantations followed by a diffusion step |
JPS59920A (ja) * | 1982-06-23 | 1984-01-06 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS5948952A (ja) * | 1982-09-14 | 1984-03-21 | Sony Corp | 抵抗体の製法 |
US4472210A (en) * | 1983-01-07 | 1984-09-18 | Rca Corporation | Method of making a semiconductor device to improve conductivity of amorphous silicon films |
JPS59138379A (ja) * | 1983-01-27 | 1984-08-08 | Toshiba Corp | 半導体装置の製造方法 |
JPS59161021A (ja) * | 1983-03-03 | 1984-09-11 | Fuji Electric Corp Res & Dev Ltd | イオン注入法 |
US4597824A (en) * | 1983-11-11 | 1986-07-01 | Kabushiki Kaisha Toshiba | Method of producing semiconductor device |
US4555842A (en) * | 1984-03-19 | 1985-12-03 | At&T Bell Laboratories | Method of fabricating VLSI CMOS devices having complementary threshold voltages |
US4584026A (en) * | 1984-07-25 | 1986-04-22 | Rca Corporation | Ion-implantation of phosphorus, arsenic or boron by pre-amorphizing with fluorine ions |
-
1985
- 1985-02-20 JP JP60030508A patent/JPS61191070A/ja active Granted
-
1986
- 1986-02-19 US US06/830,831 patent/US4697333A/en not_active Expired - Lifetime
- 1986-02-20 EP EP86102226A patent/EP0193117B1/de not_active Expired - Lifetime
- 1986-02-20 DE DE8686102226T patent/DE3685970T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH0426542B2 (de) | 1992-05-07 |
EP0193117B1 (de) | 1992-07-15 |
EP0193117A3 (en) | 1989-05-31 |
JPS61191070A (ja) | 1986-08-25 |
US4697333A (en) | 1987-10-06 |
DE3685970D1 (de) | 1992-08-20 |
EP0193117A2 (de) | 1986-09-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3685970T2 (de) | Verfahren zum herstellen eines halbleiterbauelements. | |
DE3686600D1 (de) | Verfahren zum herstellen einer harzumhuellten halbleiteranordnung. | |
DE3583934D1 (de) | Verfahren zum herstellen einer halbleiterverbundanordnung. | |
DE3686457T2 (de) | Verfahren zum herstellen eines halbleiterapparates mit zwei halbleiteranordnungen. | |
DE3785720T2 (de) | Verfahren zum herstellen eines filmtraegers. | |
DE3484481D1 (de) | Verfahren zum herstellen eines handschuhs. | |
DE3780369T2 (de) | Verfahren zum herstellen einer halbleiterstruktur. | |
DE3586732T2 (de) | Verfahren zum herstellen einer dreidimentionaler halbleiteranordung. | |
DE3671583D1 (de) | Verfahren zum herstellen eines halbleiter-speicherbauelementes. | |
DE3768912D1 (de) | Verfahren zum herstellen eines verbundwerkstoffgegenstandes. | |
DE3750325D1 (de) | Verfahren zum Herstellen eines Halbleiterbauelements. | |
DE3684676D1 (de) | Verfahren zum herstellen von halbleitersubstraten. | |
DE3679758D1 (de) | Verfahren zum herstellen eines supraleitenden hohlraumes. | |
DE3671580D1 (de) | Verfahren zum herstellen eines mehrschicht-keramiksubstrats. | |
DE3776450D1 (de) | Verfahren zum herstellen eines luftschall absorbierenden bauelements. | |
DE3673437D1 (de) | Verfahren zum herstellen eines halbleiterbauelements mit einem graben. | |
DE3580192D1 (de) | Verfahren zum herstellen eines kontaktes fuer eine halbleiteranordnung. | |
DE3671324D1 (de) | Verfahren zum herstellen einer halbleiteranordnung. | |
DE68906034D1 (de) | Verfahren zum herstellen einer halbleiteranordnung. | |
DE3683183D1 (de) | Verfahren zum herstellen eines selbtsausrichtenden bipolartransistors. | |
DE3579770D1 (de) | Verfahren zum herstellen eines eines verstaerkungsbauteils. | |
DE3675038D1 (de) | Verfahren zum herstellen eines einzelchip-mikrocomputers. | |
DE3877282T2 (de) | Verfahren zum herstellen einer halbleiter-vorrichtung. | |
DE3586019D1 (de) | Verfahren zum herstellen eines elektrostriktiven elementes. | |
DE3877601D1 (de) | Verfahren zum herstellen eines supraleitenden drahtes. |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |