DE3580192D1 - Verfahren zum herstellen eines kontaktes fuer eine halbleiteranordnung. - Google Patents

Verfahren zum herstellen eines kontaktes fuer eine halbleiteranordnung.

Info

Publication number
DE3580192D1
DE3580192D1 DE8585303878T DE3580192T DE3580192D1 DE 3580192 D1 DE3580192 D1 DE 3580192D1 DE 8585303878 T DE8585303878 T DE 8585303878T DE 3580192 T DE3580192 T DE 3580192T DE 3580192 D1 DE3580192 D1 DE 3580192D1
Authority
DE
Germany
Prior art keywords
producing
contact
semiconductor arrangement
semiconductor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585303878T
Other languages
English (en)
Inventor
Yoshimi Shioya
Yuji Furumura
Yasushi Ohyama
Shin-Ichi Inoue
Tsutomu Ogawa
Kiyoshi Watanabe
Hiroshi Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59112219A external-priority patent/JPS6110233A/ja
Priority claimed from JP59135444A external-priority patent/JPS6122651A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3580192D1 publication Critical patent/DE3580192D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/026—Deposition thru hole in mask

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8585303878T 1984-06-02 1985-05-31 Verfahren zum herstellen eines kontaktes fuer eine halbleiteranordnung. Expired - Fee Related DE3580192D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59112219A JPS6110233A (ja) 1984-06-02 1984-06-02 半導体装置の製造方法
JP59135444A JPS6122651A (ja) 1984-06-29 1984-06-29 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3580192D1 true DE3580192D1 (de) 1990-11-29

Family

ID=26451441

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585303878T Expired - Fee Related DE3580192D1 (de) 1984-06-02 1985-05-31 Verfahren zum herstellen eines kontaktes fuer eine halbleiteranordnung.

Country Status (4)

Country Link
US (1) US4906593A (de)
EP (1) EP0164976B1 (de)
KR (1) KR900008387B1 (de)
DE (1) DE3580192D1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62126632A (ja) * 1985-11-27 1987-06-08 Toshiba Corp 半導体装置の製造方法
US4751101A (en) * 1987-04-30 1988-06-14 International Business Machines Corporation Low stress tungsten films by silicon reduction of WF6
US5212400A (en) * 1988-02-18 1993-05-18 International Business Machines Corporation Method of depositing tungsten on silicon in a non-self-limiting CVD process and semiconductor device manufactured thereby
US5071788A (en) * 1988-02-18 1991-12-10 International Business Machines Corporation Method for depositing tungsten on silicon in a non-self-limiting CVD process and semiconductor device manufactured thereby
JPH0691108B2 (ja) * 1988-03-22 1994-11-14 インタ‐ナシヨナル・ビジネス・マシ‐ンズ・コ‐ポレ‐シヨン 薄膜電界効果トランジスタの製造方法
US5168089A (en) * 1989-11-27 1992-12-01 At&T Bell Laboratories Substantially facet-free selective epitaxial growth process
US4975386A (en) * 1989-12-22 1990-12-04 Micro Power Systems, Inc. Process enhancement using molybdenum plugs in fabricating integrated circuits
US5082792A (en) * 1990-08-15 1992-01-21 Lsi Logic Corporation Forming a physical structure on an integrated circuit device and determining its size by measurement of resistance
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
US5252503A (en) * 1991-06-06 1993-10-12 Lsi Logic Corporation Techniques for forming isolation structures
KR950012918B1 (ko) * 1991-10-21 1995-10-23 현대전자산업주식회사 선택적 텅스텐 박막의 2단계 퇴적에 의한 콘택 매립방법
KR960006693B1 (ko) * 1992-11-24 1996-05-22 현대전자산업주식회사 고집적 반도체 접속장치 및 그 제조방법
US5447880A (en) * 1992-12-22 1995-09-05 At&T Global Information Solutions Company Method for forming an amorphous silicon programmable element
JP2503878B2 (ja) * 1993-06-14 1996-06-05 日本電気株式会社 半導体集積回路装置及びその製造方法
EP0651436A1 (de) 1993-10-22 1995-05-03 AT&T Corp. Verfahren zur Herstellung von Leitern aus Wolfram für integrierte Halbleiter-Schaltkreise
US5430328A (en) * 1994-05-31 1995-07-04 United Microelectronics Corporation Process for self-align contact
WO2013144024A1 (en) * 2012-03-28 2013-10-03 Alstom Technology Ltd Method for separating a metal part from a ceramic part

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3717514A (en) * 1970-10-06 1973-02-20 Motorola Inc Single crystal silicon contact for integrated circuits and method for making same
EP0057738B1 (de) * 1981-02-07 1986-10-15 Ibm Deutschland Gmbh Verfahren zum Herstellen und Füllen von Löchern in einer auf einem Substrat aufliegenden Schicht
US4343676A (en) * 1981-03-26 1982-08-10 Rca Corporation Etching a semiconductor material and automatically stopping same
JPS584924A (ja) * 1981-07-01 1983-01-12 Hitachi Ltd 半導体装置の電極形成方法
US4392298A (en) * 1981-07-27 1983-07-12 Bell Telephone Laboratories, Incorporated Integrated circuit device connection process
US4517225A (en) * 1983-05-02 1985-05-14 Signetics Corporation Method for manufacturing an electrical interconnection by selective tungsten deposition
US4540607A (en) * 1983-08-08 1985-09-10 Gould, Inc. Selective LPCVD tungsten deposition by the silicon reduction method
US4532702A (en) * 1983-11-04 1985-08-06 Westinghouse Electric Corp. Method of forming conductive interconnection between vertically spaced levels in VLSI devices

Also Published As

Publication number Publication date
EP0164976A3 (en) 1987-09-02
US4906593A (en) 1990-03-06
KR860000710A (ko) 1986-01-30
EP0164976B1 (de) 1990-10-24
KR900008387B1 (ko) 1990-11-17
EP0164976A2 (de) 1985-12-18

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee